WO2007042071A1 - Bloc de composants comprenant au moins deux elements cooperant de maniere electroconductrice et procede permettant de produire ledit bloc de composants - Google Patents
Bloc de composants comprenant au moins deux elements cooperant de maniere electroconductrice et procede permettant de produire ledit bloc de composants Download PDFInfo
- Publication number
- WO2007042071A1 WO2007042071A1 PCT/EP2005/055133 EP2005055133W WO2007042071A1 WO 2007042071 A1 WO2007042071 A1 WO 2007042071A1 EP 2005055133 W EP2005055133 W EP 2005055133W WO 2007042071 A1 WO2007042071 A1 WO 2007042071A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- components
- semiconductor chip
- assembly
- component
- assembly according
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2405—Shape
- H01L2224/24051—Conformal with the semiconductor or solid-state device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24101—Connecting bonding areas at the same height
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24105—Connecting bonding areas at different heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
- H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/24998—Reinforcing structures, e.g. ramp-like support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2512—Layout
- H01L2224/25171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2512—Layout
- H01L2224/25175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/76—Apparatus for connecting with build-up interconnects
- H01L2224/7615—Means for depositing
- H01L2224/76151—Means for direct writing
- H01L2224/76152—Syringe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10439—Position of a single component
- H05K2201/10477—Inverted
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0126—Dispenser, e.g. for solder paste, for supplying conductive paste for screen printing or for filling holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
Definitions
- the invention relates to an assembly and a method for producing an assembly according to the preamble of claim 1 or claim 13.
- Such assemblies are used in numerous applications, for example in microelectronics.
- connection string is versatile. Different and varying heights of the components can be advantageously compensated.
- the assembly is characterized by a robust construction, whereby it can withstand high acceleration forces, for example.
- the connecting strand may be curable by using heat and / or by light, in particular by UV light.
- a cured connecting strand is characterized by advantageous mechanical, thermal and electrical properties.
- a further aspect of the invention in terms of the device relates to an assembly having at least two components in electrically conductive connection, whose sides, in particular their tops and / or end faces for the operative connection, are connected to one another by at least one contact means extending along a line.
- the contact means is an electrically conductive connecting strand, which is obtainable by applying a mass in pasty or liquid form and curing of the mass. Applying is understood to mean a process for the continuous application of a pasty or liquid mass.
- the mass may contain electrically conductive particles, for example particles of silver, gold or another (metallic or non-metallic) material.
- electrically conductive particles for example particles of silver, gold or another (metallic or non-metallic) material.
- electrically conductive compounds are described for example in DE-A1-1028844.
- the composition may be based on a resin, for example an epoxy resin. Silicones can also be used. Commercially available adhesives are also suitable as the basis for the composition. These can be selected according to the desired dispensability and curing behavior. Depending on the application area can transparent or non-transparent adhesives or other materials can be used as the basis for the connecting strand.
- one of the components is a semiconductor chip, particularly preferably an unhoused semiconductor chip (die).
- At least one of the components that are in electrical connection therewith may be a component, in particular a substrate or a further semiconductor chip.
- the substrate used may preferably be a rigid or flexible circuit carrier or a metallic leadframe.
- a “die” is, for example, an LED die or a laser diode chip, In such applications, an optically transparent electrically conductive connecting strand could be particularly suitable.
- connection strand can - similar to wire bonding - be protected in a further subsequent process step with a potting compound together with the semiconductor chip from the effects of the environment.
- the assembly may therefore comprise a protective sheath of a potting compound, which surrounds at least the semiconductor chip and the connecting strand in whole or in part.
- Such an encapsulation gives the assembly in particular a higher mechanical stability and thermal capacity.
- other methods for protecting the components of microelectronic assemblies are also known.
- the connecting strand can run at least in sections on free upper sides of the components.
- This arrangement has the advantage that the risk of mechanical damage can be massively reduced.
- the connection string can be from an end point arranged on an upper side of one of the components, in particular on a chip top of a semiconductor chip, to the edge of the component or of the semiconductor chip on the upper side or chip top side and / or from an end point arranged on a connection surface of the component to the edge of the component on the connection surface.
- an electrical operative connection between said components can be produced by low material costs.
- the chip top side and the connection surface can run plane-parallel to one another. Likewise, these contact surfaces can also lie on different levels. Of course, it is also conceivable that the chip top and the pad lie on planes that define an angle to each other.
- connection string may be cantilevered between the edges of the component and the semiconductor chip. However, it may also be advantageous if it is supported by an electrically insulating material. For this purpose, to bridge a distance between the components, in particular between the semiconductor chip and the component, an electrically insulating filling material may be arranged, which supports the connecting strand.
- the semiconductor chip may be inserted in a receptacle of a substrate.
- the preferably planar insertion of the component into the receptacle has various advantages.
- the recessed arrangement of the component leads to a leveling between the support top and top of the component. Particular advantages may arise in particular if this assembly is used for optical applications, such as LEDs.
- electronic Components are, in particular, semiconductor chips (so-called "dice”), in particular also LED dice or laser diode chips, in question
- a substrate is, for example, a metallic leadframe or a printed circuit board, both of which can be designed to be rigid or flexible.
- Another aspect of the invention relates to a method for producing an assembly, in particular an assembly of the aforementioned type and in particular for producing an electrical contact between two components.
- the method should work reliably even with components with varying heights.
- a mass of pasty or liquid mass in the form of a connecting strand By applying a mass of pasty or liquid mass in the form of a connecting strand, the electrically conductive operative connection between the components can be produced in an efficient and simple manner.
- the mass can be cured after the application process. This can be done by using heat and / or by light, in particular by UV light. Of course - depending on the nature and composition of the mass - the curing could be done in other ways.
- the paste is pressed for application through a channel of an applicator.
- the connecting strands can be designed differently depending on the application.
- FIG. 1 shows a perspective view of an assembly according to the invention with a semiconductor chip and a component
- FIG. 2 shows a longitudinal section through the assembly according to FIG. 1 and an application device
- Figure 2a the assembly according to Figure 2 with a one
- FIG. 2b shows the assembly according to FIG. 2a with a protective jacket
- FIG. 2c shows a longitudinal section through a further assembly as well as an application device
- FIG. 3 shows an assembly with a semiconductor chip and two further components
- FIG. 4 shows a further embodiment of an assembly
- FIG. 5 shows an assembly with a plurality of semiconductor chips and a component
- FIG. 6 shows a perspective illustration of a further embodiment of an assembly in which a semiconductor chip is inserted into a receptacle of a substrate
- FIG. 7 shows a longitudinal section through the assembly according to FIG. 6 and an application device, Figure 8: the assembly according to Figure 7 with a one
- FIG. 9 shows the assembly according to FIG. 8 with a protective jacket
- FIG. 10 a perspective view of an assembly with a bridge element
- FIG. 11 shows a longitudinal section through the assembly according to FIG. 10,
- FIG. 12 shows a perspective view of an assembly in which semiconductor chips are connected to one another by connecting strands
- FIG. 13 a longitudinal section through the assembly according to FIG. 12,
- FIG. 14 shows a perspective view of the assembly according to FIG. 12 with filling materials supporting the connecting strands
- FIG. 15 shows a longitudinal section through the assembly according to FIG. 14,
- FIG. 16 shows a perspective view of an alternative embodiment of the assembly according to FIG. 12 or 14, FIG.
- FIG. 17 shows a longitudinal section through the assembly according to FIG. 16,
- FIG. 17 a a longitudinal section through a further assembly
- FIG. 18 shows a cross section through a connecting strand (section AA according to FIG. 1)
- FIG. 19 shows a cross section through a flat connecting strand
- FIG. 20 shows a perspective view of an assembly with the planar connecting strand according to FIG. 19, and FIG.
- FIG. 21 shows another assembly with the planar connecting strand according to FIG. 19.
- an assembly designated by 1 contains a semiconductor chip 2 and a component 3 arranged at a distance from it as a further component.
- an exposed connecting strand 4 which connects the upper sides 7 and 8 of the two components 2 and 3, is provided.
- semiconductor chips are understood to be unimpeded semiconductor chips, so-called "dice.”
- Components 3 include, for example, substrates such as metallic leadframes or a printed circuit board, which may be designed to be rigid or flexible 1 and (as well as in the remaining figures) are formed by a rectangular connection section directed against the semiconductor chip 2.
- the electrically conductive connecting strand consists of a mass which can be applied in pasty or even liquid form. As a mass commercially available silver conductive paste can be used. Electrically conductive materials are further described in DE-Al-102 28 484.
- the connecting strand 4 extends from an end point 5 on the chip top side 7 to the edge of the semiconductor chip 2 along the chip top side 7. In the area of the connection surface 8, the connecting strand 4 runs from the end point 6 to the edge of the component 3 on the connection surface 8.
- the compound strand 4 is applied with the aid of an application device 12. To this end, pasty or possibly liquid material is pressed through a channel 13, while the application device 12 is moved in a predetermined direction. As applicator 12 dispensing needles or metering nozzles are conceivable, for example.
- the connecting strand is cured by the application of heat and / or by light, in particular by UV light, depending on the composition of the composition.
- an approximately wedge-shaped, electrically insulating filling material 15, which supports the connecting strand 4 is arranged between the semiconductor chip 2 and the component 3. In this way, the distance between the components 2, 3 can be bridged.
- the filler material can be introduced in liquid or pasty form in the distance. Of course, but also prefabricated (rigid) parts could be used for this purpose.
- the assembly 1 can be enveloped by a protective jacket 16 made of a potting material.
- a protective jacket 16 made of a potting material.
- the connection string - similar to the wire bonding - in a process step subsequent to the application process for the connecting strand with a potting compound together with the semiconductor chip are protected from environmental influences.
- Such an encapsulation gives the assembly in particular a higher mechanical stability and thermal capacity.
- optically transparent or non-transparent potting material can be used.
- FIG. 2c Such an arrangement is shown in FIG. 2c.
- one of the end points 5 of the connecting strand 4 is arranged on an end face 19 of the semiconductor chip 2. It is even conceivable to provide the other end point at the end face designated by 21 of the component 3.
- FIGS. 3 and 4 show assemblies 1 with a plurality of connecting strands 4. As these two exemplary embodiments show, various embodiments of electrically conductive active connections are possible.
- FIG. 5 illustrates an assembly 1 with a plurality of semiconductor chips 2.
- the semiconductor chips 2 are arranged in a row on a substrate 10, for example a leadframe or a printed circuit board.
- a semiconductor chip 2 is assigned a conductive support surface 14 in each case.
- the connecting strands 4 establish an electrically conductive connection to the respective connecting surfaces 8.
- FIGS. 6 to 9 and FIGS. 10 and 11 show assemblies 1 which, in contrast to FIGS. 1 and 2, have no step or level difference between chip top side 7 and contact surface 8. This is achieved by the semiconductor chip 2 being recessed into a receptacle 11 of the substrate 10.
- Such receptacles could be easily manufactured by a forming process.
- a corresponding forming device (not shown) can be used.
- Such assemblies are particularly preferably applicable to the use of LED or laser diode chips.
- FIG. 10 shows an assembly in which a semiconductor chip 2 is inserted into a receptacle 11 of a substrate designated by 3.
- an electrically conductive connection surface 8 is provided for the connecting strand 4.
- the recess for the receptacle 11 is advantageously to be selected such that the chip top side 7 extends approximately flush with the connection surface 8.
- This flush arrangement can also be seen from FIG.
- the arrangement has the advantage that during the application process, the application device 12 (cf., but FIG. 2) would only have to be moved along the respective top sides (chip top side 7, connection surface 8) which lie on the same plane. In particular, it would thus be possible to avoid a movement vertically to the tops of the components during the application process.
- the connecting strand 4 has a cantilevered section which bridges the gap between the semiconductor chip 2 and the terminal surface 8 of the substrate 3. It may be advantageous if this section is also supported.
- FIG. 1 To bridge a distance between the semiconductor chip 2 and the substrate is an electrically insulating filler material 15th arranged, which supports the connection strand 4.
- the cross-sectional shape of the filling material is predetermined by the design of the receptacle. In Figure 8, therefore, the filler 15 is formed in cross-section approximately wedge-shaped. The filler could be poured in liquid or pasty form in the appropriate area.
- the assembly 1 is encapsulated.
- the outline of a protective cover 16 of the encapsulation is indicated by a dashed line (FIG. 9).
- bridge element 9 bridges the distance between the component 3 and the semiconductor chip 2.
- the bridge element 9 has a bridge section which is arranged between the edges of the substrate 10 and the component 3 that are spaced apart from one another.
- the connecting strand 4 is thus supported over its entire length between the end points 5 and 6.
- the inventive connecting string arrangement is not only suitable for producing an electrically conductive operative connection between a semiconductor chip and a substrate, but also for joining together semiconductor chips. Examples of such assemblies are shown in the (schematized) Figures 12-17.
- the semiconductor chip 7 is connected to adjacent semiconductor chips 3 and 3 'by connecting strands 4.
- the semiconductor chips 2, 3 and 3 ' are evidently arranged in a row.
- the connecting strands 4 are designed to be self-supporting over a relatively large distance.
- the connecting strands 4 advantageously run approximately straight on the plane defined by the chip top sides 7 and 8, respectively. In order to prevent excessive sagging, however, the distance between the semiconductor chips should not be too large.
- FIGS. 16 and 17 show a further embodiment variant.
- the semiconductor chips 2, 3 and 3 ' are deposited on an electrically insulating base surface 18 arranged on a substrate 10. This base surface 18 is intended to prevent a short circuit caused by the pulled down connecting strands 4.
- a contiguous base surface FIGS. 16, 17
- the end faces 19 of the semiconductor chips 7, 8 can also be connected to one another by connecting strands 4.
- a connecting strand could also connect an end face of a semiconductor chip to an upper side of an adjacent semiconductor chip.
- Figures 18 and 20 show variants of cross-sectional shapes of the connecting strand in the region of the chip top side 7 or Terminal surface 8.
- Figure 18 shows an approximately circular configuration (circle segment).
- FIG. 19 shows a band-like, electrically conductive connecting strand 4 made from a material which can be applied in pasty or liquid form.
- the connecting strand 4 according to FIG. 19 can enable a surface connection between the components 2 and 3 (FIGS. 20, 21). However, in procedural terms, a corresponding applicator would also move along a line here to apply the connecting strand.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
Abstract
L'invention concerne un bloc de composants dans lequel une puce à semi-conducteur (2) et un autre élément (3), par exemple un support de circuit fixe ou flexible ou une grille de connexion, sont interconnectés par un conducteur de connexion (4). Ledit conducteur de connexion (4) se compose d'une masse électroconductrice pouvant être appliquée sous forme pâteuse ou liquide.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2005/055133 WO2007042071A1 (fr) | 2005-10-10 | 2005-10-10 | Bloc de composants comprenant au moins deux elements cooperant de maniere electroconductrice et procede permettant de produire ledit bloc de composants |
TW095136704A TW200735736A (en) | 2005-10-10 | 2006-10-03 | Assembly with at leat two component in electrical leading effect connection and procedure for manufacturing the assembly |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2005/055133 WO2007042071A1 (fr) | 2005-10-10 | 2005-10-10 | Bloc de composants comprenant au moins deux elements cooperant de maniere electroconductrice et procede permettant de produire ledit bloc de composants |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007042071A1 true WO2007042071A1 (fr) | 2007-04-19 |
Family
ID=36570941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2005/055133 WO2007042071A1 (fr) | 2005-10-10 | 2005-10-10 | Bloc de composants comprenant au moins deux elements cooperant de maniere electroconductrice et procede permettant de produire ledit bloc de composants |
Country Status (2)
Country | Link |
---|---|
TW (1) | TW200735736A (fr) |
WO (1) | WO2007042071A1 (fr) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015034664A3 (fr) * | 2013-09-04 | 2015-07-23 | Osram Sylvania Inc. | Système pour fixer des dispositifs sur des substrats souples |
WO2018109651A1 (fr) * | 2016-12-14 | 2018-06-21 | Osram Gmbh | Procédé de connexion de formations électroconductrices, structure de support correspondante et dispositif d'éclairage |
EP3429322A1 (fr) * | 2017-07-11 | 2019-01-16 | OSRAM GmbH | Procédé de production de structures de support pour dispositifs d'éclairage et dispositif correspondant |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI509837B (zh) * | 2011-01-17 | 2015-11-21 | Advanced Optoelectronic Tech | 發光二極體晶粒及其製造方法、發光二極體封裝結構 |
TWI806793B (zh) * | 2018-08-28 | 2023-06-21 | 晶元光電股份有限公司 | 半導體裝置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002050903A1 (fr) * | 2000-12-21 | 2002-06-27 | Gemplus | Organe d'isolation decoupe et connexion par cordon de dispense |
US6435414B1 (en) * | 1997-03-27 | 2002-08-20 | Gemplus | Electronic module for chip card |
FR2823011A1 (fr) * | 2001-03-30 | 2002-10-04 | Gemplus Card Int | Connexion par depot de cordon conductrice sur zone de raccordement delimitee par masque isolant |
DE10228484A1 (de) * | 2001-06-28 | 2003-01-16 | Sumitomo Bakelite Co | Elektrisch leitfähige Paste und Halbleitervorrichtung, die unter Verwendung der Paste hergestellt wird |
-
2005
- 2005-10-10 WO PCT/EP2005/055133 patent/WO2007042071A1/fr active Application Filing
-
2006
- 2006-10-03 TW TW095136704A patent/TW200735736A/zh unknown
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6435414B1 (en) * | 1997-03-27 | 2002-08-20 | Gemplus | Electronic module for chip card |
WO2002050903A1 (fr) * | 2000-12-21 | 2002-06-27 | Gemplus | Organe d'isolation decoupe et connexion par cordon de dispense |
FR2823011A1 (fr) * | 2001-03-30 | 2002-10-04 | Gemplus Card Int | Connexion par depot de cordon conductrice sur zone de raccordement delimitee par masque isolant |
DE10228484A1 (de) * | 2001-06-28 | 2003-01-16 | Sumitomo Bakelite Co | Elektrisch leitfähige Paste und Halbleitervorrichtung, die unter Verwendung der Paste hergestellt wird |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015034664A3 (fr) * | 2013-09-04 | 2015-07-23 | Osram Sylvania Inc. | Système pour fixer des dispositifs sur des substrats souples |
WO2018109651A1 (fr) * | 2016-12-14 | 2018-06-21 | Osram Gmbh | Procédé de connexion de formations électroconductrices, structure de support correspondante et dispositif d'éclairage |
EP3429322A1 (fr) * | 2017-07-11 | 2019-01-16 | OSRAM GmbH | Procédé de production de structures de support pour dispositifs d'éclairage et dispositif correspondant |
Also Published As
Publication number | Publication date |
---|---|
TW200735736A (en) | 2007-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2396832B1 (fr) | Dispositif semi-conducteur optoélectronique encapsulé à couche d'arrêt brasée, et procédé correspondant | |
DE102005049687B4 (de) | Leistungshalbleiterbauteil in Flachleitertechnik mit vertikalem Strompfad und Verfahren zur Herstellung | |
DE112006003036T5 (de) | Halbleiterchipgehäuse mit einem Leitungsrahmen und einem Clip sowie Verfahren zur Herstellung | |
DE102012201172B4 (de) | Verfahren zur Herstellung eines Leistungshalbleitermoduls mit geprägter Bodenplatte | |
DE102011079708B4 (de) | Trägervorrichtung, elektrische vorrichtung mit einer trägervorrichtung und verfahren zur herstellung dieser | |
DE10297164T5 (de) | Flächig befestigbare Optokoppler-Packung | |
DE102004013056B4 (de) | Verfahren zur Herstellung eines Halbleiterbauelements | |
DE102006033222B4 (de) | Modul mit flachem Aufbau und Verfahren zur Bestückung | |
DE102009035358A1 (de) | Elektronikbauelement und Verfahren zu dessen Herstellung | |
DE19622684A1 (de) | Verfahren zur Herstellung mechanisch fester Klebstoffverbindungen zwischen Oberflächen | |
DE112016007464B4 (de) | Halbleitervorrichtung | |
WO2007042071A1 (fr) | Bloc de composants comprenant au moins deux elements cooperant de maniere electroconductrice et procede permettant de produire ledit bloc de composants | |
DE10223738B4 (de) | Verfahren zur Verbindung integrierter Schaltungen | |
DE10124970B4 (de) | Elektronisches Bauteil mit einem Halbleiterchip auf einer Halbleiterchip-Anschlußplatte, Systemträger und Verfahren zu deren Herstellung | |
EP1688997B1 (fr) | Composant électronique avec puces semi-conductrices empilées | |
DE102013103351B4 (de) | Elektronikmodul | |
DE10232788A1 (de) | Elektronisches Bauteil mit einem Halbleiterchip | |
DE102006024147B3 (de) | Elektronisches Modul mit Halbleiterbauteilgehäuse und einem Halbleiterchip und Verfahren zur Herstellung desselben | |
DE102005037948A1 (de) | Sensoranordnung mit einem Sensorbauelement und einem Träger und Verfahren zur Herstellung einer Sensoranordnung | |
DE102015104956A1 (de) | Gedruckte Leiterplatte mit einem Leiterrahmen mit eingefügten gehäusten Halbleiterchips | |
DE10139985B4 (de) | Elektronisches Bauteil mit einem Halbleiterchip sowie Verfahren zu seiner Herstellung | |
WO2009121675A1 (fr) | Agencement de composants et procédé de fabrication d’un agencement de composants | |
DE10339487B4 (de) | Verfahren zum Aufbringen eines Halbleiterchips auf einen Träger | |
WO2014114398A1 (fr) | Ensemble d'éclairage pourvu d'un composant optoélectronique | |
EP2302987B1 (fr) | Intégration de composants SMD dans un boîtier IC |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
DPE2 | Request for preliminary examination filed before expiration of 19th month from priority date (pct application filed from 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 05794637 Country of ref document: EP Kind code of ref document: A1 |