WO2006030860A1 - 電子機器、デジタル信号生成方法、デジタル信号記録媒体、および信号処理装置 - Google Patents
電子機器、デジタル信号生成方法、デジタル信号記録媒体、および信号処理装置 Download PDFInfo
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- WO2006030860A1 WO2006030860A1 PCT/JP2005/017044 JP2005017044W WO2006030860A1 WO 2006030860 A1 WO2006030860 A1 WO 2006030860A1 JP 2005017044 W JP2005017044 W JP 2005017044W WO 2006030860 A1 WO2006030860 A1 WO 2006030860A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10527—Audio or video recording; Data buffering arrangements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/24—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing noise
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10527—Audio or video recording; Data buffering arrangements
- G11B2020/10537—Audio or video recording
- G11B2020/10546—Audio or video recording specifically adapted for audio data
Definitions
- the present invention relates to an electronic device suitable for rewriting firmware and the like, and a digital signal generation method, a digital signal recording medium, and a signal processing device suitable for rewriting firmware and the like.
- Audio devices such as amplifiers and DVD players incorporate a CPU that operates based on a program.
- programs those that are positioned between hardware and software are generally called firmware. If this firmware is stored in a flash memory or the like, it is possible to add functions or correct defects later.
- Patent Document 1 after switching to the upgrade mode when rewriting the firmware, the input terminal for digital audio signals and other terminal force firmware rewrite data are input, and this data is processed in the memory reproduction process. A device that upgrades by overwriting the program area as appropriate is described.
- Patent Document 1 Japanese Patent Laid-Open No. 2002-149428
- the firmware rewriting data has a format different from that of the audio signal, so there is a possibility that a large noise may be reproduced, and the rewriting data is processed. During this time, it was necessary to switch modes so that noise was not reproduced.
- the present invention has been made in view of the above-described circumstances, and does not use an expensive high-speed electronic circuit, and does not generate a large noise during rewriting of a program, etc., and digital signal generation It is an object to provide a method, a digital signal recording medium, and a signal processing apparatus.
- the present invention is characterized by having the following configuration.
- Storage means for storing at least one of firmware and data used in the CPU
- An input terminal for inputting a digital signal of a predetermined format
- Extraction means for extracting data at a predetermined timing position in one frame of the input digital signal and outputting it as extracted data
- Rewriting means for analyzing the extracted data and rewriting at least one of firmware and data in the storage unit based on the analysis result and the extracted data;
- the CPU functions as at least the extracting means.
- the rewriting means sequentially analyzes the extracted data stored in the buffer storage means, and the analysis result and the extracted data in the buffer storage means. (1) to (3), wherein at least one of the firmware and data in the storage means is rewritten based on The electronic device according to Crab.
- the predetermined timing position is a sampling point set in each section when the effective data length in one frame is divided into N sections (1) to (4) V An electronic device described in any way.
- the predetermined timing position is a sampling point set in M sections (M is less than N) when the effective data length in one frame is divided into N sections.
- M is less than N
- the force is also (4) V, electronic equipment as described in the gap.
- the rewriting means performs the analysis and the rewriting by ignoring the extracted data extracted by the extracting means at a specific timing.
- the effective data length in one frame is divided into N sections consisting of a plurality of bits, and for each section, the continuation of “1” data or “0” data depends on each bit value of the original data.
- a method of generating a digital signal comprising arranging a series.
- each of the sections includes a section having a different length.
- the effective data length in one frame is divided into at least a part of the stored digital signal into N sections each composed of a plurality of bits. For each section, “1” is set according to each bit value of the original data.
- a digital signal recording medium characterized in that a series of “data” or a series of “0” data is arranged!
- each of the sections includes a section having a different length.
- At least part of the stored digital signal contains N effective data lengths in one frame.
- a continuation of “1” data or a continuation of “0” data is arranged according to each bit value of the original data!
- An apparatus for extraction comprising: means for extracting and recognizing N-bit data corresponding to original data by extracting data bit by bit from N intervals.
- the sampling rate for extraction can be set lower than the sampling rate of the original digital signal. Even if the speed is slow, it can respond sufficiently. This is particularly suitable when a slow CPU is used for the extraction means and processing means. However, since the processing speed is the same as the processing of dividing the original digital signal, the time required for the entire rewriting is not extremely slow, and a practically sufficient speed can be obtained.
- the effective data length in one frame is divided into N sections, and for each section, “1” data continuation or “0” data continuation is performed according to each bit value of the original data. Since it is arranged, it can be applied to any format. Therefore, for example, when applied to the format of a digital audio signal, even if it is a device capable of processing a digital audio signal, even a normal digital audio signal is a digital signal generated by the present invention. However, both can perform processing, and the power of the digital signal according to the present invention is one reading in each section. If the sampling is performed, the original signal can be extracted. Therefore, a frequency division effect can be obtained with respect to the reading speed, and the original signal can be extracted even if the clock speed is low and the device. In this case, the processing speed is the same as the processing that divides the original digital signal, so even if it is applied to firmware rewriting, the overall time is not extremely slow and it is practically sufficient. You can get speed.
- FIG. 1 is a block diagram showing a configuration of the present embodiment.
- FIG. 2 is a waveform diagram showing signals included in the I2S bus in the same embodiment.
- FIG. 3 is a timing chart showing timing when data is extracted from digital audio signal data in the embodiment.
- FIG. 4 is a block diagram showing a circuit example when data extraction timing is extracted by nodeware in the embodiment.
- FIG. 5 is an explanatory diagram showing a processing method when data for rewriting is embedded in the format of a digital audio signal in the embodiment.
- FIG. 6 is a correspondence table showing the contents of a frame when 4-bit division is performed in the same embodiment.
- FIG. 7 is a correspondence table showing the contents of a frame when 8-bit frequency division is performed in the same embodiment.
- FIG. 8 is a correspondence table showing the contents of a frame when performing 16-bit frequency division in the same embodiment.
- FIG. 9 is a correspondence table showing the contents of frames in one aspect of frequency division when one frame is 24 bits in the embodiment.
- FIG. 10 is a correspondence table showing the contents of frames in one aspect of frequency division when one frame is 24 bits in the embodiment.
- FIG. 11 is a chart showing a noise level reduction state when the upper bits are not used.
- FIG. 12 is a correspondence table showing the contents of each frame when an audio signal and rewrite data are mixed in one frame.
- FIG. 13 is a chart showing another example of a rewrite instruction command.
- FIG. 14 is a waveform diagram showing another example of rewrite instruction command recognition.
- FIG. 15 is a waveform diagram showing another example of rewrite instruction command recognition.
- FIG. 16 is a timing chart showing another example of reading timing.
- FIG. 1 is a block diagram showing the configuration of this embodiment.
- reference numeral 1 denotes an input terminal to which a digital audio signal DAS of SPDIF (Sony / Philips Digital Interface Format) which is one of digital audio interface standards is inputted.
- DAS Serial / Philips Digital Interface Format
- the CD player 30 reproduces the compact disc 35 and supplies the digital audio signal DAS according to the SPDIF standard to the input terminal 1.
- the digital audio signal DAS is converted into a signal suitable for the I2S bus (The Inter-IC Sound Bus) by a digital interface receiver (hereinafter abbreviated as DIR) 2.
- the I2S bus is a standard generally used for transmitting and receiving 2CH (stereo) audio sampling digital data, and the signal included in this bus contains a word clock LRCLK that defines the frame as shown in Figure 2.
- a bit clock BCLK Figure 2 (Port)
- RDATA Figure 2 (C)
- the word clock LRCLK indicates L-ch (left channel) during the L level and R-ch (right channel) during the H level.
- the data signal RDATA is specified to be shifted by 1 bit from the falling edge of the word clock LRCLK.
- the explanation is based on the assumption that there is no bit shift as shown in Fig. 2 (c).
- the data length of one frame is not specified and is arbitrary, but in this embodiment, it is 64 bits.
- the valid bit indicating the data content of the 32 bits on one side channel is 16 bits, and the other bits are control data and empty (reserved) bits.
- one side channel has 16 bits, and all the bits are valid bits (see Fig. 3).
- DSP digital signal processor
- the read data signal RDATA is subjected to decoding processing, sound field application processing, and the like for each channel, and then converted to an analog signal by the DAC 4.
- the left and right channel analog signals output from the DAC 4 are amplified by the amplifier 5 and emitted from the left and right speakers 6a and 6b.
- 10 is a CPU that controls each part of the apparatus, and operates according to programs stored in the memory 11 and the flash memory 12.
- the flash memory 12 stores firmware, data referred to by the CPU 10, an OS (operating system), an application program, and the like, and the memory 11 is used for a work area of the CPU 10. Also, the word clock LRCLK and the data signal RDATA are supplied from the DIR2 to the CPU 10! /.
- the CPU 10 reads the data signal RDATA as follows. That is, as shown in FIG. 3, the data signal RDATA is read at a timing delayed by one time from the falling and rising of the word clock LRCLK, and then the data signal RDATA is read three times at a timing delayed by two. .
- time ⁇ 1 is set to approximately 1Z8 of one frame
- time ⁇ 2 is set to 1/4 of one frame.
- the CPU 10 reads the data signal RDATA four times for L ch and R-ch, that is, eight times in one frame. In other words, data that is originally transferred at a rate of 32 bits per frame is read at a speed that is divided by four. In other words, each section divided by 4 bits is read once.
- the same reading is performed for the force R-ch shown for L-ch.
- the time ⁇ 1 and ⁇ 2 in the reading process may be generated by software processing of the CPU 10, or a delay time may be set by hardware as shown in FIG.
- 20 is a pulse generator that generates a pulse at the falling or rising of the word clock LRCLK
- 21 is a delay with a delay time set to 1
- 22 to 24 are delay times ⁇ 2 respectively. Delay set to. From the circuit shown in Figure 4, One clock LRCLK falling (or rising) power A pulse is output after time ⁇ 1, and then a pulse is output three times each time 2 passes. These pulses are used as reading pulses for the data signal RDATA.
- any timing may be used as long as it is set in each section.
- timing between bits may be used as shown in timing T1 in FIG. This is because “0” data continuation or “1” data continuation is arranged in each section, and therefore it is not affected by the bit delimiter. Details of the force data arrangement will be described later.
- the reading timing force in each section does not have to be set to an accurate divide-by-four as in the circuit shown in FIG.
- the intervals may be irregular as shown in timings ⁇ 1 to ⁇ 4 shown in FIG.
- the timing entering each section may be created using the bit clock BCLK.
- it may be read at the 2-bit clock BCLK from the start of the frame, and thereafter read at intervals of the 4-bit clock BCLK, or the bit may be set so that the read timing is set in each interval even if the interval is varied.
- the read timing may be set using the clock BCLK.
- it is possible to configure the read timing within each section without using the bit clock BCLK.
- the CPU 10 reads the data signal RDATA at the timing shown in FIG. 3. However, if the data power read and extracted in this way is not a predetermined command, the CPU 10 reads the data signal RDATA. 10 does not perform any processing on the data signal RDATA force extracted, and controls the DSP3 and other parts of the device according to the program.
- the user sets a compact disc 35 in which new firmware is recorded in the CD player 30.
- the firmware is recorded in accordance with the standard compact disc standard, and the sampling rate is also in accordance with the compact disc standard.
- Firmware data read from the compact disc 35 is output to the I2S bus by DIR2 in the same manner as in the case of music data.
- the data recorded on the compact disc 35 is set to have the same value for each section when one frame is divided into eight sections of 4 bits.
- the original data to be transferred is in binary display (1001)
- the first 4 bits of the data signal DA are (1111) as shown in FIG. 5, and so on (0000), ( 0000) and (1111).
- Table 1 shown in FIG. 6 shows values that can be taken by 16-bit data of L ch (or R-ch) in the present embodiment.
- Table 1 shows 16-bit data where each row is transferred at once. As shown in Table 1, the same value of 1 or 0 is written in each section divided into 4 bits.
- Table 2 shown on the right side of Fig. 6 corresponds to Table 1.
- the first column of Table 2 shows the value of 16-bit data of L-ch (or R-ch) in hexadecimal notation. Yes.
- the second column of Table 2 shows the decimal display
- the third column shows the signed decimal display when the most significant bit is a sign bit
- the fourth column shows the data that the CPU 10 reads.
- the signed decimal representation in the third column corresponds to the signed amplitude of the digital audio data.
- the fourth column shows data embedded in 16-bit data.
- the CPU 10 extracts data by 1 bit at an appropriate timing within a continuous 4-bit section, so that 4-bit data (0000) ⁇ ( 1111) is recognized. Therefore, 8-bit data is extracted and recognized from one frame of 32-bit data consisting of L-ch and R-ch. Then, by analyzing the data extracted in this way, it can be recognized as a command or rewritten for rewriting. Or as hardware data.
- the effective bit length is divided into four sections, and the data signal RDATA is read once in each section.
- the data signal RDATA is read three times at a timing delayed by 2 after the time 1 from the falling edge of the word clock LRCLK.
- the CPU 10 reads the data signal RDATA eight times in one frame, and extracts 8-bit data. Then, the extracted 8 bits are analyzed and the firmware is rewritten.
- firmware rewriting processing For example, a series of rewriting is instructed in a format as shown in FIG.
- (1) “0x00” continues for 10 samples or more.
- “0x55” is placed as the start identifier, and (3) 6 bytes of data indicating alphanumeric characters are placed.
- Each 1-byte character string data is, for example, a character string such as “S”, “T”, “A”, “R”, “T”, “!”.
- (4) Data indicating the number of transmission data in 2 bytes, (5) Predetermined 2-byte command, and (6) Rewrite data are continued.
- the rewriting data (6) is rewritten to the flash memory 12.
- the rewriting software is transferred from the flash memory 12 to the memory 11 and executed.
- the data signal RDATA is supplied to the DSP3 even during the firmware rewriting process described above. Therefore, the sound generation processing by the DAC 4, the amplifier 5, and the speakers 6a and 6b is performed in parallel.
- the target of this processing is firmware rewrite data as described above, not music data, so the sound that is produced becomes noise.
- the generated noise is small as follows.
- the difference between the maximum value and the minimum value of the signed decimal number is “8191”, and “1FFF” is displayed in hexadecimal. Become. The number of bits required to indicate this difference is 13 bits. On the other hand, since the Lch and Rch data are each composed of 16 bits, the amplitude of the noise component is 3 bits less than the total number of bits (16).
- noise level for the maximum amplitude of the music data (hereinafter simply referred to as noise level) is X, where X is the number of bits in one section (hereinafter referred to as frequency division bit number).
- the data signal RDATA since the data signal RDATA is divided and read, it can be read sufficiently even if the operation of the CPU 10 is slow.
- the CPU operating clock is slower than that of the DSP, but the present embodiment can be applied even in such a case.
- it is of course easier to implement with a CPU or DSP with a fast operating clock.
- the present invention can be implemented in various modes. An example is shown below. 1. Changing the number of division bits
- the number of frequency division bits is 4, and the force 1 section is 8 bits. It is also possible to use 8-bit division.
- the 16-bit data of L-ch and R-ch can all be set to the same value.
- Table 3 and Table 4 shown in FIG. 7 show the case of 8-bit frequency division, and correspond to Table 1 and Table 2 shown in FIG. 6, respectively.
- the difference between the maximum and minimum values of signed decimal numbers (corresponding to the amplitude of the audio signal) is “511”, and “1FF” in hexadecimal.
- the number of bits required to indicate this difference is 9 bits.
- the L-ch or R-ch data consists of 16 bits each, the amplitude of the noise component is 7 bits less than the audio signal. Therefore, the noise level in this example is
- Table 5 and Table 6 shown in FIG. 8 show the case of 16-bit frequency division, and correspond to Table 1 and Table 2 shown in FIG. 6, respectively.
- the difference between the maximum and minimum values of signed decimal numbers is only “1”, and only one bit is required to indicate this difference.
- the noise level is
- the example shown in FIGS. 7 and 8 has a greater frequency dividing effect than the above-described embodiment, and is therefore suitable when a CPU with a slower speed is used.
- the number of bits of one side channel of one frame is not limited to that shown in the embodiment. It can be applied to various bit numbers such as 16 bits, 24 bits, 32 bits and 64 bits. Also, the effective bit length in the total number of bits on one side channel can be applied to any bit, that is, all the bits on one side channel may be effective bits, and any number of bits may be effective bits. Also good.
- Tables 7 and 8 shown in Fig. 9 show that the channel bit number is 24 bits and the division bit number is 4 bits. These correspond to Table 1 and Table 2 shown in Fig. 6, respectively. As shown in Table 8, the difference between the maximum and minimum values of signed decimal numbers is “2097151”, and the number of bits required to indicate this difference is 21 bits. In this example, the noise level is 18 dB.
- Table 9 and Table 10 shown in FIG. 10 are read out by extracting only 4 bits from the 24 bits of the force side channel corresponding to Table 7 and Table 8 of FIG. .
- the lower side of the data signal RDATA is separated by a 4-bit section, and the upper side is a 12-bit section! /.
- the difference between the maximum value and the minimum value of the signed decimal number is only “8191”, and the number of bits necessary to indicate this difference is only 13 bits.
- the noise level in this example is 66 dB, which is a significant reduction compared to the case shown in FIG.
- the rewriting is performed using the firmware or the CD for rewriting the reference data.
- the rewriting can be performed while playing music or the like (music, guidance voice, etc.).
- music or the like music, guidance voice, etc.
- the channel on one side is 16 bits
- the lower 8 bits are used for rewriting data
- the upper 8 bits are used for music playback.
- the higher-order side has a great influence on the amplitude, so even if the lower-order bits are used for data rewriting, there is a slight deterioration in sound quality, but it is difficult for the human ear. It is possible to prevent the deterioration of sound quality.
- the number of lower bits used for rewriting there is no problem as long as the number of bits is appropriate. In this case, if the music to be played has a maximum amplitude as much as possible, the effect is great.
- the lower 8 bits are noise components.
- Tables 11 and 12 shown in FIG. 12 correspond to Tables 1 and 2 in FIG.
- the difference between the maximum and minimum values of the signed decimal number is “255”.
- the number of bits required to indicate the difference is 8 bits. Therefore, noise of 8 bits is generated, which is the same as 8 bits used for rewriting the firmware and has no noise reduction effect.
- the noise level is 48dB.
- the rewrite instruction method in the above-described embodiment is an example, and there are various other methods.
- the command or command recognition pattern shown in FIG. 14 is an example in which a pattern in which a maximum value and a minimum value are alternately repeated, which cannot be music data, is used as a rewrite start command.
- Fig. 15 shows an example in which a rewrite start command is a pattern in which the maximum value continues for a certain period of time.
- mute (0 data) may be arranged in a predetermined pattern, and if a mute pattern at a predetermined interval can be recognized, it may be determined as a rewrite recognition pattern.
- the present invention is applied to the audio amplifier.
- the present invention is not limited to this, and various audio devices (electronic Equipment) or other than audio equipment, it can be used for various electronic equipment with a CPU.
- the present invention can also be applied to a personal computer.
- the above-described embodiment is a power intended for processing a SPDIF standard digital audio signal.
- a digital signal of a format other than this may be used.
- the frequency of the single clock LRCLK may be different. For example, it can be 44.1 kHz or 48 kHz.
- the present invention is not limited to data read from a recording medium such as a CD or a DVD, but can be applied to data supplied via a predetermined cable or the Internet, for example. That is, the digital signal generated by the digital signal generation method according to the present invention may be transferred without going through the recording medium.
- the power capable of various frequency dividing modes For example, data of a plurality of frequency dividing modes is recorded on a CD, and the data is processed according to the processing speed of the CPU. Select and write data You may comprise so that a replacement process may be performed. In this case, if data indicating the frequency division mode is included as a rewrite instruction command, the CPU can start rewriting when it detects a command that matches its own speed. The same applies to the case where the digital signal power is supplied via the Internet.
- the DSP functions as a processing means for processing a digital audio signal (a digital signal of a predetermined format). Functions as an extraction means for extracting data at a predetermined timing position from a frame of a digital audio signal and a rewriting means for analyzing and rewriting the extracted data, while the CPU functions as a processing means.
- the DSP may not be provided separately, and the extraction means and the rewriting means may be realized by separate circuits.
- connection between DIR2 and CPU 10 may be made via a switch SW as shown by a broken line in FIG. In this case, turn on the switch SW only when rewriting the firmware.
- the switch SW may be turned on by software processing based on a program that may be turned on when the operator operates the switch or the like.
- a digital signal of a predetermined format composed of one frame of m bits has a m-bit format based on the bit clock BCLK! It can be read as it is, or it can be read as a signal divided by n. Therefore, it is possible to mix the reading and processing of digital signals in m-bit format and the rewriting of programs by extracting data as n-divided signals. Depending on the mode of mixing, time-sharing processing is possible, and simultaneous processing is also possible.
- the DSP reads the data in the m-bit format based on the bit clock BCLK and extracts only the data at the predetermined bit position from the read data, the m-bit reading and the frequency-divided reading are performed. Both processes can be performed by DSP alone.
- the CPU 10 extracts rewritten data and the rewrite control is also performed by the CPU 10. However, the CPU 10 analyzes the extracted data so that the DSP 3 Send a rewrite command and DSP3 will do the rewrite process You may comprise. Further, all the extracted data extracted by the CPU 10 may be transferred to the DSP 3, and the analysis of the extracted data and the rewriting of the firmware (or data) may be performed by the DSP 3. In this case, as indicated by a broken line in FIG. 1, the DSP 3 performs a rewrite process on the flash memory 12 connected to the DSP 3. In addition, as shown by the broken line in Fig. 1, it is configured to output the extracted data extracted by CPU10 as it is, and the other CPU40 analyzes the extracted data and outputs it to other CPU40! / It may be configured to rewrite the firmware and data stored in the memory 41 etc.
- Fig. 16 (i) when one side channel is divided into four sections (more accurately, when the effective bit of one side channel is divided into four sections), one time in each section It is only necessary to set the read timing, but as shown in Fig. 16 (mouth), the read timing may be set only for the sections 3 and 4 (corresponding to the lower 2 bits) in the 4 sections. In this case, a series of data “0” or “1” is written in the sections 3 and 4, but any data can be written in the sections 1 and 2. Also, as shown in Fig. 16 (c), even if the reading timing is set for each section, the data extracted in sections 1 and 2 are ignored and ignored, and only the data read in sections 3 and 4 are ignored. May be adopted as extraction data. In this case, as in the case of Fig. 16 (mouth), any data can be written in sections 1 and 2.
- the reading timing is summarized as follows. First, the reading timing is a sampling point set in each section when the effective data length in one frame is divided into N sections (Fig. 16 (i)). Alternatively, as shown in Fig. 16 (mouth), the reading timing is a sampling point set in M sections (M is less than N) when the effective data length in one frame is divided into N sections. is there. Ma In addition, as shown in Fig. 16 (c), it may be possible to perform analysis or rewrite processing of commands, etc., ignoring the extracted data at a specific timing.
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT05783282T ATE533156T1 (de) | 2004-09-15 | 2005-09-15 | Unterabtastung der firmwareaktualisierungsdaten durch die cpu eines audiowiedergabegeräts während der wiedergabe des audiosignals. |
CN2005800309620A CN101019104B (zh) | 2004-09-15 | 2005-09-15 | 电子设备、数字信号产生方法、数字信号记录介质以及信号处理设备 |
EP05783282A EP1830267B1 (en) | 2004-09-15 | 2005-09-15 | Subsampling firmware update data by the CPU in an audioplayer while reproducing the audio signal. |
US11/663,008 US8121713B2 (en) | 2004-09-15 | 2005-09-15 | Electronic apparatus, method for generating digital signal, digital signal recording medium, and signal processing apparatus |
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JP2004268249A JP2006085339A (ja) | 2004-09-15 | 2004-09-15 | デジタル信号生成方法、デジタル信号記録媒体 |
JP2004-268249 | 2004-09-15 | ||
JP2004268248A JP4529605B2 (ja) | 2004-09-15 | 2004-09-15 | 電子機器 |
JP2004-268248 | 2004-09-15 |
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PCT/JP2005/017044 WO2006030860A1 (ja) | 2004-09-15 | 2005-09-15 | 電子機器、デジタル信号生成方法、デジタル信号記録媒体、および信号処理装置 |
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US (1) | US8121713B2 (ja) |
EP (2) | EP1830267B1 (ja) |
AT (1) | ATE533156T1 (ja) |
WO (1) | WO2006030860A1 (ja) |
Families Citing this family (2)
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EP2672393A1 (en) * | 2012-06-04 | 2013-12-11 | Dialog Semiconductor B.V. | Circuit and methods to use an audio interface to program a device within an audio stream |
US10447910B2 (en) * | 2016-08-04 | 2019-10-15 | International Business Machines Corporation | Camera notification and filtering of content for restricted sites |
Citations (5)
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JPH0721615A (ja) * | 1993-07-05 | 1995-01-24 | Sony Corp | 光デイスク装置 |
JP2002149428A (ja) | 2000-11-13 | 2002-05-24 | Yamaha Corp | オーディオ信号処理装置およびオーディオ信号処理装置の内部データ書き換え方法 |
JP2003036650A (ja) * | 2001-07-23 | 2003-02-07 | Sony Corp | ディスク記録再生装置 |
JP2003091428A (ja) * | 2001-09-14 | 2003-03-28 | Accuphase Laboratory Inc | プログラム更新機能を備えた電子機器、及び同電子機器のプログラム更新方式 |
JP2004164006A (ja) * | 2002-11-08 | 2004-06-10 | Fuji Photo Film Co Ltd | 電子機器 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000276387A (ja) * | 1999-03-23 | 2000-10-06 | Toshiba Corp | メタデータ登録方法および装置、データサーバ装置、並びにメタデータ登録用プログラムを記憶した記憶媒体 |
JP3659321B2 (ja) * | 2000-06-29 | 2005-06-15 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電子透かし方法およびそのシステム |
US7483979B1 (en) * | 2001-01-16 | 2009-01-27 | International Business Machines Corporation | Method and system for virtualizing metadata between disparate systems |
JP3521904B2 (ja) * | 2002-08-22 | 2004-04-26 | 日本電気株式会社 | イーサネット(r)におけるフレーム転送方法及びノード |
JP2004235739A (ja) * | 2003-01-28 | 2004-08-19 | Sony Corp | 情報処理装置、および情報処理方法、並びにコンピュータ・プログラム |
US7957263B2 (en) * | 2003-09-08 | 2011-06-07 | Qualcomm Corporation | Method and apparatus for acknowledging reverse link transmissions in a communications system |
-
2005
- 2005-09-15 EP EP05783282A patent/EP1830267B1/en not_active Not-in-force
- 2005-09-15 WO PCT/JP2005/017044 patent/WO2006030860A1/ja active Application Filing
- 2005-09-15 EP EP11007275.8A patent/EP2400495B1/en not_active Not-in-force
- 2005-09-15 AT AT05783282T patent/ATE533156T1/de active
- 2005-09-15 US US11/663,008 patent/US8121713B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0721615A (ja) * | 1993-07-05 | 1995-01-24 | Sony Corp | 光デイスク装置 |
JP2002149428A (ja) | 2000-11-13 | 2002-05-24 | Yamaha Corp | オーディオ信号処理装置およびオーディオ信号処理装置の内部データ書き換え方法 |
JP2003036650A (ja) * | 2001-07-23 | 2003-02-07 | Sony Corp | ディスク記録再生装置 |
JP2003091428A (ja) * | 2001-09-14 | 2003-03-28 | Accuphase Laboratory Inc | プログラム更新機能を備えた電子機器、及び同電子機器のプログラム更新方式 |
JP2004164006A (ja) * | 2002-11-08 | 2004-06-10 | Fuji Photo Film Co Ltd | 電子機器 |
Also Published As
Publication number | Publication date |
---|---|
US8121713B2 (en) | 2012-02-21 |
EP2400495B1 (en) | 2015-06-03 |
EP2400495A1 (en) | 2011-12-28 |
EP1830267A1 (en) | 2007-09-05 |
ATE533156T1 (de) | 2011-11-15 |
US20080005540A1 (en) | 2008-01-03 |
EP1830267A4 (en) | 2009-07-29 |
EP1830267B1 (en) | 2011-11-09 |
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