Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09B—EDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS
  • G09B27/00—Planetaria; Globes
  • G09B27/08—Globes
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
  • G02F1/1362—Active matrix addressed cells
  • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B42—BOOKBINDING; ALBUMS; FILES; SPECIAL PRINTED MATTER
  • B42F—SHEETS TEMPORARILY ATTACHED TOGETHER; FILING APPLIANCES; FILE CARDS; INDEXING
  • B42F17/00—Card-filing arrangements, e.g. card indexes or catalogues or filing cabinets
  • B42F17/30—Card-filing arrangements, e.g. card indexes or catalogues or filing cabinets modified for particular uses
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B42—BOOKBINDING; ALBUMS; FILES; SPECIAL PRINTED MATTER
  • B42F—SHEETS TEMPORARILY ATTACHED TOGETHER; FILING APPLIANCES; FILE CARDS; INDEXING
  • B42F5/00—Sheets and objects temporarily attached together; Means therefor; Albums
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
  • G02F1/1362—Active matrix addressed cells
  • G02F1/136213—Storage capacitors associated with the pixel electrode
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09B—EDUCATIONAL OR DEMONSTRATION APPLIANCES; APPLIANCES FOR TEACHING, OR COMMUNICATING WITH, THE BLIND, DEAF OR MUTE; MODELS; PLANETARIA; GLOBES; MAPS; DIAGRAMS
  • G09B29/00—Maps; Plans; Charts; Diagrams, e.g. route diagram
  • G09B29/003—Maps
  • G09B29/006—Representation of non-cartographic information on maps, e.g. population distribution, wind direction, radiation levels, air and sea routes
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
  • G02F1/1362—Active matrix addressed cells
  • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F2202/00—Materials and properties
  • G02F2202/10—Materials and properties semiconductor
  • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

• the present invention relates to a liquid crystal display using a high-temperature poly silicon thin film transistor(TFT-LCD) used for a projection display device and a manufacturing method thereof, and more specifically to an LCD panel using a thin film transistor and a manufacturing method thereof for improving an opening ratio of a screen by minimizing an impermeable area of light, which is occupied by a storage capacitor.
• TFT-LCD high-temperature poly silicon thin film transistor
• An opening ratio refers to a ratio occupied by a part for transmitting light on the entire screen of the liquid crystal display using the thin film transistor, and the opening ratio is an important factor when determining performance of the LCD panel. As a certain area gets increased, the opening ratio gets reduced.
• Fig. 1 is a sectional view of a lower substrate of an LCD panel using a poly silicon thin film transistor by prior art.
• the lower substrate of the LCD panel using the thin film transistor forms black matrices(2) by depositing and patterning an opaque film on a transparent substrate(l), deposits a first interlayer insulting f ⁇ lm(3) on the transparent substrate(l) and the black matrices(2), and forms an active layer(4) consisting of a semiconductor film by depositing and patterning the semiconductor film on the insulating film(3).
• a gate insulating film(5) is deposited on the active layer(4).
• Contact holes contacted with the black matrices(2) are formed by opening the first interlayer insulating film(3) and the gate insulating film(5), and a first connection electrode(18) is formed by injecting a conductive material into the contact holes and patterning them. Also, a gate electrode( ⁇ ) and a capacitor upper electrode( ⁇ ') are formed by depositing and patterning the conductive material on the gate insulating film(5). At this time, the first connection electrode(18), the gate electrode( ⁇ ), and the capacitor upper electrode( ⁇ ') are made of the same material. Then, impurities are injected into the active layer(4) through an ion injection process after forming the gate electrode( ⁇ ), and the active layer(4) is activated.
• a second interlayer insulating film(7) is deposited on the first connection electrode(18), the gate electrode( ⁇ ), the capacitor upper electrode( ⁇ '), and the gate insulating film(5).
• the capacitor upper electrode( ⁇ '), the gate insulating film, and the active layer configure a storage capacitor for maintaining data transmitted to a liquid crystal cell for a certain time.
• Contact holes connected to the first connection electrode(18) and the capacitor upper electrode( ⁇ '), respectively, are comprised by opening a predetermined area of the second interlayer insulating film(7).
• Contact holes contacted with the active layer are formed by opening predetermined areas of the second interlayer insulating film and the gate insulating film at an interval of the gate electrode.
• a first common electrode(19) connected with the first connection electrode(18) a source electrode(8) contacted with a source area of the active layer, a drain electrode(8') contacted with a drain area of the active layer, and a second common electrode(14) contacted with the capacitor upper electrode( ⁇ ') are formed, respectively.
• a third interlayer insulating film(9) for covering the first common electrode(19), the source electrode(8), the drain electrode(8'), the second connection electrode(14), and the second interlayer insulating film(7) is deposited and planarized.
• Contact holes connected with the drain electrode(8') and the second common electrode(14), respectively, are formed by opening a predetermined area of the planarized third interlayer insulating film(9), while forming a second connection electrode(l ⁇ ) connected with the drain electrode(8') by filling the contact holes with a conductive metal and an upper black matrix(12) filled with a light cutoff material while being patterned.
• contact holes contacted with the second connection electrode(l ⁇ ) are formed after depositing and planarizing a fourth interlayer insulating film on the upper black matrix(12), the second connection electrode(l ⁇ ), and the third interlayer insulating film(9).
• a pixel electrode(14) is formed by depositing and patterning a transparent conductive film such as ITO to complete the manufacturing process.
• the size of the storage capacitor may exert a severe affect upon an opening ratio of the LCD element.
• an LCD panel for transmitting or cutting off light through a change of a liquid crystal material array by interposing a liquid crystal material between a lower substrate consisting of a thin film transistor as a switching element and an upper substrate consisting of a common electrode
• the lower substrate comprising: a transparent substrate; a storage capacitor consisting of a storage capacitor first electrode deposited and patterned on the transparent substrate with a conductive film, a capacitor insulating film deposited in predetermined thickness on the transparent substrate and the storage capacitor first electrode, and a capacitor second electrode opposite to the storage capacitor first electrode on the capacitor insulating film, and having an opaque conductive material for cutting off a light incident on a thin film transistor channel unit; a first interlayer insulating film deposited on the capacitor insulating film and the capacitor second electrode; a thin film transistor channel patterned on the first interlayer insulating film with a semiconductor film such as silicon; a gate insulating film covering the first interlayer insulating film and the thin film transistor channel; a gate
• an LCD panel for transmitting or cutting off light through a change of a liquid crystal material array by interposing a liquid crystal material between a lower substrate consisting of a thin film transistor as a switching element and an upper substrate consisting of a common electrode
• the lower substrate comprising: a transparent substrate; a storage capacitor consisting of a storage capacitor first electrode deposited and patterned on the transparent substrate with a conductive film, a capacitor insulating film deposited in predetermined thickness on the transparent substrate and the storage capacitor first electrode, and a capacitor second electrode opposite to the storage capacitor first electrode on the capacitor insulating film and consisting of an opaque conductive material for cutting off a light incident on a thin film transistor channel unit; a first interlayer insulating film deposited on the capacitor insulating film and the capacitor second electrode; a thin film transistor channel forming contact holes contacted with the capacitor second electrode and the capacitor first electrode by opening a predetermined area of the first interlayer insulating film, and patterned on the first interlayer insulating film
• an LCD panel for transmitting or cutting off light through a change of a liquid crystal material array by interposing a liquid crystal material between a lower substrate consisting of a thin film transistor as a switching element and an upper substrate consisting of a common electrode
• the lower substrate comprising: a transparent substrate; a storage capacitor consisting of a storage capacitor first electrode deposited and patterned on the transparent substrate with a conductive film, a capacitor insulating film deposited in predetermined thickness on the transparent substrate and the storage capacitor first electrode, and a capacitor second electrode opposite to the storage capacitor first electrode on the capacitor insulating film and comprising an opaque conductive material for cutting off a light incident on a thin film transistor channel unit; a first interlayer insulating film deposited on the capacitor insulating film and the capacitor second electrode; a thin film transistor channel patterned on the first interlayer insulating film with a semiconductor film; a gate insulating film deposited on the thin film transistor channel and the first interlayer insulating film;
• FIG. 1 is a sectional view of a lower substrate of an LCD panel using a poly silicon thin film transistor by prior art
• FIG. 2 to Fig. 7 are cut sectional views for illustrating a manufacturing method of a lower substrate of a thin film transistor in accordance with a desired embodiment of the present invention
• FIG. 8 is a cut sectional view for illustrating a lower substrate structure of a thin film transistor by one embodiment of the present invention.
• FIG. 9 to Fig. 14 are cut sectional views for illustrating a manufacturing process of a thin film transistor by one embodiment of the present invention.
• Fig. 15 is a cut sectional view for illustrating a lower substrate structure of a thin film transistor by one embodiment of the present invention.
• FIG. 16 to Fig. 21 are cut sectional views for illustrating a manufacturing process of a thin film transistor by one embodiment of the present invention.
• Fig. 22 is a cut sectional view for illustrating a lower substrate structure of a thin film transistor by one embodiment of the present invention.
• FIG. 2 to Fig. 7 are cut sectional views for illustrating a lower substrate manufacturing method of a thin film transistor in accordance with a desired embodiment of the present invention.
• a storage capacitor lower electrode(102) is formed by depositing and patterning a conductive film such as doped poly silicon or metal silicide on a transparent substrate(l ⁇ l).
• a capacitor insulating film(103) is formed by depositing an insulating film through thermal oxidation or CVD(Chemical Vaporized Deposition), and a metal silicide film such as tungsten silicide(WSix) is deposited on the capacitor insulating film(103) while being patterned, functioning as a lower BM(Black Matrix) for cutting off a light incident on a channel unit of the thin film transistor and forming a storage capacitor upper electrode(104)(Fig. 2).
• the BM should have an opaque property for cutting off light as well as conductive property, being made of metal with a high fusion point or silicide film.
• a channel area(106) of the thin film transistor is formed by depositing and patterning a semiconductor film such as poly silicon on the first interlayer insulating film(105). Then, a gate insulating film(107) is formed on the first interlayer insulating film(105) and the channel area(106)(Fig. 3).
• a method for forming the channel area will be more specifically described as follows. The description is applied to a thin film transistor suggested in the present invention except the structure of Fig. 2.
• a polycrystalline silicon thin film transistor which forms the channel area(106) with polycrystalline silicon(p-Si) is mainly used for driving pixels to improve a switching speed.
• Such a polycrystalline silicon thin film polycrystallizes an amorphous silicon semiconductor thin film after depositing it, using an SPC(Solid Phase Crystallization) for annealing at about 500 to 1000°C, a laser crystallization using a low-fusion-point substrate by enabling crystallization at low temperature less than about 400°C, and a metal inductive crystallization using a crystal growth feature change by metal.
• An LDD(Lightly Doped Drain) structure is generally used for a thin film transistor for driving pixels.
• a first contact electrode(121) and a second contact electrode(122) for the storage capacitor upper electrode(104) and the lower electrode(102) are formed by filling with a conductive film.
• the first contact electrode(121) and the second contact electrode(122) use the same conductive material as a gate electrode(108).
• the conductive material is deposited and patterned to form the gate electrode(108)(Fig. 4).
• a second interlayer insulating film(109) covering the first contact electrode(121), the second contact electrode(122), the gate electrode(108), and the gate insulating film(107) is deposited.
• each contact hole is filled with metal while being patterned, to form a common electrode(131) contacted with the first contact electrode(121), a source electrode(132) contacted with the source area, and a drain electrode(133) contacted with the drain area and the second contact electrode(122).
• a third interlayer insulating film(l 11) covering the common electrode(131), the source electrode(132), the drain electrode(133), and the second interlayer insulating film is deposited and planarized.
• the contact holes are filled with metal while being patterned, to form a connection electrode(142) for connecting an upper BM(141) with a pixel electrode(Fig. 6).
• connection electrode(142) After depositing a fourth interlayer insulating film(l 13) on the upper BM(141), the connection electrode(142), and the third interlayer insulating film(l 11), contact holes contacted with the connection electrode(142) are formed while a pixel electrode(l 14) is configured(Fig. 7).
• the pixel electrode is made of a transparent conductor, being generally formed with ITO(Indium Tin Oxide).
• connection electrode(142) and the upper BM(141) suggested in the Fig. 6 is performed to improve display features, which is not an essential step.
• the upper BM is a factor for carrying out an additional function of cutting off a light incident on the channel area
• the connection electrode(142) functions as an intermediate medium for connecting the drain electrode(133) with the pixel electrode(114).
• Fig. 8 is a cut sectional view for illustrating a lower substrate structure of a thin film transistor by one embodiment of the present invention, following the manufacturing methods suggested in Fig. 2 to Fig. 7.
• a difference between the lower substrate structure suggested in Fig. 7 and the lower substrate structure suggested in Fig. 8 is that a lower BM(104) configuring a storage capacitor upper electrode is formed in an upper area only of a storage capacitor lower electrode(102), thereby preventing a step difference from being created in the storage capacitor upper electrode. Therefore, compared to a prior storage capacitor upper electrode having a step difference, it can increase a breakdown voltage.
• FIG. 7 and Fig. 8 Another embodiment may be suggested by replacing a contacting method of the capacitor upper electrode and the lower electrode in the lower substrate structures illustrated in Fig. 7 and Fig. 8. That is, even though the capacitor lower electrode(102) is connected to the drain electrode(133) through the second contact electrode(122) while the capacitor upper electrode(104) is connected to the common electrode(131) through the first contact electrode(121) in Fig. 7 and Fig. 8, a liquid crystal panel as another embodiment may configure that the capacitor upper electrode(104) is connected to the drain electrode(133) through the second contact electrode(122) while the capacitor lower electrode(102) is connected to the common electrode(131) through the first contact electrode(121). [68]
• FIG. 9 to Fig. 14 are cut sectional views for illustrating a manufacturing process of a thin film transistor by one embodiment of the present invention.
• a storage capacitor lower electrode(102) is formed by depositing and patterning a conductive film such as doped poly silicon or metal silicide on a transparent substrate(l ⁇ l). Then, after forming a capacitor insulating film(103) by depositing an insulating film through thermal oxidation or CVD(Chemical Vaporized Deposition), a lower BM(104) for cutting off a light incident on a channel unit of the thin film transistor is formed by depositing and patterning a metal silicide film such as tungsten silicide(WSix) on the capacitor insulating film(103).
• the lower BM(104) is made of a conductive material to perform a function of a storage capacitor upper ele ctrode(104)(Fig. 9).
• a first interlayer insulating film(105) on the capacitor upper electrode(104) and the capacitor insulating film(103) contact holes contacted with the capacitor upper electrode(104) and the lower electrode(102) are formed.
• a semiconductor film such as poly silicon is deposited on the first interlayer insulating film(105), while the contact holes are filled with the semiconductor film as being patterned to configure a first contact electrode(121) contacted with the capacitor upper electrode(104) and a second contact electrode(122) contacted with the capacitor lower electrode(102), respectively.
• a channel area(106) of the thin film transistor is formed by patterning poly silicon deposited on the first interlayer insulating film(105)(Fig. 10). In this case, it is desirable to use poly silicon configuring the channel area(106) of the thin film transistor for the fist contact electrode(121) and the second contact electrode(122).
• a gate insulating film(107) is formed on the first contact electrode(121), the second contact electrode(122), the channel area(106), and the first interlayer insulating film(105).
• a gate electrode(108) is configured by depositing and patterning a conductive film on the gate insulating film(107).
• a second interlayer insulating film(109) is deposited on the formed gate insulating film(107) and the gate electrode(108)(Fig. 11).
• each contact hole is filled with metal while being patterned, to form a common electrode(131) contacted with the first contact electrode(121), a source electrode(132) contacted with the source area, and a drain electrode(133) contacted with the drain area and the second contact electrode(122).
• a third interlayer insulating film( 111) covering the common electrode( 131), the source electrode(132), the drain electrode(133), and the second interlayer insulating film is deposited and planarized. After forming contact holes contacted with the common electrode(131) and the drain electrode(133), respectively, on the planarized third interlayer insulating film, the contact holes are filled with metal while being patterned, to form a connection electrode(142) for connecting an upper BM(141) with a pixel electrode(Fig. 13).
• connection electrode(142) After depositing and planarizing a fourth interlayer insulating film(l 13) on the upper BM(141), the connection electrode(142), and the third interlayer insulating film(l 11), contact holes contacted with the connection electrode(142) are formed to configure a pixel electrode(l 14)(Fig. 14).
• connection electrode(142) and the upper BM(141) suggested in Fig. 13 is performed to improve display features, which is not an essential step.
• the upper BM is a factor for carrying out an additional function of cutting off a light incident on the channel area
• the connection electrode(142) functions as an intermediate medium for connecting the drain electrode(133) with the pixel electrode(114).
• Fig. 15 is a cut sectional view for illustrating a lower substrate structure of a thin film transistor by one embodiment of the present invention, following the manufacturing methods suggested in Fig. 9 to Fig. 14.
• a difference between the lower substrate structure suggested in Fig. 14 and the lower substrate structure suggested in Fig. 15 is that the lower BM(104) configuring the storage capacitor upper electrode is formed in an upper area only of the storage capacitor lower electrode(102), thereby preventing a step difference from being created in the storage capacitor upper electrode. Accordingly, compared to a prior storage capacitor upper electrode having a step difference, it can increase a breakthrough voltage.
• FIG. 14 and Fig. 15 Another embodiment may be suggested by replacing the contacting method of the capacitor upper electrode and the lower electrode in the lower substrate structures of Fig. 14 and Fig. 15. That is, even though the capacitor lower electrode(102) is connected to the drain electrode(133) through the second contact electrode(122) while the capacitor upper electrode(104) is connected to the common electrode(131) through the first contact electrode(121) in Fig. 14 and Fig. 15, an LCD panel as another embodiment may configure that the capacitor upper electrode(104) is connected to the drain electrode(133) through the second contact electrode(122) while the capacitor lower electrode(102) is connected to the common electrode(131) through the first contact electrode(121).
• Fig. 16 to Fig. 21 are cut sectional views for illustrating a manufacturing process of a thin film transistor by one embodiment of the present invention.
• a storage capacitor lower electrode(102) is formed.
• a metal silicide film such as tungsten silicide(WSix) is deposited and patterned on the capacitor insulating film(103) to form a lower BM(104) for cutting off a light incident on a channel unit of the thin film transistor.
• the lower BM(104) is made of a conductive material, to carry out a function of a storage capacitor upper electrode(104) while functioning as the lower BM(Fig. 16).
• a semiconductor film such as poly silicon is deposited and patterned on the first interlayer insulating film(105) to configure a channel area(106) of the thin film transistor. Then, a gate insulating film(107) is formed on the first interlayer insulating film(105) and the channel area(106)(Fig. 17).
• a gate electrode(108) After forming a gate electrode(108) by depositing and patterning a conductive film on the gate insulating film(107) located on top of the channel area(106), contact holes are formed to open certain parts of the capacitor upper electrode(104) and the capacitor lower electrode(102).
• a second interlayer insulating film(109) is deposited to cover the gate insulating film(107), the gate electrode, and the formed contact holes(Fig. 18).
• contact holes are formed in contact with the capacitor upper electrode(104), a source area and a drain area of a thin film transistor channel, and the capacitor lower electrode(102). Then, the contact holes are filled with metal while being patterned, to configure a common electrode(131) contacted with the capacitor upper electrode(104), a source electrode(132) contacted with the source area, and a drain electrode(133) contacted with the drain area and the capacitor lower electrode(102). At this time, it is desirable to fill the common electrode(131), the source electrode(132), and the drain electrode(133) with the same conductive metal(Fig. 19).
• an opening process is once executed to open the capacitor first electrode(102) and the capacitor second electrode(104) after forming the gate oxide film(107) in the process suggested in Fig. 18, while a second opening process is executed to open the capacitor first electrode(102) and the capacitor second electrode(104) after forming the second interlayer insulating film(109) in Fig. 19. It is because the contact holes contacted with the capacitor first electrode(102) and the capacitor second electrode(104) cannot be smoothly formed with one-time opening process while the first interlayer insulating film and the second interlayer insulating film are accumulated.
• a third interlayer insulating film(l 11) covering the common electrode(131), the source electrode(132), the drain electrode(133), and the second interlayer insulating film is deposited and planarized.
• the contact holes are filled with metal while being patterned to configure a connection electrode for connecting an upper BM(141) with a pixel electrode(Fig. 20).
• connection electrode(142) After depositing a fourth interlayer insulating film(l 13) on the upper BM(141), the connection electrode(142), and the third interlayer insulating film(l 11), contact holes contacted with the connection electrode(142) are formed to configure a pixel electrode(114)(Fig. 21).
• connection electrode(142) and the upper BM(141) suggested in the Fig. 20 is carried out to improve display features, which is not an essential step.
• the upper BM is a factor for performing an additional function of cutting off a light incident on the channel area
• the connection electrode(142) functions as an intermediate medium for connecting the drain electrode(133) with the pixel electrode(l 14).
• Fig. 22 is a cut sectional view for illustrating a lower substrate structure of a thin film transistor by one embodiment of the present invention, following the manufacturing methods suggested in Fig. 16 to Fig. 21.
• a difference between the lower substrate structure suggested in Fig. 21 and the lower substrate structure suggested in Fig. 22 is that a lower BM(104) configuring a storage capacitor upper electrode is formed in an upper area only of a storage capacitor lower electrode(102), thereby preventing a step difference from being created in the storage capacitor upper electrode. Therefore, compared to a prior storage capacitor upper electrode having a step difference, it can increase a breakdown voltage.
• FIG. 21 and Fig. 22 Another embodiment may be suggested by replacing a contacting method of the capacitor upper electrode and the lower electrode in the lower substrate structures illustrated in Fig. 21 and Fig. 22. That is, even though the capacitor lower electrode(102) is connected to the drain electrode(133) while the capacitor upper electrode(104) is connected to the common electrode(131) in Fig. 21 and Fig. 22, a liquid crystal panel as another embodiment may configure that the capacitor upper electrode(104) is connected to the drain electrode(133) while the capacitor lower electrode(102) is connected to the common electrode(131).
• the lower substrate of the thin film transistor manufactured according to the above manufacturing methods is united with the upper substrate, while a liquid crystal is injected, thereby completing the liquid crystal substrate using the thin film transistor.
• an LCD panel using a thin film transistor and a manufacturing method thereof in accordance with the present invention can improve an opening ratio occupied by an area where a light is emitted on the entire screen, by configuring a storage capacitor and black matrices which increase sharpness by cutting off a light incident on a channel area of the thin film transistor in a channel lower section of the thin film transistor, and forming the thin film transistor for controlling a liquid crystal cell on an upper end of the storage capacitor to reduce a size that the light is cut off by the black matrices and the thin film transistor.
• the opening ratio resulting in a manufacturing of a display device using a high-quality liquid crystal panel.
• capacitor electrodes of the liquid crystal panel in accordance with the present invention can configure the liquid crystal panel located under the channel of the thin film transistor, that is, near to a transparent substrate.
• the capacitor electrodes formed on the liquid crystal panel in accordance with the present invention form contact holes by dividing them at least twice in order to form contacts without damage of a channel area of the thin film transistor, fill the contact holes with a metal material as a portion of a process for manufacturing a gate electrode while filling them with the same one as a material which configures the gate electrode in the embodiments of Fig. 7 and Fig.
• the liquid crystal panel suggested in the present invention removes any step difference of a storage capacitor upper electrode, thereby proposing the liquid crystal panel using the thin film transistor which comprises a high breakdown voltage.

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