Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
  • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
  • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
  • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
  • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
  • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Definitions

• the invention is in the filed of semiconductor fabrication and more specifically in semiconductor fabrication processes employing elevated source/drain processing.
• SOI wafers incorporate a shallow silicon region (in which transistor structures such as the transistor channel are located) overlying a buried, electrically insulating layer such as silicon dioxide.
• the shallow silicon layer may be too shallow to contain the transistor source/drain regions without exhibiting undesirable and performance limiting current crowding.
• Elevated source/drain structures alleviate this problem by providing a thicker silicon film where the source/drain regions are formed.
• elevated source/drain structures are fabricated with a selective epitaxial process.
• the epitaxial process that forms the elevated source/drain regions introduces an additional thermal cycle into the processing sequence.
• the additional thermal cycle has an undesirable impact on impurity distributions that have already been introduced into the wafer.
• these impurity distributions may include the halo and extension impurity distributions that are well known in the filed of CMOS fabrication. Because it is generally highly desirable to minimize the depth of the halo and extension implant distributions, the additional thermal cycle represented by the epitaxial process is problematic. Accordingly, it would be highly desirable to introduce a method of semiconductor fabrication that incorporates an elevated source/drain processing while simultaneously addressing issued associated with the resulting impact of existing impurity profiles within the wafer.
• FIG. 1 is a partial cross sectional view of a semiconductor wafer at a first selected stage of one embodiment of a fabrication process according to the present invention in which a gate electrode is formed overlying a substrate;
• FIG. 2 depicts processing subsequent to FIG. 1 in which a first oxide liner is formed;
• FIG. 3 depicts processing subsequent to FIG. 2 in which an offset spacer is formed adjacent the first oxide liner;
• FIG. 4 depicts processing subsequent to FIG.
• FIG. 5 depicts processing subsequent to FIG. 4 in which a disposable spacer is formed
• FIG. 6 depicts processing subsequent to FIG. 5 in which an elevated source/drain is formed
• FIG. 7 depicts processing subsequent to FIG. 6 in which the disposable spacer and the second oxide liner are removed
• FIG. 8 depicts processing subsequent to FIG. 7 in which shallow implants are performed
• FIG. 9 depicts processing subsequent to FIG. 8 in which a replacement oxide liner and a replacement spacer are formed where the disposable spacer previously existed
• FIG. 10 depicts processing subsequent to FIG. 9 in which a source/drain implant is introduced into the elevated source/drain
• FIG. 11 depicts processing subsequent to FIG. 10 in which the gate electrode and source/drain regions are suicided.
• Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
• the present invention encompasses a semiconductor fabrication process, and the resulting transistor structure, in which a disposable spacer is used in conjunction with elevated source/drain processing to provide a reliable elevated source/drain process sequence.
• a disposable spacer is used in conjunction with elevated source/drain processing to provide a reliable elevated source/drain process sequence.
• the use of an offset spacer in conjunction with a disposable spacer beneficially prevents the formation of unwanted structures, such as "mouse ears" on the gate electrode, during the elevated source/drain formation sequence while still enabling the introduction of shallow implants after the elevated source/drain formation.
• a silicon nitride offset spacer is used to prevent formation of so-called "mouse ears" at the corners of the transistor gate electrode during epitaxial processing of the elevated source/drain.
• FIG. 1 a wafer 100 is depicted at a first selected stage of a fabrication process according to the present invention.
• wafer 100 is a silicon-on-insulator (SOI) wafer that includes a silicon layer 108 overlying a buried oxide (BOX) layer 104.
• BOX layer 104 is likely overlying a silicon bulk region (not depicted) of wafer 100.
• Silicon layer 108 is preferably single crystal silicon having a thickness of approximately 700 Angstroms and BOX layer 104 is preferably a silicon oxide compound such as silicon dioxide having a thickness of approximately 1400 Angstroms. As depicted in FIG. 1, wafer 100 includes a gate structure overlying silicon layer 108.
• the gate structure includes a gate dielectric 112 overlying silicon layer 108, a conductive gate electrode 110 overlying gate dielectric 112, and a capping layer 114 overlying gate electrode 110.
• gate dielectric 112 is a silicon oxide compound such as thermally formed silicon dioxide and gate electrode 110 is a conventional polysilicon gate electrode.
• gate dielectric 112 may include a "high-K" dielectric material (i.e., a dielectric having a dielectric constant greater than the dielectric constant of silicon dioxide) such as hafnium oxide (HfO) while gate electrode 110 may include one or more metal materials such as titanium, tantalum, and alloys thereof.
• Capping layer 114 preferably provides an antireflective coating (ARC) over gate electrode 110.
• capping layer 114 (also referred to herein as ARC 114) is a silicon nitride film.
• the elevated source/drain processing according to the present invention is initiated by forming a liner dielectric 120 on the exterior of gate electrode 110 and the upper surface of silicon layer 108.
• liner dielectric 120 is a relatively thin silicon oxide liner of approximately 23 Angstroms formed by thermally oxidizing polysilicon gate electrode 110 (and silicon layer 108).
• offset spacer 122 is formed on the sidewall of liner dielectric 120 adjacent the sidewalls of gate electrode 110.
• offset spacer 122 is formed by depositing silicon nitride on wafer 100 using a CVD reactor and thereafter anisotropically etching the deposited film to leave silicon nitride on vertically oriented surfaces such as the sidewalls of liner dielectric 120 while removing the silicon nitride from horizontally oriented surfaces such as the upper surface of liner dielectric 120 over silicon layer 108.
• offset spacer 122 contacts ARC 114 and thereby beneficially encloses or surrounds gate electrode 110 in silicon nitride to provide a protective barrier for the gate electrode during subsequent processing and, more specifically, during subsequent silicon formation processing.
• a 150 Angstrom thick layer of silicon nitride is deposited and etch to form offset spacer 122.
• a second liner dielectric 124 is formed on the sidewalls of offset spacer 122 and the upper surface of (first) liner dielectric 120.
• first liner dielectric 120 and 124 are preferably both silicon oxide compounds, the film is shown with a single reference numeral 124 overlying the silicon layer 108).
• second liner dielectric 124 is a CVD silicon-oxide film preferably having a thickness of approximately 150 Angstroms.
• first liner dielectric 120 is a thermally formed oxide and second liner dielectric is a CVD oxide
• the etch rate of first liner dielectric 120 in HF solution is significantly less than the etch rate of second dielectric 124.
• the slower etch rate of first liner dielectric 120 will ensure that first liner dielectric 120 beneficially remains intact during subsequent processing to protect the gate electrode and provide mechanical support for the offset spacer 122.
• a spacer referred to herein as disposable spacer 130, has been formed on the sidewalls of second liner dielectric 124 adjacent the offset spacer 122.
• disposable spacer is a silicon nitride spacer formed by depositing approximately 900 Angstroms of silicon nitride followed by an anisotropic silicon nitride etch. Disposable spacer 130 may then be subjected to a rapid thermal anneal (e.g., 5 seconds at 1060 °C) to "densify" the as-deposited silicon nitride. Disposable spacer 130 (in conjunction with capping layer 114 and offset spacer 122) serves as a mask that defines the portions of the underlying silicon wafer 108 on which an elevated source/drain structure will be formed. As depicted in FIG.
• silicon wafer 100 beneficially incorporates disposable spacer 130 that enables the formation of elevated source/drain regions prior to shallow implant processes, such as extension and halo implant processes, that would be negatively impacted by the high temperature process required to form the elevated source/drain epitaxially.
• the inclusion of the offset spacer 122 and ARC 114 protects gate electrode 110 during the high temperature silicon formation process thereby preventing the formation of so- called mouse ears at the corners of the gate electrode.
• wafer 100 as depicted in FIG. 5 is suitable for be subjected to an epitaxial or other high temperature, silicon formation process, such as an elevated source/drain formation process sequence, without jeopardizing the physical dimensions of the gate electrode structure.
• the presently described invention promotes superior repeatability and reliability by providing better protection of the gate electrode.
• the gate electrode 110 of the present invention is sealed within a silicon nitride enclosure formed when offset spacer 122 is formed in contact with ARC 114.
• offset spacer 122 provides a good etch stop during subsequent etch processing and a desirable offset spacer for shallow implants.
• an elevated silicon layer 132 is formed overlying the exposed portions of silicon layer 108 (i.e., the portions of silicon layer 108 covered by neither gate electrode 110 nor disposable spacer 130).
• the preferred embodiment of forming elevated source/drain layer 132 includes epitaxial growth of elevated source/drain layer 132 using a silicon-chloride source such as SiHCL 3 at a temperature in excess of 1000 °C.
• a thickness of elevated source/drain layer 132 in one implementation is in the range of approximately 200 to 300 Angstroms.
• the presence of disposable spacer 130 during the epitaxial processing prevents formation of the epitaxial layer below the spacer.
• the presence of offset spacer 122 and ARC 114 prevent the epitaxial processing from affecting the profile of gate electrode 110.
• a thin (i.e., less than 25 Angstroms) layer of oxide is thermally grown overlying elevated source/drain 132.
• This thin oxide which is subsequently stripped, is a sacrificial layer that consumes contaminants and imperfections at the upper surface of the epitaxial film.
• disposable spacer 130 and second liner dielectric 124 are removed without removing offset spacer 122 to expose portions of silicon layer 108 in close proximity to gate electrode 110 (displaced laterally from gate electrode 110 only by the combined thickness of liner 120 and offset spacer 122).
• Disposable spacer 130 is preferably removed by dipping wafer 100 in a phosphoric acid solution heated to 180 °C while second liner dielectric 124 is removed with an HF dip or another suitable etching process. If the HF is properly controlled, the thermally formed first liner dielectric 120 underlying offset spacer 122 will remain intact after CVD second liner dielectric 124 is removed due to differences in their respective etch rates in HF.
• the oxide-nitride-oxide-nitride layering of liner 120, spacer 122, liner 124, and spacer 130 enables the separate removal of each film thereby facilitating the removal of disposable spacer 130 without affecting offset spacer 122.
• offset spacer 122 beneficially protects the sidewalls of gate electrode 110 during removal of second liner dielectric 124.
• the removal of disposable spacer 130 also removes ARC 114 (as seen in FIG. 7).
• the removal of spacer 130 and liner 124 exposes the upper surface of silicon layer 108 proximal to gate electrode 110.
• shallow implants including a halo implant represented by reference numeral 140 and an extension implant represented by reference numeral 142 are performed.
• Halo implant 140 is a angled implant that introduces an impurity of the same species as the well region in which it is introduced.
• Extension implant 142 introduces an opposite type impurity into each well region.
• Halo implant 140 is a P-type dopant such as boron while extension implant 142 is an N-type dopant such as phosphorous or arsenic.
• offset spacer 122 which has a thickness of approximately 100 Angstroms during the shallow implants is beneficial in optimizing the location of the implanted impurity distributions relative to gate electrode 110 and the underlying transistor channel.
• a third liner dielectric 134 and a replacement spacer 136 are formed where disposable spacer 130 and line 124 existed previously to cover the portion of silicon layer 108 exposed when the disposable spacer was removed.
• liner 134 and spacer 136 are substantially equivalent to the formation of second liner dielectric 124 and disposable spacer 130.
• third liner dielectric 134 is a silicon oxide layer while replacement spacer 136 is silicon nitride.
• a source/drain implant represented by reference numeral 140 is performed to introduce a source/drain impurity distribution having a relatively high impurity concentration into elevated source/drain 132.
• source/drain implant 140 is an N-type dopant such as arsenic or phosphorous while a P-type dopant is used for PMOS transistors.
• a rapid thermal anneal process may be performed following source/drain implant 140 to activate the implanted species.
• a likely embodiment of this anneal would expose the wafer 100 to a temperature of approximately 1000 °C for a duration of approximately 5 seconds.
• suicide processing of wafer 100 is performed by depositing a metal such as cobalt that is reactive with silicon over wafer 100. The wafer is then heated to react the metal with silicon (where the metal overlies silicon) to form silicide structures identified by reference numeral 150 in a manner that will be familiar to those skilled in semiconductor wafer fabrication. Silicide 150 forms overlying the elevated source/drain region 130 as well as overlying silicon gate 110.
• the silicide 150 extends entirely through the elevated source/drain 132 and partially into the underlying silicon layer 108.
• the resulting transistor 160 includes a gate electrode 110 overlying a transistor channel region 162.
• a silicided and elevated source/drain region is laterally displaced from gate electrode 110.
• An offset spacer 122 and a replacement spacer 136, both comprised of silicon nitride are located between gate electrode 110 and elevated source/drain 132.
• a first liner oxide 120 is located between offset spacer 122 and gate electrode 110 while the third liner oxide 134 is positioned between offset spacer 122 and replacement spacer 136.

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• 2004
  • 2004-05-05 US US10/839,385 patent/US7125805B2/en not_active Expired - Lifetime
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