DE602005017490D1 - Verfahren zur halbleiterherstellung mit integration einer wegwerf-abstandsschicht in die erhöhte source-/drain-verarbeitung - Google Patents

Verfahren zur halbleiterherstellung mit integration einer wegwerf-abstandsschicht in die erhöhte source-/drain-verarbeitung

Info

Publication number
DE602005017490D1
DE602005017490D1 DE602005017490T DE602005017490T DE602005017490D1 DE 602005017490 D1 DE602005017490 D1 DE 602005017490D1 DE 602005017490 T DE602005017490 T DE 602005017490T DE 602005017490 T DE602005017490 T DE 602005017490T DE 602005017490 D1 DE602005017490 D1 DE 602005017490D1
Authority
DE
Germany
Prior art keywords
spacer
gate electrode
silicon nitride
disposable
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602005017490T
Other languages
German (de)
English (en)
Inventor
Jian Chen
Rode R Mora
Marc A Rossow
Yasuhito Shiho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of DE602005017490D1 publication Critical patent/DE602005017490D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
DE602005017490T 2004-05-05 2005-04-13 Verfahren zur halbleiterherstellung mit integration einer wegwerf-abstandsschicht in die erhöhte source-/drain-verarbeitung Expired - Lifetime DE602005017490D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/839,385 US7125805B2 (en) 2004-05-05 2004-05-05 Method of semiconductor fabrication incorporating disposable spacer into elevated source/drain processing
PCT/US2005/012252 WO2005112099A2 (en) 2004-05-05 2005-04-13 Method of semiconductor fabrication in corporating disposable spacer into elevated source/drain processing

Publications (1)

Publication Number Publication Date
DE602005017490D1 true DE602005017490D1 (de) 2009-12-17

Family

ID=35239953

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005017490T Expired - Lifetime DE602005017490D1 (de) 2004-05-05 2005-04-13 Verfahren zur halbleiterherstellung mit integration einer wegwerf-abstandsschicht in die erhöhte source-/drain-verarbeitung

Country Status (9)

Country Link
US (1) US7125805B2 (enExample)
EP (1) EP1756860B1 (enExample)
JP (1) JP5048480B2 (enExample)
KR (1) KR20070007900A (enExample)
CN (1) CN1998072B (enExample)
AT (1) ATE447765T1 (enExample)
DE (1) DE602005017490D1 (enExample)
TW (1) TWI377625B (enExample)
WO (1) WO2005112099A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100668954B1 (ko) * 2004-12-15 2007-01-12 동부일렉트로닉스 주식회사 박막트랜지스터 제조 방법
US7745296B2 (en) * 2005-06-08 2010-06-29 Globalfoundries Inc. Raised source and drain process with disposable spacers
US20070056930A1 (en) * 2005-09-14 2007-03-15 International Business Machines Corporation Polysilicon etching methods
US7514331B2 (en) * 2006-06-08 2009-04-07 Texas Instruments Incorporated Method of manufacturing gate sidewalls that avoids recessing
US7510923B2 (en) * 2006-12-19 2009-03-31 Texas Instruments Incorporated Slim spacer implementation to improve drive current
US7550808B2 (en) * 2007-01-18 2009-06-23 International Business Machines Corporation Fully siliciding regions to improve performance
JP2009158677A (ja) * 2007-12-26 2009-07-16 Renesas Technology Corp 半導体装置の製造方法及び混成トランジスタ用半導体装置の製造方法
JP6169222B2 (ja) * 2012-01-23 2017-07-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5968708B2 (ja) 2012-01-23 2016-08-10 ルネサスエレクトロニクス株式会社 半導体装置
US9171927B2 (en) 2013-03-26 2015-10-27 GlobalFoundries, Inc. Spacer replacement for replacement metal gate semiconductor devices
CN103412444B (zh) * 2013-07-23 2015-08-26 北京京东方光电科技有限公司 一种阵列基板及其制作方法和显示面板
JP6279291B2 (ja) * 2013-11-18 2018-02-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9773865B2 (en) 2014-09-22 2017-09-26 International Business Machines Corporation Self-forming spacers using oxidation
US11653498B2 (en) * 2017-11-30 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device with improved data retention
JP7034834B2 (ja) 2018-05-30 2022-03-14 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US11437245B2 (en) * 2020-09-30 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium hump reduction

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200352A (en) * 1991-11-25 1993-04-06 Motorola Inc. Transistor having a lightly doped region and method of formation
US5496750A (en) * 1994-09-19 1996-03-05 Texas Instruments Incorporated Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition
JP2848299B2 (ja) * 1995-12-21 1999-01-20 日本電気株式会社 半導体装置及びその製造方法
US5847428A (en) * 1996-12-06 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit gate conductor which uses layered spacers to produce a graded junction
TW469648B (en) * 1999-09-07 2001-12-21 Sharp Kk Semiconductor device and its manufacture method
US6555437B1 (en) * 2001-04-27 2003-04-29 Advanced Micro Devices, Inc. Multiple halo implant in a MOSFET with raised source/drain structure
US20020171107A1 (en) * 2001-05-21 2002-11-21 Baohong Cheng Method for forming a semiconductor device having elevated source and drain regions
US6429084B1 (en) * 2001-06-20 2002-08-06 International Business Machines Corporation MOS transistors with raised sources and drains
US6614079B2 (en) * 2001-07-19 2003-09-02 International Business Machines Corporation All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS
JP2004095639A (ja) * 2002-08-29 2004-03-25 Fujitsu Ltd 半導体装置及びその製造方法
US6800530B2 (en) * 2003-01-14 2004-10-05 International Business Machines Corporation Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors
US20050048732A1 (en) * 2003-08-26 2005-03-03 International Business Machines Corporation Method to produce transistor having reduced gate height

Also Published As

Publication number Publication date
WO2005112099A2 (en) 2005-11-24
JP2007536734A (ja) 2007-12-13
EP1756860A4 (en) 2008-12-17
CN1998072A (zh) 2007-07-11
ATE447765T1 (de) 2009-11-15
EP1756860B1 (en) 2009-11-04
JP5048480B2 (ja) 2012-10-17
US20050250287A1 (en) 2005-11-10
KR20070007900A (ko) 2007-01-16
CN1998072B (zh) 2010-09-15
TW200625463A (en) 2006-07-16
WO2005112099A3 (en) 2006-04-27
US7125805B2 (en) 2006-10-24
EP1756860A2 (en) 2007-02-28
TWI377625B (en) 2012-11-21

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