WO2005067139A1 - 増幅器 - Google Patents
増幅器 Download PDFInfo
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- WO2005067139A1 WO2005067139A1 PCT/JP2004/019526 JP2004019526W WO2005067139A1 WO 2005067139 A1 WO2005067139 A1 WO 2005067139A1 JP 2004019526 W JP2004019526 W JP 2004019526W WO 2005067139 A1 WO2005067139 A1 WO 2005067139A1
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- 239000003990 capacitor Substances 0.000 description 12
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/34—DC amplifiers in which all stages are DC-coupled
- H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0261—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A
- H03F1/0266—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the polarisation voltage or current, e.g. gliding Class A by using a signal derived from the input signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3276—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using the nonlinearity inherent to components, e.g. a diode
Definitions
- the present invention relates to an amplifier, and more particularly to an amplifier for amplifying and outputting input power by a plurality of transistors connected in multiple stages, which is used for wireless communication performing wide-range output power control.
- a base bias circuit operating close to a constant voltage source is indispensable.
- the reason why a constant voltage source is more suitable than a constant current source as a bias circuit is as follows.
- the collector current of the emitter-grounded bipolar transistor increases and reaches several times or more of the collector bias current. This increase in collector current results in higher saturation power and lower distortion.
- the collector current is always kept at hFE times the base bias current, so even if the input power is increased, the collector current does not increase.
- the collector bias current is set equal to the base bias provided by a constant voltage source, gain compression at large signal operation will occur at lower input power. That is, the saturation characteristics deteriorate, leading to a decrease in added power efficiency and a deterioration in linearity.
- the collector bias current is set equal to the collector current when the base bias is given by a constant voltage source and the input power is large, the RF signal is not input or the input power is small. Also, a large collector current flows, causing problems such as increased power consumption.
- a power amplifier using an emitter-grounded neupolar transistor is A base bias circuit that operates close to a constant voltage source is essential.
- a base bias circuit operating close to a constant voltage source there is a first conventional amplifier described in Japanese Patent No. 3377675. This is shown in FIG. The operation of this circuit will be described according to the embodiment of Japanese Patent No. 33 77 675.
- FIG. 1 is a circuit diagram of a first conventional amplifier of patent 3377675
- FIG. 2 is A graph showing the voltage applied to the base and the diode of the transistor in the circuit shown in FIG. 1
- FIG. 3 is graphs showing the input / output characteristics of the circuit of FIG.
- the applied voltage at point B1 on the base side is the voltage applied from the external voltage source VB, for example, by resistors R1 and R2.
- a diode D1 is further inserted between the point B2 and the point B1 in the figure so that the B1 point side becomes the force-sword terminal side of the diode.
- a capacitor C1 is inserted between the B2 point and the ground potential so that the B2 point force is sufficiently smaller than the impedance seen from the bias resistance side and the impedance value is obtained.
- the amplitude of the voltage of the input power is sufficiently small as shown by VI in FIG. 5 (see FIG. 9 of patent 3377675).
- the transistor Trl is in linear motion th
- the gain 'input and output power phase deviations are both constant. However, as the input power increases as shown by V2 in Fig. 5, the voltage amplitude V2 at point B1 increases, and the bias voltage VB1 given at point B1 and the ON voltage V of the diode between the base and emitter
- transistor Trl When the potential difference of th is exceeded, transistor Trl enters a non-linear operating state, and the operating point as class A can not be maintained, and the power gain gradually decreases. Also, if the voltage value at point B1 fluctuates to the potential below the ON voltage V of the diode between the base and emitter, the above transistor Trl
- an on state time and an off state time occur.
- the input impedance of the diode between the base 'emitters is equal to that when maintaining the class A operating point, but when it is in the off state, the diode between the base' emitters is Since the input impedance of H is high compared to when the A class operating point is maintained, the voltage value at point B1 at that time largely fluctuates to the negative side.
- the voltage value at point B1 was constant at V in time average, but the above-mentioned off state
- the time average is a voltage value smaller than V.
- the capacitance value of the connection has voltage dependency. Therefore, when the voltage applied between the base and emitter fluctuates, the junction capacitance of the diode between the base and emitter fluctuates, and when the input impedance of the emitter-grounded amplifier is small enough to maintain class A operation. It has a different value than.
- the potential at point B2 is determined by the voltage value of the constant voltage source and the division ratio of the resistors R1 and R2, and is not affected by the increase in input power, so the potential at point B1 is gradually increased as described above.
- the voltage AVBE2 applied to the diode D1 shown in Fig. 1 gradually increases as shown in Fig. 2. Therefore, the junction capacitance of the diode D1 in the bias circuit performs the reverse fluctuation to the fluctuation of the junction capacitance of the base of the transistor Trl of the emitter ground and the emitter of the diode.
- the amplitude of the input power increases, and the input impedance of the emitter-grounded transistor Trl fluctuates accordingly, so that the impedance of the force diode D1 fluctuates so as to cancel it. Therefore, the fluctuation of the input impedance of the emitter-grounded transistor Tr1 can be suppressed, and the passing phase deviation can be made smaller than that of the conventional circuit. Furthermore, when the voltage applied to the diode D1 increases, the current flowing into the base of the transistor Tr1 through the diode D1 increases, so that the collector current increases and saturation of the output power at the collector end can be eliminated. The reduction in gain can also be improved.
- the bipolar transistor Tr2 is The base 'emitter of the transistor Tr2 is connected in the forward direction between point B2 of the base bias circuit which divides the power supply voltage VB by the resistors R1 and R2 and the base of the transistor Tr1, and is connected to the collector of the transistor Tr2.
- Supply voltage VC is applied.
- the base force also has an impedance sufficiently smaller than the impedance when looking at the bias resistors R1 and R2. Capacitor C1 is inserted.
- This second conventional amplifier utilizes the PN junction between the base and the emitter of the transistor Tr2 as opposed to the one utilizing the PN junction of the diode D1 provided in the base bias circuit shown in FIG.
- the operation of the circuit is substantially the same as in the first prior art amplifier shown in FIG. 1 with the diode D1 in the base bias circuit.
- the transistor Tr2 since the transistor Tr2 forms an amplification circuit, the base bias current is amplified by the transistor Tr2 and supplied to the base of the emitter-grounded transistor Tr1. Therefore, it is possible to reduce the current flowing in the base bias circuit which generates the original base bias which is constituted by the resistors R 1 and R 2.
- the current flowing to the base of the transistor Tr2 can be neglected in the second conventional amplifier as well as the first conventional amplifier even though it is reduced. It is similar to the first problem that the current flowing to the Furthermore, since the emitter-grounded bipolar transistor has an extremely high transconductance, it is necessary to strictly apply the voltage to be applied to the base.
- the first and second biases are applied by resistance division by the resistors Rl and R2.
- the circuit also has a second problem that it is greatly affected by the voltage fluctuation between the base and the emitter due to temperature and manufacturing variations.
- FIG. 6 A circuit diagram of a third conventional amplifier is shown in FIG. 6 (see FIG. 5 of Japanese Patent Application Laid-Open No. 2002-9 559).
- the resistor 18 is not directly grounded, but is grounded via a reference voltage circuit consisting of a neupolar transistor Tr19 and a bipolar transistor Tr20.
- the potential at the base of the bipolar transistor Tr19 is equal to the sum of VBE of the bipolar transistor Tr20 and VBE of the bipolar transistor Trl9.
- the present circuit is configured by comparing the collector current density of the bipolar transistor Tr20 and the power transistor Tr.
- the 22 collector current densities are designed to be equal. Therefore, VBE of the bipolar transistor Tr20 and VBE of the power transistor Tr22 are equal.
- the base current of power transistor Tr22 is equal to the emitter current of bipolar transistor Tr21
- the base current of bipolar transistor Tr20 is equal to the emitter current of bipolar transistor Trl9
- the emitter area of bipolar transistor Tr20 is bipolar transistor Trl 9
- the emitter area of the power transistor Tr22 is set larger than that of the bipolar transistor Tr21. Therefore, the VBE of the bipolar transistor Tr21 is larger than the VBE of the bipolar transistor Trl9.
- the voltage drop across the resistor 18 is equal to the difference between the VBE of the bipolar transistor Tr21 and the VBE of the bipolar transistor Trl9.
- Tr22 Tr20 is equal to the relationship of the area ratio of power transistor Tr22 and bipolar transistor Tr20.
- the area of the power transistor Tr22 is S
- the area of the bipolar transistor Tr20 is S.
- This circuit can alleviate the second problem described above because the changes in VBE due to temperature and manufacturing variations cancel each other out. Also with regard to the first problem described above, the increase in input power Since the decrease in VBE of the power transistor Tr22 does not affect the VBE of the bipolar transistor Tr20 and does not cancel it, it can operate close to a constant voltage source.
- the emitter grounded amplification circuit operating in the vicinity of class B is biased by the bias circuits of the aforementioned first to third conventional amplifiers operating in the vicinity of a constant voltage source.
- the emitter-grounded amplifier biased in a state near class B causes gain expansion as shown in Fig. 7 because the base current increases as the input power increases due to the rectifying action of the diode between the base and emitter.
- An amplifier having this gain extension characteristic is a wide band with a power change like a W-CDMA signal.
- Inputting a modulated signal causes gain fluctuation, which causes a third problem that the signal is distorted.
- the distortion of this signal appears as a disturbance to the adjacent channel next to the communication channel as shown in FIG.
- the ratio of the signal strength of the communication channel to the disturbance strength of the adjacent channel is called the adjacent channel leakage power (ACPR).
- a represents the amplification factor (ie, gain), and the remainder represents the variation of the gain with respect to the input amplitude (ie, whether it is gain expansion or gain compression). Also, the frequency component 2 ⁇ — ⁇ of V is out 1 2
- Vout It becomes + 5 j sin (2- ⁇ 2 ) ⁇ (7).
- (7) is a third-order intermodulation distortion ( ⁇ 3) component of V. Where a and a, a have the same sign out 1 3 5
- the phase can not be defined for signals of different frequencies, but in this case the signal shown in (5) is used for the input, so the frequency ( ⁇ ⁇ ⁇ ).
- phase angles of the fundamental wave and ⁇ 3 that are identical ( ⁇ - ⁇ ) ⁇ 2 ⁇ apart are 2
- phase of ⁇ 3 obtained by amplifying the distortion at the former stage and the phase of ⁇ 3 generated by amplifying the fundamental wave at the latter stage differ by ⁇ 90 degrees or more, the distortion cancellation phenomenon occurs. Therefore, in the following, for the sake of simplicity, when the phase angle of the fundamental wave and ⁇ 3 is within 90 °, “phase is the same”, and when it is more than that, “phase is inverse”.
- FIG. 10 shows the relationship between the fundamental wave and the phase of the ⁇ 3 signal when the third conventional amplifier shown in FIG. 6 is biased to ⁇ class close to ⁇ ⁇ class and analyzed.
- the magnitude of the ⁇ 3 signal is smaller than that of the fundamental wave, so it is displayed 10 times larger.
- the absolute value of the phase does not have any particular meaning because it merely represents the delay of input and output.
- Fig. 11 shows how gain expansion is performed at that time.
- FIG. 11 the input power range depicted in FIG. 10 is indicated by an arrow.
- gain In the amplifier that exhibits tension characteristics the phases of the fundamental wave and IM3 are the same.
- Figure 13 shows an example of the relationship between the fundamental wave and the IM3 signal phase when analysis is performed using the gain expansion amplifier using the variable gain amplifier and multiplier shown in Fig. 12.
- the size of IM3 is shown enlarged 10 times.
- the phases of the fundamental wave and IM3 are the same.
- Fig. 14 shows how gain expansion is performed at that time.
- Figure 14 shows the gain extension characteristics.
- the reason why the distortion can be reduced by combining the gain expansion amplification stage and the gain compression amplification stage is that the phase angle of the fundamental wave and IM3 is inverted in each stage. This is because the amplified signal and the IM3 generated by amplifying the fundamental wave in the latter stage have an opposite phase and cancel each other.
- the first amplifier stage in FIG. 9 has a gain expansion characteristic such that the gate bias of the FET amplifier circuit is B class and the second amplifier stage has a gain compression characteristic.
- the base stage of the HBT amplification circuit is class AB and the second amplification stage is the first amplification stage in FIG. 9 so as to have gain extension characteristics.
- the gate bias of the HBT amplifier circuit is set to class A so as to have gain compression characteristics, the gain extension characteristics and the gain compression characteristics are canceled and distortion is reduced.
- the first amplification stage in FIG. 9 has the gate bias of the MES amplification circuit as class A and the second amplification stage so as to have gain compression characteristics.
- the gate bias of the MOS amplifier circuit By setting the gate bias of the MOS amplifier circuit to class AB to have gain expansion characteristics Cancel the gain expansion characteristics and the gain compression characteristics to reduce distortion.
- the base bias of the HBT amplification circuit is set to class AB or C so that the first amplification stage in FIG.
- the gain expansion characteristics and gain compression characteristics are canceled and distortion is reduced by setting the gate bias of the HBT amplifier circuit to class A so that the amplification stage has gain compression characteristics.
- these conventional examples are generally referred to as a fourth conventional amplifier.
- These fourth conventional amplifiers combine the gain expansion amplifier stage and the gain compression amplifier stage to reduce distortion, so all amplifiers with good power addition efficiency and power expansion efficiency at low output power are available. It has the fourth problem that it can not be applied to the amplification stage of
- differential frequency injection as exemplified in Japanese Patent 3337766 and Japanese Patent Laid-Open No. 2003-338713. There is technology.
- FIG. 17 is an explanatory view of distortion compensation by second-order distortion (difference frequency) injection shown in FIG. 9 of Japanese Patent No. 3337766.
- the injection amount D is selected to a (negative) appropriate value, the IM3 component shown in equation 10 can be reduced at an input amplitude ⁇ ⁇ . Therefore, it is necessary to choose an injection amount D that reduces IM3 independently of the value of the input amplitude A! /, So it is necessary to optimize the injection amount in some way such as feedback or feedforward.
- Patents 3337766 and 2003-338713 are generally referred to as a fifth conventional amplifier.
- the optimal injection amount depends on the input amplitude, there is a fifth problem when it is necessary to adjust the injection amount by feedback or feed forward.
- the problems with the first to third conventional amplifiers are that when used in a state close to class B and used to increase power addition efficiency at low output, Signal distortion is the result of gain extension.
- the problem with the fourth conventional amplifier is the amplifier stage with high power added efficiency at low output because the third problem described above is present. The problem is that you can not use it for all stages.
- the problem with the fifth conventional amplifier is that the injection of the difference frequency signal depends on the input amplitude because the optimum injection amount depends on the input amplitude. It is necessary to adjust the injection volume by
- a first object of the present invention is to provide a means for inverting distortion to an amplification stage having gain expansion characteristics.
- a second object of the present invention is to use an amplification stage having gain expansion characteristics in all stages of a multistage amplifier by bypassing in a state close to class B with high power addition efficiency at low output. It is about providing the method.
- a third object of the present invention is to control the optimum amount of feedback and feedforward by using an amplifier stage biased in a state close to class B and having gain expansion characteristics in all stages of a multistage amplifier. To offer without doing.
- An amplifier according to the present invention is an amplifier having a gain expansion characteristic in which a gain increases with an increase in the input power or the output power in a certain range of input power or output power.
- the phase characteristic of third-order intermodulation distortion at the moment when the phase of the two signals becomes the same when the two signals are input has an output characteristic that rotates 90 degrees or more from the phase of the two signals. It is characterized by
- the distortions of the respective stages can be offset each other.
- amplification stages with gain expansion characteristics can be used in all stages of multistage amplifiers by biasing in a state close to class B with high power addition efficiency at low output.
- FIG. 1 is a circuit diagram illustrating a first conventional amplifier.
- FIG. 2 is a diagram for explaining the potential difference at each point with respect to the input power of the first conventional amplifier.
- FIG. 3 is a diagram for explaining gain and phase variations with respect to input power of a first conventional amplifier.
- FIG. 4 is a circuit diagram illustrating a second conventional amplifier.
- FIG. 5 is a diagram for explaining a first conventional amplifier.
- FIG. 6 is a circuit diagram illustrating a third conventional amplifier.
- FIG. 7 is a circuit diagram illustrating gain expansion characteristics.
- FIG. 8 is a diagram for explaining adjacent channel leakage power (ACPR).
- ACPR adjacent channel leakage power
- FIG. 9 is a diagram for explaining a fourth conventional amplifier.
- Figure 10 This figure shows the relationship between the fundamental wave and the IM3 signal phase when the third conventional amplifier is biased to class AB close to class B.
- FIG. 11 is a diagram for explaining the relationship between input power and gain when the third conventional amplifier is biased to class AB close to class B.
- FIG. 12 is a circuit diagram illustrating a gain extension amplifier.
- ⁇ 13] A diagram illustrating the phase relationship between the fundamental wave and distortion in a general gain extension amplifier.
- ⁇ 15] A diagram illustrating the phase relationship between the fundamental wave and distortion in a general gain compression amplifier.
- FIG. 12 is a diagram for explaining the relationship between input power and gain when a gain compression amplifier is formed in the circuit of FIG.
- Fig. 17 is a diagram for describing a fifth conventional amplifier.
- FIG. 18 A diagram for explaining the phase relationship between a fundamental wave and distortion of a second conventional amplifier circuit.
- FIG. 19 is a diagram for explaining the relationship between the output power and the gain of the second conventional amplifier circuit.
- FIG. 20 is a diagram for explaining the relationship between the voltage between the base and emitter of the transistor Tr1 of the second conventional amplifier circuit and the emitter current of the transistor Tr2.
- FIG. 21 A diagram for explaining the phase relationship between the fundamental wave and distortion of the second conventional amplifier circuit.
- FIG. 22 is a diagram for explaining the relationship between the output power and the gain of the second conventional amplifier circuit.
- FIG. 24 A diagram for explaining the phase relationship between a fundamental wave and distortion of a second conventional amplifier circuit.
- ⁇ 24 is a diagram showing a first embodiment of the present invention.
- FIG. 25 is a circuit diagram for explaining a second embodiment of the present invention.
- FIG. 26 is a diagram for explaining the phase relationship between a fundamental wave and distortion in the second embodiment of the present invention.
- ⁇ 27] is a diagram showing a second embodiment of the present invention.
- ⁇ 28 It is a circuit diagram for explaining a second embodiment of the present invention.
- FIG. 30 is a diagram showing a third embodiment of the present invention.
- FIG. 31 is a diagram showing a fourth embodiment of the present invention.
- FIG. 32 is a diagram showing a fifth embodiment of the present invention.
- FIG. 33 is a diagram showing a sixth embodiment of the present invention.
- FIG. 34 is a circuit diagram for explaining a sixth embodiment of the present invention.
- FIG. 35 is a diagram for explaining the phase relationship between a fundamental wave and distortion in the sixth embodiment of the present invention.
- FIG. 36 A diagram for explaining the relationship between the momentary potential of the emitter potential of the transistor 26 and the current supplied to the emitter of the transistor 26 in the sixth embodiment of the present invention.
- FIG. 37 is a diagram showing the concept of distortion cancellation in a multistage amplifier according to a seventh embodiment of the present invention.
- FIG. 38 is a diagram showing a seventh embodiment of the present invention.
- FIG. 39 is a circuit diagram for explaining a seventh embodiment of the present invention.
- FIG. 40 is a circuit diagram for explaining a seventh embodiment of the present invention.
- FIG. 41 is a view for explaining distortion cancellation according to the seventh embodiment of the present invention.
- the amplifier according to the present invention amplifies input power to output power, and gain expansion characteristics in which gain increases with increase of the input power or the output power in a certain range of the input power or the output power.
- the amplifier is characterized in that the amplifier has a mechanism for compressing the amplitude at a high frequency at its input.
- the input power is amplified to be output power, and at least two or more amplification stages are the input power or the output within a range of the input power or the output power.
- a multi-stage amplifier with gain expansion characteristics where the gain increases with increasing power, with at least one of the amplification stages (in the gain expansion power range) compressing the amplitude at high frequency at the input It is characterized by having a mechanism.
- the amplifier according to the present invention has an amplitude compression characteristic such that the instantaneous amplitude of the amplifier input is compressed, thereby providing a gain expansion characteristic and an amplification having the characteristic that the phase of the fundamental wave and that of IM3 are reversed.
- the distortion appearing at the output is reduced by canceling out the distortion between the stage and the normal amplification stage which also has the same gain expansion characteristics and the characteristic that the phase of the fundamental wave and the IM3 are the same.
- the second conventional amplifier shown in FIG. 4 the case where terminal B 2 is biased by a constant voltage source will be described as an example (when the input power is increased, as described above).
- the first problem of lowering the potential of B2 is avoided by biasing B2 with a constant voltage source, and the second problem of temperature and manufacturing variation is not assumed here).
- the second conventional amplifier When the second conventional amplifier is used at a bias close to class B, it can be an amplifier that inverts distortion in the gain extension region by satisfying a certain condition.
- FIG. 18 shows the relationship between the fundamental wave and IM3 phase when amplifier A is interpreted as amplifier A with the ratio of the area of Trl: Tr2 being 5: 1.
- IM3 is displayed 50 times larger.
- FIG. 19 shows the relationship between output power and gain at this time. Since the power range shown in Figure 18 is the gain extension range of output power less than 16dBm, the gain extension power range is But the phases of the fundamental and IM3 are reversed.
- Figure 20 shows the relationship between the instantaneous value of VBE of transistor Trl and the current supplied by the transistor Tr2.
- This figure is a load line representing the internal impedance of the transistor Tr2.
- the two lines shown in the figure represent load lines near the maximum amplitude (when the two frequencies are just added) when two frequencies are input and the output is 16 dBm and 6 dBm.
- the output impedance of Tr2 when the base potential is lowered is extremely small when the amplitude is large compared to when the amplitude is small.
- an amplifier B is obtained by enlarging the area of Trl by 7.2 times and making the ratio of the area of Trl: the area of Tr2 36: 1. Then, the relationship between the fundamental wave and the phase of IM3 when the amplifier B is analyzed is shown in FIG. IM3 is also enlarged 50 times and displayed.
- Figure 22 shows the relationship between output power and gain at this time.
- the power range shown in Fig. 21 is the gain expansion range of the output power of 16 dBm or less.
- the fundamental wave and the phase of IM3 are the same. This is because the input impedance of the base of Trl is lowered by expanding the area of Trl, and the influence of the change in impedance of the bias circuit becomes small. This is also reworded as the input power for applying the amplitude until the output impedance of Tr2 is lowered, because the voltage amplitude at the same input power is reduced by lowering the base impedance of Tr1.
- the input impedance of the amplification transistor side viewed from the input terminal By making one dance appear large, amplifier distortion causes the lower input amplitude force fundamental wave and IM 3 to have opposite phases, and cancels distortion with an amplifier whose latter stage fundamental wave and IM 3 have the same phase. Then, it is possible to use an amplification stage close to an efficient class B at low output power for all stages of the amplifier.
- the distortion generated in the former stage and the distortion generated in the latter stage are offset! /.
- IM3 increases three times as much as the increase in input power, so the distortion amount at the former stage and the latter stage increases together. Therefore, according to the present invention, it is possible to control the input power without performing the optimum control according to the input power 4 _ such as feedback and feedforward.
- the distortion reduction effect can be obtained in a wide range.
- the distortion of the gain expansion amplifier can be reduced by providing amplitude compression at the input unit
- the case of injecting the third harmonic of the main signal is considered.
- V in a e A ⁇ sin ⁇ ⁇ ⁇ + sm ⁇ 2 ⁇ + Z) (sin 3 ⁇ w + sin 3 ⁇ 3 ⁇ 4 2 ⁇ ) ⁇ (1 1) of two waves of the sine wave and mosquitoes ⁇ the third harmonic It is assumed that If the third wave is added to the sine wave, the third wave will have an antiphase peak value at the peak value of the fundamental wave, so the maximum amplitude will be compressed.
- the IM3 component shown in (13) can be reduced at an input amplitude A where the injection amount D is selected to an appropriate value.
- the distortion can be reduced in the range of input amplitude A, relatively wide, even if fixed at.
- FIG. 24 is a diagram showing an amplifier for reversing the phase of IM 3 with respect to a fundamental wave according to a first embodiment of the present invention.
- the amplification transistor 1 forms an emitter-grounded amplification circuit, and the base of the transistor 1 is connected to the force matching of the input matching circuit 3 and the bias supply diode 4 via the impedance element 2.
- the anode of the bias supply diode 4 is connected to a reference power supply 5 which has a sufficiently low impedance at high frequencies.
- the collector of transistor 1 is connected to collector power supply 7 via load 6 and connected to output terminal 9 via output matching circuit 8.
- FIG. 24 showing the present embodiment corresponds to FIG. 1 showing the first conventional example. Comparing the first embodiment shown in FIG. 24 with the first conventional example shown in FIG. 1, according to the prior art, the force source of the bias supply diode D1 is directly connected to the base terminal of the amplification transistor Tr1. On the other hand, in the present embodiment, the force source of the bias supply diode 4 is connected to the amplification Trl via the impedance element 2 !. By connecting the impedance element 2, the input impedance of the amplification transistor 1 viewed from the input terminal 10 is made high, and a state in which the phase of the fundamental wave and that of IM3 are reversed is achieved at a low input power.
- FIG. 27 is a diagram showing an amplifier for reversing the phase of IM 3 with respect to a fundamental wave according to a second embodiment of the present invention, which is a diagram of a second prior art example. It corresponds to In this embodiment, instead of the diode 4 of the first embodiment, the base-emitter of the noise supply transistor 11 is used. Therefore, the effects and operations are the same as in the first embodiment.
- the present embodiment when the reference power supply 5 is realized by a resistor, the above-mentioned second problem that a voltage drop due to the resistor occurs can be alleviated. Also in the present embodiment, since the noise is supplied to the amplification transistor 1 via the impedance element 21, the impedance element 21 does not block direct current.
- the present embodiment is substantially the same as the above-described first embodiment in effect and operation, and therefore, the present embodiment will be collectively described in the following.
- FIG. 25 is a view for explaining the second embodiment of the present invention by a more specific example.
- the base-emitter of the bias supply transistor 11 is considered as a bias supply diode 4.
- FIG. 25 shows a more specific example using a parallel circuit of a resistor 13 and a capacitor 14 as the impedance element 2.
- the reference power supply 5 the reference power supply 35 having the same configuration as that of the third conventional amplifier shown in FIG. 6 was used.
- the base of the bias supply transistor 11 was grounded using the capacitance 19 so as to have a sufficiently low impedance in high frequency.
- a GaAs heterojunction bipolar transistor As a transistor model for analysis, a GaAs heterojunction bipolar transistor (HBT) is used, and as amplification transistor 1, an array of five 120 ⁇ m 2 unitary elements is used, and an impedance element is used. Resistor 2 of 2 is configured by arranging five 250 ⁇ resistors in parallel and also serving as a ballast resistor of transistor 1, and capacitor 14 of impedance element 2 is configured by connecting five 0.8 pF capacitors in parallel.
- An HBT with an emitter area of 120 / zm 2 was used as the noise supply transistor 11.
- an HBT with an emitter area of 30 m 2 was used for the transistors 15 and 16 of the reference power supply 35.
- a capacitance 19 in the reference power supply 35 As a capacitance 19 in the reference power supply 35, a capacitance of 2 pF was used. As the load 6, a line having a length of 1 ⁇ 4 wavelength with respect to the fundamental wave was used, and for the collector power supply 7 and the bias power supply 12, a constant voltage source of 3.5 V was used.
- the circuit parameters of the reference power supply 35 and the control power supply 20 are set so that the collector current of the amplification transistor 1 becomes 5 mA when there is no input signal from the input terminal 10, and fl as the fundamental wave
- the size of IM3 is enlarged 50 times and displayed.
- the phase of IM3 with respect to the fundamental wave is reversed!
- FIG. 28 is a view showing another example for more specifically explaining the second embodiment of the present invention, in which an inductor 22 is used as the impedance element 21.
- the base-emitter of the bias supply transistor 11 is considered as the bias supply diode 4.
- Figure 29 shows the relationship between the fundamental and ⁇ 3 at an output power of 2 dBm.
- the size of IM3 is enlarged 50 times and displayed.
- the phase of IM3 with respect to the fundamental wave is reversed.
- the present invention is a technique for reducing distortion in a multistage amplifier and not necessarily a technique for reducing distortion in a single-stage amplifier.
- FIG. 30 is a diagram showing an amplifier for reversing the phase of IM 3 with respect to the fundamental wave according to a third embodiment of the present invention.
- the amplification transistor 1 forms an emitter-grounded amplification circuit, and the base of the transistor 1 is biased by a bias supply diode 23. Similarly, the base of the transistor 1 is connected to the input matching circuit 3 and the bias supply diode 24 via the impedance element 25.
- the anodes of the bias supply diodes 23 and 24 are connected to the reference power supply 5.
- the collector of the transistor 1 is connected to a collector power supply 7 via a load 6 and connected to an output terminal 9 via an output matching circuit 8.
- This embodiment is the same as the fourth to sixth embodiments described later in the effects and operations, and therefore will be collectively described in the sixth embodiment.
- FIG. 31 is a diagram showing an amplifier for reversing the phase of IM 3 with respect to a fundamental wave according to a fourth embodiment of the present invention.
- the base-emitter of the bipolar transistor 26 is used in place of the diode 24 of the third embodiment. Therefore, the effects and operations are the same as those of the third embodiment and the fifth to sixth embodiments described later, and therefore, the sixth embodiment will be collectively described.
- FIG. 32 is a diagram showing an amplifier for reversing the phase of IM 3 with respect to the fundamental wave according to a fifth embodiment of the present invention.
- the base-emitter of the bipolar transistor 27 is used as the diode 23 of the third embodiment. Therefore, the effects and operations are the same as those of the third embodiment, the fourth embodiment, and the sixth embodiment described later, and therefore, the sixth embodiment will be collectively described. Do.
- FIG. 33 is a diagram showing an amplifier for reversing the phase of IM 3 with respect to the fundamental wave according to a sixth embodiment of the present invention.
- the base 'emitters of the bias supply transistors 26 and 27 are used as the diodes 23 and 24 in the third embodiment. Therefore, the effects and operations are the same as in the third to fifth embodiments.
- the reason why the phase of IM 3 with respect to the fundamental wave is reversed in the operations of the third to sixth embodiments is substantially the same as in the first to second embodiments.
- the present embodiment is the same as the third to fifth embodiments in effect and operation, and therefore, the sixth embodiment will be collectively described as an example.
- FIG. 34 is a view for explaining the sixth embodiment of the present invention.
- a series circuit of resistors 30 and 31 is connected in parallel with a capacitor 32 as an impedance element 25 in FIG.
- a reference power supply 5 a reference power supply 36 having the same configuration as that of the third conventional amplifier shown in FIG. 6 was used.
- a GaAs heterojunction bipolar transistor As a transistor model for analysis, a GaAs heterojunction bipolar transistor (HBT) is used, and as amplification transistor 1, an array of five 120 ⁇ m 2 unitary elements is used, and an impedance element is used.
- the 25 resistors 30 also served as the transistor ballast resistors and made five 250 ⁇ resistors in parallel, and the 31 resistor used the lk Q resistor.
- the capacitance 32 of the impedance element 25 is configured by five parallel 0.8 pF capacitors.
- An HBT with an emitter area of 120 / zm 2 was used as the noise supply transistor 27.
- an HBT with an emitter area of 30 m 2 was used as the bias supply transistor 26.
- the transistors 15 and 16 of the reference power supply 36 used one with an emitter area of 30 m 2 .
- the size of IM3 is enlarged 50 times and displayed.
- the phase of IM3 with respect to the fundamental wave is reversed!
- FIG. 36 shows the relationship between the instantaneous value of the emitter potential of the transistor 26 and the current supplied from the emitter of the transistor 26 as well.
- This figure is a load line representing the internal impedance of transistor 26.
- the two lines shown in the figure represent load lines near the maximum amplitude (the moment when the two frequencies just add) when two frequencies are input and the output is 10 dBm and -3 dB m.
- the base voltage when large amplitude is entered compared to when small amplitude. It can be seen that the output impedance of the transistor 26 when the power goes down is extremely small.
- the advantages of the third to sixth embodiments are as follows.
- a circuit having a real part of impedance such as a parallel circuit of a resistor and a capacitor is used as an impedance element, and when the input matching is performed, energy is consumed by the real part of the impedance. Loss will occur.
- the resistor supplies the bias current to the amplification transistor 1, the resistance can not be increased indiscriminately.
- the bias current supply to the amplification transistor 1 can be performed by the bias supply transistor 27, the value of the resistor 31 can be increased to prevent high frequency from passing through the resistor side.
- FIGS. 37 and 38 illustrate a multistage amplifier according to a seventh embodiment of the present invention.
- Fig. 38 [Fig. 38, 80, 82, 84 matching circuits, 81, 83 amplification stages are shown.
- FIG. 38 in a multistage amplifier having two or more amplification stages having gain expansion characteristics in which the gain increases with an increase in input power or output power in a certain range of input power or output power. Stages other than the stage are designed to have an amplitude compressor mechanism at high frequency at the input.
- the reason for not using an amplification stage having an amplitude compression mechanism at the final stage is that the size of the amplification transistor at the final stage is usually the largest among all the amplification transistors, so the input impedance is low and This is because it is difficult to control so that the phases of become opposite.
- FIGS. 39, 40 and 41 are diagrams for explaining the present embodiment.
- an amplification stage having the same configuration (FIG. 25) as that of the first embodiment is used as an amplification stage having an amplitude compression mechanism at high frequency at its input.
- the first stage amplification transistor 61 has three emitters with an area of 180 ⁇ m 2 in parallel, and the resistance 43 of the impedance element 62 also serves as a ballast resistance of the transistor 61 and three 250 ⁇ resistors. Parallel and imp
- the capacitance 44 of the dance element 62 is configured by three parallel ones of 0.8 pF. An emitter area of 60 ⁇ m 2 was used as the bias supply transistor 42.
- the final stage amplification transistor 71 used is a parallel arrangement of 24 units of emitter area of 180 ⁇ m 2 , and the resistance 53 of the impedance element 72 is 250 ⁇ in combination with the transistor ballast resistance. Twenty-four resistors were arranged in parallel, and a capacitor 54 of the impedance element 72 was constructed by arranging twenty-four capacitors of 0.8 pF in parallel. Two HBTs with an emitter area of 120 / zm 2 were used in parallel as the negative supply transistor 52. HBTs with an emitter area of 30 m 2 were used for the reference power supply 35 and 46 transistors. As the capacitance 39 in the reference power supply 35, a capacitance of 3 pF was used. As the loads 66 and 76, transmission lines having a length of 1Z4 with respect to the fundamental wave were used, and for the collector power supplies 67 and 77 and the noise power supplies 36 and 56, 3.5V constant voltage sources were used.
- Reference power supply 35 such that the collector current of amplification transistor 61 when there is no input signal from input terminal 60 is 5 mA, and the collector current of amplification transistor 71 when there is no input signal from input terminal 55 is also 15 mA.
- Figure 41 shows the change in gain and ACPR with respect to the output power when 46 parameters and control power supplies 45 and 49 are set, and a W-CDMA signal is input and measured. For comparison, FIG. 41 also shows the change in gain and ACPR with respect to the output power when measuring only the final stage amplifier shown in FIG.
- ACPR measured with the first stage + final stage multistage amplifier is lower than ACPR when measuring the final stage amplifier in the range of output power lOdBm to 25dBm. That is, distortions of the first stage and the last stage cancel out in this power range. Comparing the gains of only the final stage with the gains of the first and last stages, the gain difference is expanded in the range of output power lOdBm to 25dBm, so that the first stage and the last stage have gain expansion in this power range I am strong.
- GaAs heterojunction bipolar transistor (HBT) excellent in high frequency characteristics is used as the transistor in the above, the same effect can be obtained by using other bipolar transistors such as SiGe-HBT and Si bipolar. Needless to say!
- a reference power supply of the bias circuit a reference power supply using a two-stage stacked diode or an avalanche diode, and other current sources using two-stage stacked diodes or avalanche diodes described in Patents 3377675 and 2002-9559.
- Use any circuit that acts as a reference power supply, such as a mirror circuit Needless to say, the same effect can be obtained.
- the reference power supply is grounded with a capacitance of 2 pF so that the impedance is sufficiently low in high frequency, but different capacitance values may be provided or the high frequency impedance may be lowered by using an element other than capacitance (for example, active capacitor). If you do, you can get the same effect.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
Claims
Priority Applications (3)
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US10/585,206 US7768345B2 (en) | 2004-01-05 | 2004-12-27 | Amplifier |
CN2004800422421A CN1926759B (zh) | 2004-01-05 | 2004-12-27 | 放大器 |
JP2005516849A JP4752509B2 (ja) | 2004-01-05 | 2004-12-27 | 増幅器 |
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JP2004-000672 | 2004-01-05 | ||
JP2004000672 | 2004-01-05 |
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PCT/JP2004/019526 WO2005067139A1 (ja) | 2004-01-05 | 2004-12-27 | 増幅器 |
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US (1) | US7768345B2 (ja) |
JP (1) | JP4752509B2 (ja) |
CN (1) | CN1926759B (ja) |
WO (1) | WO2005067139A1 (ja) |
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Also Published As
Publication number | Publication date |
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CN1926759B (zh) | 2010-04-28 |
JP4752509B2 (ja) | 2011-08-17 |
JPWO2005067139A1 (ja) | 2008-04-17 |
US7768345B2 (en) | 2010-08-03 |
CN1926759A (zh) | 2007-03-07 |
US20070164824A1 (en) | 2007-07-19 |
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