WO2005053010A1 - Plaquette recuite et methode de fabrication de cette plaquette recuite - Google Patents

Plaquette recuite et methode de fabrication de cette plaquette recuite Download PDF

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Publication number
WO2005053010A1
WO2005053010A1 PCT/JP2004/016394 JP2004016394W WO2005053010A1 WO 2005053010 A1 WO2005053010 A1 WO 2005053010A1 JP 2004016394 W JP2004016394 W JP 2004016394W WO 2005053010 A1 WO2005053010 A1 WO 2005053010A1
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Prior art keywords
wafer
temperature
silicon wafer
silicon
heat treatment
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PCT/JP2004/016394
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English (en)
Japanese (ja)
Inventor
Ryoji Hoshi
Hiroshi Takeno
Izumi Fusegawa
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Shin-Etsu Handotai Co., Ltd.
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Publication of WO2005053010A1 publication Critical patent/WO2005053010A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment

Definitions

  • Anneal eha and method for producing annea eha are identical to Anneal eha and method for producing annea eha
  • the present invention relates to an anneal wafer having both an ea wafer surface layer having excellent oxide film breakdown voltage characteristics and an evaha balta part having excellent gettering ability, and a method of manufacturing the anneal wafer.
  • CZ method silicon substrates manufactured by using the Czochralski method (hereinafter abbreviated as CZ method) serving as a substrate thereof are used.
  • Quality requirements for C are increasing.
  • FPD LSTD
  • COP COP
  • V Volancy, hereinafter abbreviated as V
  • I interstitial silicon
  • the V region is a region having many vacancies, that is, recesses and holes generated due to lack of silicon atoms, and the I region has extra silicon atoms.
  • This is a region with many dislocations and extra silicon lump generated due to the occurrence of atoms, and there is no lack or excess of atoms between V region and I region !, (less! /,) Neutral ( Neutral (hereinafter sometimes abbreviated as N).
  • the above-mentioned green-in defects (FPD, LSTD, COP, etc.) are generated only when V and I are supersaturated. However, it has been found that it does not exist as a green-in defect.
  • OSF Oxidation Induced Stacking Fault
  • LZD Large Dislocation: an abbreviation for interstitial dislocation loop, LSEPD, LFPD, etc.
  • LSEPD interstitial dislocation loop
  • LFPD LFPD
  • N region there is a region called the N region, as described above, in which neither FPD, LSTD, or COP caused by vacancies nor LSEPD or LFPD caused by a dislocation loop exists. ing.
  • This N region is outside the OSF ring, and when oxygen precipitation heat treatment is performed and the contrast of the precipitation is confirmed by X-ray observation, etc., almost no oxygen precipitation occurs and L SEPD and LFPD are formed. It is reported that the region is not as rich as the I region. Furthermore, in recent years, the existence of an N region inside the OSF ring has been confirmed without defects caused by vacancies or defects caused by dislocation loops.
  • the pulling speed in the crystal radial direction plane Since the degree should be constant, in a general single crystal growth, G has a distribution in the plane.For example, at a certain pulling speed, the center becomes V region and the N region becomes Only a single crystal that could be the I region was obtained.
  • Nv region a region with many vacancies
  • Ni region a region with a large amount of interstitial silicon
  • SEPD Secco Etch Pit Defect
  • LSTD Laser Scattering Tomography Defect
  • COP Crystal Originated Particle
  • the diameter of this pit is less than 1 ⁇ m and is examined by the light scattering method.
  • L / D Large Dislocation: abbreviation for interstitial dislocation loop
  • LSEPD is a large SEPD of 10 m or more as described above.
  • the LFPD is one of the above-mentioned FPDs having a tip pit size of 10 ⁇ m or more.
  • the silicon single crystal grown by the CZ method contains interstitial oxygen as an impurity at a concentration of about 10 18 atoms / cm 3 .
  • the interstitial oxygen is used in a heat history (hereinafter, may be abbreviated as a crystal heat history) from solidification in a crystal growth process to cooling to room temperature, or a heat treatment process in a semiconductor device manufacturing process.
  • a precipitate of silicon oxide hereinafter sometimes referred to as an oxygen precipitate, BMD (Bulk Micro Defects), or simply a precipitate
  • the oxygen precipitate effectively functions as a gettering site for capturing heavy metal impurities mixed in the device process (Internal Gettering: IG), and can improve device characteristics and yield.
  • IG Internal Gettering
  • the wafer is not only subject to the heat history in the device process, but also the crystal heat. Received history. Therefore, oxygen precipitate nuclei (grain-in precipitate nuclei) formed by the heat history of the crystal already exist in the as-grown crystals, and the presence of the grow-in precipitate nuclei makes it more difficult to control the oxygen precipitates. ing.
  • the process of oxygen precipitation consists of the formation of a precipitate nucleus and its growth process.
  • nucleation proceeds in the heat history of crystallization, grows larger due to the heat history of the subsequent device process and the like, and is detected as an oxygen precipitate. Therefore, the oxygen precipitates present in the wafer at the stage prior to the injection of the device process have extremely small IG capability. However, through the device process, the oxygen precipitate grows greatly and has IG capability.
  • oxygen precipitates of a detectable size having high IG capability be formed at a high density in a stage before the device process is introduced, for a device process at a low temperature and a short time.
  • oxygen precipitates exist in the device fabrication region near the wafer surface, the device characteristics are degraded. Therefore, it is desirable that oxygen precipitates do not exist near the wafer surface.
  • the single crystal when a single crystal is grown by the CZ method, the single crystal may be grown in a V region where the pulling speed can be increased for reasons such as improvement in productivity.
  • voids such as COPs formed by the aggregation of atomic vacancies (vacancies)
  • vacancies There are (hole) type defects. It is known that the presence of such a void type defect such as COP in the device fabrication region deteriorates the device characteristics, particularly the breakdown voltage characteristics of the oxide film, which is an important characteristic. Therefore, the device fabrication area It is desirable that void-type defects do not exist in the surface layer of the wafer (usually, the area of the wafer surface force of about several meters) as well as oxygen precipitates.
  • the wafer is subjected to a high-temperature heat treatment at about 1200 ° C. in an inert atmosphere such as hydrogen or argon. Is being done. Furthermore, in order to eliminate void-type defects such as COP existing in the surface layer of the wafer and to form oxygen precipitates inside the wafer (balta), for example, a method of adding nitrogen during crystal growth has been proposed.
  • a high-temperature heat treatment at about 1200 ° C. in an inert atmosphere such as hydrogen or argon.
  • a method of adding nitrogen during crystal growth has been proposed.
  • an object of the present invention is to provide The oxide surface of the wafer surface area, which is a vice manufacturing area, has excellent withstand voltage characteristics, and the density of oxygen precipitates in the wafer balta section is uniform and high in the plane before the device process is introduced.
  • An object of the present invention is to provide an annealed wafer having excellent IG capability and a method of manufacturing the annealed wafer.
  • an annealed wafer obtained by subjecting a silicon wafer produced from a silicon single crystal grown by the Czochralski method to a heat treatment, wherein the entire surface of the wafer has a grown-in defect.
  • the non-defective rate of the oxide film breakdown voltage characteristic is 95% or more in the region where the surface tension of the wafer is at least 5 ⁇ m, and the density of the oxygen precipitate inside the wafer is less than 95%.
  • Aniruueha is provided, wherein a value of the ratio between the maximum value and the minimum value of the density of oxygen precipitates in Ueha plane (maximum value Z minimum value) is 1 one 10 Is done.
  • the annealed wafer of the present invention has an N region on the entire surface of the wafer, a non-defective rate of oxide film breakdown voltage characteristics of 95% or more, and an oxygen precipitate density of 1 ⁇ 10 9 Zcm inside the wafer (balta portion). Since the value of (maximum value Z minimum value) of the oxygen precipitate density in the wafer surface is 1 to 10 when it is 3 or more, the oxide film breakdown voltage characteristics of the wafer surface layer, which is the device fabrication area, are very low. It is excellent, and the density of oxygen precipitates is uniform and high density in the plane at the stage before the device process is injected into the Ehbar balta part.
  • the present invention also relates to an annealed wafer obtained by subjecting a silicon wafer produced from a silicon single crystal grown by the Czochralski method to a heat treatment, wherein the entire surface of the silicon wafer has neither a grown-in defect nor an OSF. !, An anneal wafer characterized by having a large number of vacancies in the Nv region and heat-treating the silicon wafer.
  • the entire surface of the wafer has neither a grown-in defect nor OSF! If the silicon wafer in the Nv region with many vacancies is subjected to a heat treatment, not only the surface of the wafer but also the surface of the wafer, for example, The region from to 5 ⁇ m is the defect-free layer (DZ layer), which makes it possible to make the wafer excellent in the breakdown voltage characteristics of the oxide film on the surface layer of the wafer.
  • the object has a high density of, for example, 1 X 10 9 Zcm 3 or more. Since it is formed uniformly inside, it is possible to obtain a wafer having excellent IG capability.
  • the diameter of the annealing wafer can be 200 mm or more.
  • the anneal wafer of the present invention has oxygen precipitates formed at high density and in-plane uniformly as described above, and the oxygen precipitates have, for example, slip dislocation due to thermal stress when the wafer is heat-treated. It is known to have the effect of suppressing the occurrence. Therefore, as long as the anneal ⁇ eno of the present invention has a diameter of 200 mm or more in which slip dislocation is easily generated by heat treatment, for example, a large diameter wafer that can suppress the occurrence of slip dislocation due to thermal stress during a device process is used. It will be a very effective wafer especially for wafers of 300mm or more, which will become mainstream in the future.
  • a silicon wafer having an Nv region with many vacancies in which the entire surface of the wafer does not have a green-in defect or OSF was prepared, and then the prepared silicon wafer was heated at a temperature of 500 ° C or more to 700 ° C or more. Temperature T below ° C
  • a silicon wafer having a large number of atomic vacancies and an Nv region is produced, and the silicon wafer is held at a temperature of 500 ° C or more and 700 ° C or less for a predetermined time.
  • the grown-in precipitate nuclei in C become difficult to grow and disappear, and new oxygen precipitate nuclei can be generated on the wafer.
  • at a temperature rise rate of 5 ° CZ or less 1000 ° C or more and 1 230 ° C
  • high-density glowin precipitate nuclei and oxygen precipitate nuclei existing in the ewa can be efficiently grown without extinction, and then maintained at that temperature for a predetermined period of time.
  • the silicon wafer is kept at a temperature T ° C of 500 ° C. or more and 700 ° C. or less.
  • the time t is 15 minutes or more.
  • the time t for holding the silicon wafer at a temperature of 500 ° C or more and 700 ° C or less is set as follows.
  • the interval t be 30 minutes or more.
  • oxygen precipitates can be grown stably to a size having gettering ability, and a DZ layer can be formed with a sufficient width near the wafer surface.
  • a silicon wafer having an Nv region with many vacancies in which the entire surface of the wafer has neither a glow-in defect nor an OSF was manufactured, and then the manufactured silicon wafer was heated at a temperature of at least T ° C. T ° C
  • a heating step A in which the temperature is raised at a heating rate of R ° CZ at 22 ° C, and the temperature T ° C to T ° C
  • a heat treatment including a temperature raising step B for raising the temperature at a rate of 2 ° CZ and a holding step C for holding the temperature T ° C. for a predetermined time t is performed.
  • a method for producing an annealed wafer is provided.
  • a silicon wafer having a large number of vacancies and an Nv region is produced, and the silicon wafer is subjected to a temperature raising step so that the grown-in precipitation nuclei in the wafer are reduced as much as possible.
  • Oxygen precipitates near the wafer surface can be grown without being extinguished, and then heated to a high temperature in a short time by performing a heating process with a heating rate different from that of the heating process.
  • the fine oxygen precipitates grown in the heating step A and the heating step B can be further grown to a size having IG capability in the evaporator section. In the vicinity of the wafer surface, oxygen precipitates disappear and a DZ layer can be formed.
  • the oxide film withstand voltage characteristics of the surface layer of the wafer, which is the device fabrication area, are extremely excellent, and oxygen precipitates are uniformly present at a high density in the wafer, at the stage before the device process is introduced. Annealed wafers having excellent IG capability can be easily manufactured.
  • the temperature raising step A, the temperature raising step B, and the holding step C are performed successively.
  • the process time of the entire heat treatment process can be shortened, and the efficiency of the heat treatment process and the productivity can be improved. Can be planned.
  • the temperature T is set to 700 ° C. or less and the temperature T is set to 800
  • the heating rate R is not more than 3 ° CZ and not more than 1000 ° C.
  • the temperature T may be maintained at the temperature T for 30 minutes or more before performing the temperature raising step A.
  • the silicon wafer is held at the temperature T for 30 minutes or more.
  • the growth nuclei of the grown-in nuclei can be made more difficult to be eliminated.
  • new oxygen nuclei can be effectively generated, and a higher-density oxygen nuclei can be formed on the silicon wafer. Can be formed.
  • the temperature T is set to 800 ° C. or more and 1000 ° C. or less
  • the temperature T should be 1050 ° C or more and 1230 ° C or less, and the heating rate R should be 5 ° CZ minutes or more.
  • the temperature T is set to 1050 ° C or more and 1230 ° C or less
  • the holding time t is 30 minutes or more.
  • the oxygen precipitates in the ehabalta part grown in the heating steps A and B can be grown stably, and at the same time, the oxygen precipitates in the vicinity of the ewa surface A DZ layer free of oxygen precipitates can be formed stably with a sufficient width.
  • a silicon wafer produced from a silicon single crystal grown without adding nitrogen as the silicon wafer to be subjected to the heat treatment it is preferable to use a silicon wafer produced from a silicon single crystal grown without adding nitrogen as the silicon wafer to be subjected to the heat treatment.
  • a thermally stable grown-in precipitation nucleus for example, Since there is no precipitation nucleus with a diameter of 40 nm or more, the force near the surface of the evaporator during thermal treatment can easily eliminate the grown-in precipitation nuclei and form a DZ layer. In addition, since it is not necessary to add nitrogen when growing a silicon single crystal, there is an advantage that the crystal growing process is not complicated and work and management are easy.
  • the oxygen concentration of the silicon wafer subjected to the heat treatment be 14 ppma or more.
  • the heat treatment can form a higher density of oxygen precipitates in the ember barta portion, and the IG capability which is superior to the anneal wafer Can be added.
  • the growth rate of oxygen precipitates is increased, so that the overall process time can be reduced.
  • the diameter of the annealed wafer to be manufactured is 200 mm or more. be able to.
  • the method for producing annealed wafers of the present invention can be particularly suitably applied to the case of producing large-diameter annealed wafers having a diameter of 200 mm or more, in which slip dislocations are easily generated by heat treatment in the past. That is, according to the present invention, oxygen precipitates having a large size can be uniformly formed at a high density in the wafer surface as described above, so that the slip dislocation generated during the heat treatment is more likely to be pinned and the slip dislocation is increased. Can be suppressed. Therefore, it is possible to stably produce a large-diameter annealed wafer having no slip dislocation.
  • heat treatment is performed under predetermined conditions on a silicon wafer that has many atomic vacancies and an Nv region in which the entire surface of the wafer has neither a grown-in defect nor an OSF.
  • the oxide film withstand voltage characteristic of the surface layer of the wafer, which is the device fabrication area, is extremely excellent, and the oxygen precipitates are uniformly distributed in the plane before the device process is injected into the wafer barrier part.
  • the present invention can provide an annealed wafer having excellent IG capability.
  • FIG. 1 is a flowchart showing an example of a method for producing an annealing machine according to a first embodiment of the present invention.
  • FIG. 2 is a schematic view schematically showing a pattern of a heat treatment applied to a silicon wafer in the first embodiment of the present invention.
  • FIG. 3 is a flowchart showing an example of a method for producing an annealing device according to a second embodiment of the present invention.
  • FIG. 4 is a schematic view schematically showing a pattern of a heat treatment applied to a silicon wafer in a second embodiment of the present invention.
  • FIG. 5 is a schematic configuration diagram showing an example of a single crystal pulling apparatus that can be used in the method for producing annealed wafers of the present invention.
  • FIG. 6 is a graph showing temperature distributions of the single crystal pulling apparatus used in the example and the single crystal pulling apparatus used in the comparative example.
  • FIG. 7 is a diagram showing a result of identifying a crystal defect region and a result of obtaining an initial oxygen concentration and an amount of precipitated oxygen with respect to a vertically divided sample of an example.
  • FIG. 8 is a view showing a result of identifying a crystal defect region in a vertically divided sample of a comparative example.
  • FIG. 9 is a graph showing density values and in-plane distributions of oxygen precipitates (BMD) in annealed wafers manufactured in Examples and Comparative Examples.
  • the inventors of the present invention have reported that the ⁇ wafer surface layer has a very excellent oxygen-withstand voltage characteristic, and the ⁇ ⁇ wafer, in which oxygen precipitates are uniformly and densely present in the plane before the device process is introduced, in the ⁇ ⁇ balta section.
  • intensive experiments and studies were repeated.
  • the oxygen precipitation amount i.e., the initial oxygen concentration before the oxygen precipitation heat treatment and the oxygen Silicon wafers with a difference from oxygen concentration
  • Ippma CiEIDA Jopan Electronic Industry Development Association standard
  • the grown-in precipitate nuclei could be grown in the ⁇ eno and Balta portions without disappearing, and oxygen precipitates could be formed stably.
  • a silicon wafer whose entire surface is an N region where neither a grown-in defect nor an OSF exists is used.
  • a DZ layer can be formed near the surface of the wafer, and oxygen precipitates can be formed on the Balta portion of the wafer.
  • the N region includes the Nv region and the Ni region as described above, and the Ni region is a region in which oxygen precipitation is less likely to occur than the Nv region.
  • the density of oxygen precipitates becomes non-uniform in the plane of the wafer, and as a result, the gettering ability of the wafer becomes non-uniform in the plane. It became clear that it becomes. Furthermore, in this case, the wafer may be warped due to the in-plane variation in the density of the oxygen precipitate. I also understood.
  • the present inventors have conducted further experiments and studies and found that, in the Nv region of silicon wafer, the amount of precipitated oxygen becomes lppma or more when the above oxygen precipitation heat treatment is performed. If annealed silicon wafers are manufactured by heat-treating silicon wafers in which the Nv region spreads over the entire surface of the wafer, the oxide film withstand pressure characteristics of the surface layer of the wafer are extremely excellent, and oxygen precipitates are formed on the wafer bar.
  • the present invention has been completed by conceiving that a high-quality annealed wafer can be obtained in which the particles exist uniformly at high density in the plane.
  • the annealing wafer of the present invention is an annealing wafer obtained by subjecting a silicon wafer produced from a silicon single crystal grown by the CZ method to a heat treatment, and the entire silicon wafer has both a grown-in defect and an OSF. It is characterized by having a large number of atomic vacancies and being in the Nv region, which is obtained by subjecting the silicon wafer to a heat treatment.
  • such an anneal wafer of the present invention is a non-defective product having excellent surface pressure characteristics of an oxidized film in an area where the entire surface of the wafer is free of a grown-in defect and an OSF, and the surface area of the wafer is at least up to a depth of 5 m.
  • Ratio is 95% or more, and the density of oxygen precipitates inside the eaves is 1 ⁇ 10 9 Zcm 3 or more, and the ratio (maximum value)
  • the characteristic value is that the value of (Z minimum value) is 1 to 10.
  • the yield rate is 95%. % Or more, and has excellent withstand voltage characteristics of the oxide film.
  • the oxide film compression characteristic in the present invention means a TZDB (Time Zero Dielectric Breakdown) characteristic
  • the non-defective rate is, for example, assuming that the determination current value is ImAZcm 2 and the dielectric breakdown electric field is 8 MVZcm or more. Show the ratio of
  • the density of Ueha internal (Butler portion) oxygen precipitate above size having an IG capability is detected Te odor as described above is 1 X 10 9 Zcm 3 or more, It has excellent IG capability at the stage before device process introduction, and even in recent years of low temperature and short-time device processes, the oxygen precipitates in the Aehbarta part are also used as gettering sites for the initial stage of the device process. It can function as an aera that can exhibit sufficient gettering ability without adding special heat treatment.
  • the density of oxygen precipitates is preferably set to 1 ⁇ 10 13 Zcm 3 or less in order to prevent deterioration due to excessive precipitation.
  • the size of the oxygen precipitate having IG capability is based on the size of the oxygen precipitate (for example, about 30 to 40 nm in diameter) which can be detected experimentally.
  • the size of the oxygen precipitate having the ability is preferably about 40 nm or more in diameter.
  • an oxygen precipitate having a size that cannot be detected experimentally has IG capability. It can be determined that it has sufficient IG capability.
  • Such oxygen precipitates can be detected, for example, by infrared scattering tomography, which is one of the light scattering methods.
  • the value of the ratio (maximum value Z minimum value) between the maximum value and the minimum value of the density of oxygen precipitates in the ⁇ a plane is 20 or more, or an order of magnitude higher!
  • the ratio of the maximum density to the minimum density (maximum value Z minimum value) of the oxygen precipitates in the wafer surface is 110, and more preferably 115. Therefore, the in-plane variation of the IG capability at the ehabalta section can be significantly reduced, and the ewa can have an extremely excellent gettering ability uniformly over the entire surface of the eha. In this case, the density of oxygen precipitates in the Problems such as warpage of the wafer, which have occurred due to the knock, can be easily solved.
  • oxygen precipitates having an effect of suppressing the occurrence of slip dislocation are uniformly formed on the surface of the wafer. Because of its high density and high density, it becomes a large-diameter wafer that suppresses the occurrence of slip dislocations in the device process, and becomes a very effective wafer especially in the future mainstream wafers of 300 mm or more.
  • the method for manufacturing an annealing wafer according to the first aspect of the present invention is a method for manufacturing a silicon wafer from a silicon single crystal grown by the CZ method and subjecting the manufactured silicon wafer to a heat treatment to manufacture an annealing wafer.
  • a silicon wafer having an Nv region with many vacancies in which the entire surface of the wafer has neither a grown-in defect nor an OSF is prepared.
  • FIG. 1 is a flow chart showing an example of a method for producing an annealing wafer according to the first embodiment of the present invention
  • FIG. 2 is a schematic drawing schematically showing a heat treatment pattern applied to a silicon wafer. It is.
  • a silicon wafer which is a raw material for annealed wafer, is produced from a silicon single crystal grown by the CZ method (Step 101 in FIG. 1). At this time, there is no grown-in defect or OSF on the entire surface of the silicon wafer to be manufactured. If there is a lot of atomic vacancies and Nv region, the manufacturing method is particularly limited. For example, as described in WO 01Z057293 pamphlet, WO 02,002852 pamphlet, and Japanese Patent Publication No. 2002-226296, the pulling speed when growing a single crystal The ratio between F and the temperature gradient G near the solid-liquid interface in the pulled crystal. A wafer can be manufactured using a method of pulling a crystal. Here, an example of a method for manufacturing a silicon wafer in the present invention will be specifically described.
  • FIG. 5 shows an example of a single crystal pulling apparatus for pulling a silicon single crystal.
  • the single crystal pulling apparatus 20 includes a crucible driving mechanism including a quartz crucible 5 containing a raw material melt 4 and a graphite crucible 6 protecting the quartz crucible 5 in a main chamber 1. (Not shown) rotatably and vertically supported by a holding shaft 19, and a heater 7 and a heat insulating material 8 are arranged so as to surround these crucibles 5 and 6.
  • a pulling chamber 2 for containing and removing the grown single crystal 3 is connected to the upper portion of the main chamber 1, and a single crystal 3 is pulled above the pulling chamber 2 while rotating the single crystal 3 with a wire 16 above the pulling chamber 2.
  • a lifting mechanism (not shown) is provided.
  • a gas rectifying cylinder 13 is provided inside the main chamber 1, and a heat shield member 14 is provided below the gas rectifying cylinder 13 so as to face the raw material melt 4.
  • the radiation from the surface of the melt 4 is cut, and the surface of the raw material melt 4 is kept warm.
  • the heat shield member 14 is installed such that the distance between the lower end thereof and the surface of the raw material melt 4 is about 2 to 20 cm, for example.
  • a cooling cylinder 11 is provided above the gas rectification cylinder 13 so that the single crystal 3 can be forcibly cooled by flowing a cooling medium from the refrigerant inlet 12.
  • an inert gas such as argon gas or the like can be introduced from a gas inlet 10 provided in the upper part of the pulling chamber 2, and passes between the single crystal 3 being pulled and the gas rectifying cylinder 13. After that, it can pass between the heat shield member 14 and the melt surface of the raw material melt 4 and be discharged from the gas outlet 9.
  • a magnet (not shown) can be provided outside the main chamber 1 in the horizontal direction, whereby a magnetic field such as a horizontal direction or a vertical direction is applied to the raw material melt 4 so that the raw material melt 4 is applied.
  • the so-called MCZ method which suppresses the convection of the crystal and stably grows the single crystal, can be used.
  • a silicon single crystal is grown by the CZ method using such a single crystal pulling apparatus 20, for example, first, a high-purity polycrystalline silicon material is melted in a quartz crucible 5 at a melting point (about 1420 ° C.). Heat and melt as above. Next, the wire 16 is unwound and the silicon melt 4 is unwound. The seed crystal 17 fixed to the seed holder 18 is brought into contact with or immersed in the approximate center of the surface of the substrate. After that, the crucible holding shaft 19 is rotated in an appropriate direction, and the wire 16 is wound while the wire 16 is not rotated and the seed crystal is pulled up to start growing the single crystal. Thereafter, by adjusting the pulling speed of the single crystal and the temperature of the silicon melt appropriately, a substantially cylindrical silicon single crystal 3 can be grown.
  • the pulling speed when growing the single crystal straight body portion was F [mmZmin], and the crystal temperature gradient in the pulling axis direction from the melting point of silicon to 1400 ° C was represented by G [° CZmm].
  • a silicon single crystal is grown by controlling the pulling speed F so that the value of FZG [mm 2 Z ° C ⁇ min] is in the Nv region.
  • the temperature gradient Gc at the center of the crystal and the temperature gradient Ge at the periphery of the crystal can be obtained.
  • the furnace temperature can be controlled so that the difference in crystallinity is small, and the temperature gradient around the crystal is lower than the crystal center, so that the entire surface in the crystal diameter direction can easily be in the Nv region. It becomes possible.
  • the cooling zone 11 installed above the gas flow straightening column 13 can rapidly cool the temperature zone (1080-1150 ° C) in which void defects are formed, thereby expanding the Nv region in the crystal growth axis direction. Therefore, it is possible to easily grow a single crystal in which the entire body is in the Nv region over the entire radial direction.
  • the silicon wafer obtained by slicing the silicon single crystal obtained as described above is a silicon wafer that has no atomic defects and no OSF and is an Nv region with many atomic vacancies. With such a silicon wafer, it is preferable to use a silicon wafer that does not have any grown-in defects or oxygen precipitates in the surface layer of the wafer when heat treatment is performed thereafter, and that a high oxygen deposition amount can be obtained in the wafer bar part. it can.
  • the silicon wafer is preferably manufactured from a silicon single crystal grown without adding nitrogen.
  • a silicon wafer fabricated from a silicon single crystal grown without adding nitrogen as described above there is no thermally stable grown-in precipitation nucleus, for example, a precipitation nucleus having a diameter of 40 nm or more in the wafer.
  • the force near the surface of the wafer can eliminate the grown-in precipitate nuclei and form the DZ layer stably.
  • the crystal growing process is not complicated, and the operation and management are simplified. Have.
  • the method for producing a silicon wafer from a silicon single crystal is not particularly limited. For example, after slicing a silicon wafer from a silicon single crystal, chamfering, lapping, By sequentially performing each process such as etching and mirror polishing, a silicon wafer can be easily manufactured.
  • the temperature is maintained at the temperature T ° C. for a predetermined time t (step 103 in FIG. 1). Like this
  • the holding temperature T is a temperature at which the grown-in precipitation nuclei can be grown.
  • the temperature T is 500 ° C or more. Is desirable. On the other hand, when the temperature T exceeds 700 ° C
  • the density of oxygen precipitates may not be sufficiently increased.
  • the time t for holding the silicon wafer at the temperature T is 15 minutes or more.
  • Holding time t is about 6
  • the time is set to 0 minutes or less. Incidentally, the silicon wafer is maintained at the temperature T as described above.
  • the temperature is not limited to being maintained at a constant temperature with high accuracy.
  • the temperature T may be 500 ° C or more and 700 ° C or less, and when maintaining the temperature,
  • the term “maintaining at a temperature T ° C for a predetermined time” in the present invention means that the temperature T 500-700 ° C This includes the case where it is varied and held.
  • FIG. 2 shows a silicon wafer held at a temperature T of 500 ° C. or more and 700 ° C. or less.
  • step 104 Warm up (step 104).
  • the temperature of the silicon wafer at a rate of 5 ° CZ or less, high-density grown-in precipitate nuclei existing in the wafer can be grown efficiently without disappearing as much as possible.
  • the lower the heating rate the higher the precipitate density. Therefore, by performing the temperature raising step in this manner, the grown-in precipitation nuclei formed when growing a single crystal can be effectively grown, so that, for example, oxygen precipitation nuclei are newly formed on the wafer.
  • the precipitate density can be sufficiently increased without separately performing a heat treatment step, and the entire process time can be reduced. At this time, the temperature T
  • the lower the temperature T the longer the holding time t at the temperature T.
  • Holding time t, and heating rate from temperature T to temperature T can be set as appropriate.
  • the silicon wafer is heated to a temperature T ° C of not less than 1000 ° C and not more than 1230 ° C.
  • step 12 After the temperature is raised in step 12, the temperature is maintained at the temperature T ° C for a predetermined time t (step 105). Like this
  • Oxygen precipitates in Aehbarta are further grown by holding at a temperature ⁇ for a predetermined time.
  • oxygen can be increased to a size having gettering ability, and at the same time, oxygen in the vicinity of the surface of the evaporator can be diffused outward to eliminate oxygen precipitate nuclei, thereby forming a DZ layer free of oxygen precipitates on the surface layer of the evaporator.
  • the higher the temperature T the more the oxygen precipitates have a desired size, that is, the gettering ability.
  • the time required to grow to a size having a short time and the power that can shorten the overall process time is preferably set to 1230 ° C or lower. Furthermore, during heat treatment,
  • the temperature T should be 1200 ° C or less.
  • the silicon wafer it is more preferable to keep the silicon wafer at a temperature of 1200 ° C or less, and even 1150 ° C or less, so that the oxygen precipitate in the wafer balta part grows.
  • a DZ layer can be formed on the surface of the wafer, which is particularly effective when heat-treating large-diameter wafers with a diameter of 200 mm or more, in which slip dislocations are likely to occur.
  • the time t maintained at this temperature T is determined by the growth-in precipitation nuclei in the Ehabarta part.
  • the heating time is 30 minutes or more in order to surely grow the DZ layer to a size having gettering ability, and to form a DZ layer having a sufficient width on the surface layer of the wafer.
  • the time t should be about 4 hours or less, or even about 2 hours or less, as this may reduce productivity.
  • the size of the oxygen precipitate to be grown is less than 100 nm.
  • the holding time t is shorter than 30 minutes.
  • step 105 the silicon wafer is heated
  • step 102-104 from the time of charging into the processing furnace until the temperature rises to the temperature T ° C
  • the purpose is to further grow oxygen precipitates in the grown barta and to form a DZ layer near the surface. Therefore, if the purpose can be achieved, it is not limited to maintaining the temperature at a constant temperature with high accuracy.
  • the oxygen formed on the anneal wafer is adjusted.
  • the size of the precipitate can be easily controlled.
  • the silicon wafer is taken out of the heat treatment furnace (step 107).
  • the temperature drop rate and the temperature at which the wafer is taken out after the temperature is lowered are not particularly limited. For example, it is preferable that slip dislocation due to thermal stress does not occur when the temperature of the wafer is dropped or when the wafer is taken out.
  • the heat treatment atmosphere when performing the above heat treatment is not particularly limited.
  • the heat treatment can be performed in an oxygen atmosphere, a mixed atmosphere of oxygen and nitrogen, an argon atmosphere, a hydrogen atmosphere, or the like.
  • a non-oxidizing atmosphere of argon or hydrogen since an oxide film is not formed on the surface of the evaporator, outward diffusion of oxygen is promoted as compared with the case of the oxidizing atmosphere, which may be more preferable.
  • the manufactured silicon wafer is subjected to a heat treatment under the above conditions, whereby the above-described anneal wafer of the present invention, that is, the silicon wafer is manufactured.
  • the entire surface is free of any grown-in defects or OSFs. ⁇
  • the area is ⁇ A surface area of the wafer.
  • the non-defective rate of the oxide film breakdown voltage characteristic is at least 95% in the area up to a depth of 5 ⁇ m.
  • a high quality value of the ratio between the maximum value and the minimum value of the density of oxygen precipitates in Ueha plane is 1 one 10 Aniruueha Can be easily and stably manufactured.
  • the oxygen concentration of the wafer being 14 ppma or more, it is possible to form oxygen precipitates at a higher density on the wafer barter part. With better IG capability for Anil @ eha can do.
  • the oxygen concentration of silicon wafer is increased to 14 ppma or more, the growth rate of oxygen precipitates is increased, so that the entire process time can be shortened.
  • the oxygen concentration of the silicon wafer subjected to the heat treatment is preferably 23 ppma or less, more preferably 17 ppma or less.
  • a method for producing an annealing wafer according to the second embodiment of the present invention will be described.
  • a silicon wafer is grown from a silicon single crystal grown by the CZ method.
  • the silicon wafer does not have any grown-in defects or OSF on the entire surface of the silicon wafer !, a large number of atomic vacancies, Nv
  • the manufactured silicon wafer is at least heated to a temperature T.
  • FIG. 3 is a flow chart showing a method for producing an annealing wafer according to the second embodiment of the present invention
  • FIG. 4 is a schematic drawing showing a pattern of a heat treatment applied to a silicon wafer.
  • a silicon wafer to be used as a raw material for annealed silicon is produced from a silicon single crystal grown by the CZ method (Step 201 in FIG. 3).
  • the silicon wafer can be manufactured using the same method as the method for manufacturing the silicon wafer in the first embodiment (step 101 in FIG. 1).
  • the produced silicon wafer is subjected to a heat treatment maintained at, for example, a temperature T ° C.
  • Heating process A is performed in which the temperature is raised at a rate of R ° CZ up to 21-22 (Step 203 in Fig. 3).
  • the density of oxygen precipitates can be increased by efficiently growing the grown-in precipitation nuclei formed in the crystal growth step without extinction as much as possible.
  • the temperature T is preferably set to 700 ° C or lower, since the concentration of oxygen precipitates in the annealed wafer after the heat treatment may not be sufficiently obtained because the precipitate nuclei easily disappear.
  • the temperature exceeds 1 21 22 1 ° CZ, the growth-in precipitation nuclei may not be sufficiently grown, and the growth-in precipitation nuclei may disappear in the subsequent process. It is preferable that the temperature be not more than ° CZ. Also, the lower the heating rate R, the lower the rate of growth of the grown-in precipitation nuclei without extinction, which is desirable.However, if the heating rate R is too low, the process time becomes longer and it is not efficient. Is preferably 0.5 ° CZ or more.
  • the temperature T after the heating is increased to 800
  • the rate of disappearance in the subsequent heating step B1 increases, and the density of oxygen precipitates may not be sufficiently obtained.
  • the temperature T the rate of disappearance in the subsequent heating step B1 increases, and the density of oxygen precipitates may not be sufficiently obtained.
  • the temperature of 22 exceeds 1000 ° C, the grown-in precipitation nuclei near the wafer surface also grow large, and the oxygen precipitates remain near the surface even after the subsequent heating step B and holding step C. DBecause a DZ layer cannot be formed on the surface of the wafer, the breakdown voltage characteristics of the oxide film may be reduced.
  • the silicon wafer is kept at the temperature T for 30 minutes or more.
  • the growth-in precipitation nuclei can be further eliminated, and new oxygen precipitation nuclei can be effectively generated in addition to the growth-in precipitation nuclei, so that a higher oxygen concentration can be obtained in the silicon wafer.
  • Precipitation nuclei can be formed. At this time, hold at temperature T
  • the time is too long, the process time becomes unnecessarily long. Therefore, it is preferable to set the time to about 4 hours or less.
  • the temperature is kept constant. Not only high accuracy is maintained, but also slight temperature change around temperature ⁇ depending on conditions.
  • Heating process B in which the temperature is raised at a rate of R ° CZ faster than that of temperature process A, is performed (step in Fig. 3).
  • the heating rate R2 in the heating step B1 should be 5 ° CZ min or more. preferable.
  • the heating rate R2 is too high, the oxygen precipitates in the ehabalta area may disappear in the holding step C, and it is considered that the oxygen precipitate density may decrease. Is desirably 10 ° CZ or less.
  • the temperature T after the heating is set to 1050 ° C or more and 1230 ° C or less.
  • oxygen near the surface can be diffused outward to eliminate oxygen precipitate nuclei near the surface.
  • T the higher the temperature T, the larger the oxygen precipitates in the balter section and the larger the DZ width.
  • the temperature T is preferably set to 1230 ° C or less. In addition, it occurs on wafers during heat treatment
  • the temperature T should be 1200 ° C or less, or 1150 ° C
  • the temperature is maintained at a temperature T ° C for a predetermined time t.
  • the holding process C is performed (step 205 in FIG. 3).
  • the fine oxygen precipitates grown in the temperature raising step and in the temperature raising step are grown to a size having an IG capability in the Aehark section, for example, a diameter of about 40 nm or more, and further, a diameter of about 5 Onm or more.
  • oxygen precipitates can be more completely eliminated near the wafer surface, an extremely high-quality DZ layer can be efficiently formed.
  • the retention time t is preferably set to 30 minutes or more, since oxygen precipitates and DZ widths of desired sizes may not be obtained due to the above. Also, as the holding time t becomes longer,
  • the retention time t be about 4 hours or less.
  • the temperature T and the temperature at which the silicon wafer is held at a high temperature are held at a high temperature.
  • the constant temperature T is used as in the method according to the first embodiment of the present invention.
  • the temperature T is more than 1050 ° C and 1230 ° C
  • the silicon wafer is taken out of the heat treatment furnace (Step 207).
  • the temperature drop rate and the temperature at which the wafer is taken out after the temperature is lowered are not particularly limited. For example, it is preferable to set conditions such that slip dislocation due to thermal stress does not occur when the temperature of the wafer is lowered or when the wafer is taken out. .
  • the heat treatment atmosphere when performing the heat treatment is also the first mode. There is no particular limitation as in the above.
  • the wafer is heated between the above-mentioned heating step A and the heating step B and between the heating step B and the holding step C.
  • the heating step A, the heating step B, and the holding step C are continuously performed. It is preferable to perform the heat treatment step, whereby the entire process time of the heat treatment step can be shortened, and the efficiency of the heat treatment step can be improved and the productivity can be improved.
  • the manufactured silicon wafer is subjected to a heat treatment including at least the temperature raising step A, the temperature raising step B, and the holding step C.
  • a heat treatment including at least the temperature raising step A, the temperature raising step B, and the holding step C.
  • the oxygen concentration of silicon wafer subjected to the heat treatment is preferably 23 ppma or less, particularly preferably 17 ppma or less.
  • the method for producing an anneal wafer according to the first and second aspects of the present invention is suitable for producing a large-diameter anneal wafer having a diameter of 200 mm or more, in which slip dislocations are easily generated by heat treatment. It can be particularly preferably used. That is, according to the present invention, as described above, large-size oxygen precipitates can be uniformly formed at high density in the wafer surface, so that the slip dislocation generated during the heat treatment is more likely to be pinned and the slip dislocation is reduced. Can be suppressed. Therefore, it is effective for large-diameter wafers in which slip dislocations are easily generated, and large-diameter annealed wafers in which slip dislocations are not generated. Ichino, in particular, will be able to produce stable, high-yield annealed wafers with a diameter of 200 mm or even 300 mm or more, which will become the mainstream in the future.
  • a 24-inch quartz crucible is charged with 150 kg of silicon polycrystal, and while applying a horizontal magnetic field of a central magnetic field strength of 4000 Gauss, a silicon single crystal having a diameter of 200 mm, an orientation of 100> and an oxygen concentration of about 15 ppma (j EIDA) is directly transferred. It was raised so that the length of its torso was about 130 cm.
  • the distance between the silicon melt surface and the heat-insulating member 14 was set to 60 mm so as to keep the crystal growth small, and a single crystal was grown by gradually lowering the crystal growth rate in the crystal growth axis direction.
  • FIG. 7 shows a graph showing the measured initial oxygen concentration and the amount of precipitated oxygen.
  • the silicon single crystal was pulled at a growth rate such that a single crystal only in the Nv region was obtained.
  • the initial oxygen concentration is 15 ppm as above.
  • the production conditions were adjusted to be a.
  • the silicon single crystal thus obtained was sampled at intervals of 2 Ocm in the growth axis direction, and the initial oxygen concentration was measured at in-plane intervals of 10 mm for the sampled wafer.
  • a heat treatment at 800 ° C. for 4 hours and a heat treatment for precipitation at 1000 ° C. for 16 hours were applied to the sample wafer to remove an oxide film caused by the heat treatment, and then the oxygen concentration was measured in the same manner as before the heat treatment.
  • the amount of precipitated oxygen which was obtained by subtracting the oxygen concentration after the precipitation heat treatment from the initial oxygen concentration force, exceeded lppma at all the measurement points in the plane for all of the sampled wafers. From this, it is considered that the silicon single crystal grown this time was able to be Nv region over the entire region of the single crystal straight body.
  • the wafer was subjected to a thermal oxidation treatment in a dry atmosphere to form a 25 nm gate oxide film, and 8 mm of the gate oxide film was formed thereon.
  • a phosphorus-doped polysilicon electrode having an electrode area of 2 was formed.
  • this A voltage was applied to the polysilicon electrode formed on the silicon oxide film, and the TZDB evaluation was performed with the judgment current value set to ImAZcm 2 and the dielectric breakdown electric field set to 8 MVZcm or more. As a result, it was found that the yield rate of the oxide film pressure resistance was 100%.
  • FIG. 6 shows the result of analyzing the temperature distribution of the single crystal pulling apparatus used in the above example and comparative example. As shown in FIG. 6, it can be confirmed that the single crystal pulling apparatus of the comparative example has a lower degree of rapid cooling as compared with the example having the cooling cylinder.
  • a vertically divided sample was prepared from the grown silicon single crystal, and a crystal defect region of the silicon single crystal was identified.
  • Fig. 8 shows the results. As shown in FIG. 8, it can be seen that it is almost impossible to grow a single crystal in which the defect-free region (N region) is very narrow and the entire surface is an Nv region as compared with the above example.
  • the silicon single crystal was pulled at a growth rate such that a single crystal having a defect-free region having both the Nv region and the Ni region was obtained.
  • the production conditions were adjusted so that the initial oxygen concentration was 15 ppma.
  • Sample silicon was cut out from the silicon single crystal thus obtained at intervals of 20 cm in the growth axis direction, and the amount of precipitated oxygen was determined in the same manner as in the above example.
  • a mirror-polished silicon wafer was produced from the silicon single crystal having the Nv region and the Ni region in the same manner as in the example, and was subjected to a heat treatment under the same conditions as in the example.
  • the density of oxygen precipitates (BMD) inside the wafers was measured by infrared scattering tomography at 10 mm intervals from the center of the wafers at 10 mm intervals, and the in-plane distribution was investigated. The results are shown in FIG.
  • the present invention is not limited to the above embodiment.
  • the above embodiment is a mere example, and any one having substantially the same configuration as the technical idea described in the claims of the present invention and having the same function and effect will be described. Are also included in the technical scope of the present invention.

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Abstract

L'invention concerne une plaquette recuite fabriquée en soumettant une plaquette en silicium fabriquée à partir d'un cristal de silicium unique formé par la méthode de Czochralski, à un traitement thermique. Cette plaquette recuite est caractérisée en ce que toute sa surface constitue une zone N ne présentant aucun défaut de croissance et aucun OSF, en ce que le taux de rendement de la tension de claquage de film d'oxyde caractéristique de cette zone, à une profondeur d'au moins 5 microns, à partir de la surface de la plaquette, est supérieur ou égal à 95 %, que la densité des précipités d'oxygène de la plaquette est supérieure ou égale à 1x109/cm3, et que le rapport de la valeur maximale par rapport à la valeur minimale (valeur maximale/valeur minimale) de la densité des précipités d'oxygène de la surface de la plaquette est compris entre 1 et 10. Par conséquent, la tension de claquage de film d'oxyde caractéristique de la partie de couche de surface de la plaquette, à savoir la zone de fabrication de dispositifs, est excellente, la densité des précipités d'oxygène est très régulière dans le plan de la partie de masse de la plaquette, à l'étape où la plaquette n'est pas encore arrivée dans le processus de dispositif, et la plaquette présente une excellente capacité IG. L'invention concerne une méthode pour fabriquer une telle plaquette recuite.
PCT/JP2004/016394 2003-11-26 2004-11-05 Plaquette recuite et methode de fabrication de cette plaquette recuite WO2005053010A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007083476A1 (fr) * 2006-01-17 2007-07-26 Shin-Etsu Handotai Co., Ltd. Procédé de fabrication de tranche de monocristal de silicium

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4380689B2 (ja) 2006-11-21 2009-12-09 信越半導体株式会社 縦型熱処理用ボートおよびそれを用いた半導体ウエーハの熱処理方法
JP5119677B2 (ja) * 2007-02-16 2013-01-16 株式会社Ｓｕｍｃｏ シリコンウェーハ及びその製造方法
JP5061663B2 (ja) 2007-03-12 2012-10-31 信越半導体株式会社 縦型熱処理用ボートおよび半導体ウエーハの熱処理方法
JP5227586B2 (ja) * 2007-12-28 2013-07-03 ジルトロニック アクチエンゲゼルシャフト アニールシリコンウエハの製造方法
JP5163459B2 (ja) * 2008-12-05 2013-03-13 株式会社Ｓｕｍｃｏ シリコン単結晶の育成方法及びシリコンウェーハの検査方法
JP5537802B2 (ja) * 2008-12-26 2014-07-02 ジルトロニック アクチエンゲゼルシャフト シリコンウエハの製造方法
JP5597378B2 (ja) * 2009-03-27 2014-10-01 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハの熱処理方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330316A (ja) * 1995-05-31 1996-12-13 Sumitomo Sitix Corp シリコン単結晶ウェーハおよびその製造方法
JP2000053497A (ja) * 1998-06-04 2000-02-22 Shin Etsu Handotai Co Ltd 窒素ド―プした低欠陥シリコン単結晶ウエ―ハおよびその製造方法
WO2001057293A1 (fr) * 2000-01-31 2001-08-09 Shin-Etsu Handotai Co., Ltd. Dispositif et procede de production de monocristal et monocristal
JP2001278692A (ja) * 2000-03-29 2001-10-10 Shin Etsu Handotai Co Ltd シリコンウエーハおよびシリコン単結晶の製造方法
WO2002002852A1 (fr) * 2000-06-30 2002-01-10 Shin-Etsu Handotai Co., Ltd. Plaquette en silicium monocristallin et procede de fabrication
JP2002226296A (ja) * 2001-01-31 2002-08-14 Shin Etsu Handotai Co Ltd シリコン単結晶の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330316A (ja) * 1995-05-31 1996-12-13 Sumitomo Sitix Corp シリコン単結晶ウェーハおよびその製造方法
JP2000053497A (ja) * 1998-06-04 2000-02-22 Shin Etsu Handotai Co Ltd 窒素ド―プした低欠陥シリコン単結晶ウエ―ハおよびその製造方法
WO2001057293A1 (fr) * 2000-01-31 2001-08-09 Shin-Etsu Handotai Co., Ltd. Dispositif et procede de production de monocristal et monocristal
JP2001278692A (ja) * 2000-03-29 2001-10-10 Shin Etsu Handotai Co Ltd シリコンウエーハおよびシリコン単結晶の製造方法
WO2002002852A1 (fr) * 2000-06-30 2002-01-10 Shin-Etsu Handotai Co., Ltd. Plaquette en silicium monocristallin et procede de fabrication
JP2002226296A (ja) * 2001-01-31 2002-08-14 Shin Etsu Handotai Co Ltd シリコン単結晶の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007083476A1 (fr) * 2006-01-17 2007-07-26 Shin-Etsu Handotai Co., Ltd. Procédé de fabrication de tranche de monocristal de silicium
JP2007191320A (ja) * 2006-01-17 2007-08-02 Shin Etsu Handotai Co Ltd シリコン単結晶ウエーハの製造方法
CN101360852B (zh) * 2006-01-17 2012-12-05 信越半导体股份有限公司 单晶硅晶片的制造方法

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