WO2005053010A1

WO2005053010A1 - Annealed wafer and annealed wafer manufacturing method

Info

Publication number: WO2005053010A1
Application number: PCT/JP2004/016394
Authority: WO
Inventors: Ryoji Hoshi; Hiroshi Takeno; Izumi Fusegawa
Original assignee: Shin-Etsu Handotai Co., Ltd.
Priority date: 2003-11-26
Filing date: 2004-11-05
Publication date: 2005-06-09
Also published as: JP2005159028A; JP4857517B2

Abstract

An annealed wafer manufactured by subjecting a silicon wafer fabricated from a silicon single crystal grown by the Czochralski method to a heat treatment. The annealed wafer is characterized in that the whole surface of the wafer is an N region where no grow-in defects and no OSFs are present, the yield rate in the oxide film breakdown voltage characteristic in the region to the depth of at least 5 μm from the wafer surface is 95% or more, the density of the oxygen precipitates in the wafer is 1×109/cm3 or more, and the ratio of the maximum value to the minimum value (maximum value/minimum value) of the density of the oxygen precipitates in the surface of the wafer is 1 to 10. Therefore, the oxide film breakdown voltage characteristic in the wafer surface layer portion, namely the device fabrication region, is excellent, the density of the oxygen precipitates is high uniformly in the plane in the wafer bulk portion at the stage before the wafer is put into a device process, and the wafer has an excellent IG capability. A method for manufacturing such an annealed wafer is also disclosed.

Description

Anneal eha and method for producing annea eha

Technical field

The present invention relates to an anneal wafer having both an ea wafer surface layer having excellent oxide film breakdown voltage characteristics and an evaha balta part having excellent gettering ability, and a method of manufacturing the anneal wafer. Background art

[0002] In recent years, as the miniaturization of elements accompanying the high integration of semiconductor circuits progresses, silicon substrates manufactured by using the Czochralski method (hereinafter abbreviated as CZ method) serving as a substrate thereof are used. Quality requirements for C are increasing. In particular, there is a single crystal growth-induced defect, such as FPD, LSTD, COP, etc., which deteriorates oxide film breakdown voltage characteristics and device characteristics called grown-in defects, and it is important to reduce the density and size of these defects. Being done.

[0003] In describing these defects, first, a pay-can incorporated into a silicon single crystal is used.

(Vacancy, hereinafter abbreviated as V), and an interstitial silicon type called interstitial silicon (hereinafter sometimes abbreviated as I). The factors that determine the concentration of each of the point defects to be incorporated are generally known.

[0004] In a silicon single crystal, the V region is a region having many vacancies, that is, recesses and holes generated due to lack of silicon atoms, and the I region has extra silicon atoms. This is a region with many dislocations and extra silicon lump generated due to the occurrence of atoms, and there is no lack or excess of atoms between V region and I region !, (less! /,) Neutral ( Neutral (hereinafter sometimes abbreviated as N). The above-mentioned green-in defects (FPD, LSTD, COP, etc.) are generated only when V and I are supersaturated. However, it has been found that it does not exist as a green-in defect.

[0005] The concentration of these two-point defects depends on the crystal pulling rate F (growth rate) in the CZ method. It is known that the relationship with the temperature gradient G near the solid-liquid interface in the crystal is also determined. In the N region between the V region and the I region, a defect (hereinafter, referred to as an OSF ring) called an OSF (Oxidation Induced Stacking Fault) is a cross section in a direction perpendicular to the crystal growth axis. It has been confirmed that they are distributed in a ring when viewed.

[0006] When these defects caused by crystal growth are classified, for example, when the growth rate is relatively high, such as about 0.6 mmZmin or more, FPD, LSTD, FPD, LSTD, This is a V region in which grown-in defects such as COP exist at high density throughout the crystal diameter direction.

[0007] Further, when the growth rate is about 0.6 mmZmin or less, the peripheral force of the crystal is generated in the OSF ring as the growth rate decreases, and it is considered that a dislocation loop is caused outside the ring. LZD (Large Dislocation: an abbreviation for interstitial dislocation loop, LSEPD, LFPD, etc.) is an I region (sometimes called an LZD region) where defects exist at low density. Furthermore, when the growth rate is set to a low speed of about 0.4 mmZmin or less, the OSF ring condenses at the center of the ハ and disappears, and the ゥ becomes the entire area of the ゥ.

[0008] Further, between the V region and the I region, there is a region called the N region, as described above, in which neither FPD, LSTD, or COP caused by vacancies nor LSEPD or LFPD caused by a dislocation loop exists. ing. This N region is outside the OSF ring, and when oxygen precipitation heat treatment is performed and the contrast of the precipitation is confirmed by X-ray observation, etc., almost no oxygen precipitation occurs and L SEPD and LFPD are formed. It is reported that the region is not as rich as the I region. Furthermore, in recent years, the existence of an N region inside the OSF ring has been confirmed without defects caused by vacancies or defects caused by dislocation loops.

[0009] These N regions exist obliquely with respect to the growth axis direction when a single crystal is grown at a reduced growth rate in a normal method, and therefore exist only partially in the wafer surface. Did not. For this N region, the Voronkov theory (VV Voronkov, Journal of Crystal Growth, vol. 59 (1982), pp. 625–643) is the ratio of the pulling rate F to the temperature gradient G near the crystal-solid interface. He claims that the parameter FZG determines the total density of point defects. Considering this, the pulling speed in the crystal radial direction plane Since the degree should be constant, in a general single crystal growth, G has a distribution in the plane.For example, at a certain pulling speed, the center becomes V region and the N region becomes Only a single crystal that could be the I region was obtained.

[0010] In recent years, by improving the distribution of G in the plane, for example, when pulling a single crystal while gradually lowering the pulling speed F, a force N region, which has conventionally only existed obliquely, has been reduced in diameter. As a result, it became possible to produce a single crystal in which the entire area in the radial direction was an N region at a certain pulling speed. In addition, by maintaining the pulling speed when the N region spreads over the entire surface in the radial direction and growing the single crystal, the crystal in the entire N region can be expanded in the length direction. In particular, taking into account that G changes as the crystal grows, the pulling speed is corrected and adjusted so that the FZG remains constant, so that the entire N region crystal is greatly expanded in the crystal growth direction. (For example, JP-A-8-330316).

[0011] Further, when the N region outside the OSF ring is further classified, an Nv region (a region with many vacancies) adjacent to the outside of the OSF ring and a Ni region (a region with a large amount of interstitial silicon) adjacent to the I region (For example, JP-A-2001-139396).

[0012] Here, the terms described above will be described.

1) With FPD (Flow Pattern Defect), a wafer is cut out from a silicon single crystal rod after growth, and the strained layer on the surface is removed by etching with a mixed solution of hydrofluoric acid and nitric acid. By etching the surface with a mixture of water (Secco etching)

2 2 7

Pits and ripples (Flow Pattern) occur. This flow pattern is referred to as FPD. The higher the FPD density in the wafer surface, the more the breakdown voltage of the oxide film increases (see Japanese Patent Application Laid-Open No. 4-192345).

[0013] 2) SEPD (Secco Etch Pit Defect) refers to those with a flow pattern when subjected to the same Secco etching as FPD, and those without the flow pattern are called SEPD. Among these, SEPD (LSEPD) is considered to be caused by dislocation clusters.If a dislocation cluster exists in the device, current leaks through the dislocation and the function as a PN junction Will not work.

[0014] 3) LSTD (Laser Scattering Tomography Defect) is the growth of silicon The wafer is cut out of the single crystal, and the strained layer on the surface is removed by etching with a mixed solution of hydrofluoric acid and nitric acid, and then the wafer is cleaved. By irradiating infrared light from the cleavage plane (or the wafer surface) and detecting light emitted from the wafer surface (or the cleavage plane), scattered light due to defects existing in the wafer can be detected. The scatterers observed here have already been reported by academic societies and are regarded as oxygen precipitates (Shinsuke Sada mitsu et al. Japanese Journal of Applied Pnysics Vol. 32 (1993), p. 3679). reference). Recent studies have also reported octahedral voids.

[0015] 4) COP (Crystal Originated Particle) is a defect that causes deterioration of the oxide film pressure of the wafer. The defect force that becomes FPD in Secco etch SC-1 cleaning (NH OH

Four

: H O: H 0 = 1: 1: 10 mixture cleaning) works as a selective etching solution, CO

2 2 2

Become P. The diameter of this pit is less than 1 μm and is examined by the light scattering method.

[0016] 5) L / D (Large Dislocation: abbreviation for interstitial dislocation loop) includes LSEPD, LF PD, etc., and is a defect considered to be caused by the dislocation loop. LSEPD is a large SEPD of 10 m or more as described above. The LFPD is one of the above-mentioned FPDs having a tip pit size of 10 μm or more.

On the other hand, the silicon single crystal grown by the CZ method contains interstitial oxygen as an impurity at a concentration of about 10 ¹⁸ atoms / cm ³ . The interstitial oxygen is used in a heat history (hereinafter, may be abbreviated as a crystal heat history) from solidification in a crystal growth process to cooling to room temperature, or a heat treatment process in a semiconductor device manufacturing process. As a result, a precipitate of silicon oxide (hereinafter sometimes referred to as an oxygen precipitate, BMD (Bulk Micro Defects), or simply a precipitate) is formed.

[0018] The oxygen precipitate effectively functions as a gettering site for capturing heavy metal impurities mixed in the device process (Internal Gettering: IG), and can improve device characteristics and yield. However, since oxygen precipitates are highly dependent on heat treatment conditions, it is extremely difficult to obtain appropriate oxygen precipitates in different device processes for each user.Control of oxygen precipitates is a very important issue. .

[0019] Furthermore, the wafer is not only subject to the heat history in the device process, but also the crystal heat. Received history. Therefore, oxygen precipitate nuclei (grain-in precipitate nuclei) formed by the heat history of the crystal already exist in the as-grown crystals, and the presence of the grow-in precipitate nuclei makes it more difficult to control the oxygen precipitates. ing.

[0020] The process of oxygen precipitation consists of the formation of a precipitate nucleus and its growth process. In the case of a normal azglow wafer, nucleation proceeds in the heat history of crystallization, grows larger due to the heat history of the subsequent device process and the like, and is detected as an oxygen precipitate. Therefore, the oxygen precipitates present in the wafer at the stage prior to the injection of the device process have extremely small IG capability. However, through the device process, the oxygen precipitate grows greatly and has IG capability.

[0021] However, in recent device processes, as the diameter of wafers used has been increased, the temperature has been reduced and the time has been shortened. For example, in a series of device processes, heat treatment is performed at a temperature of 1000 ° C or less. RTP (Rapid Thermal Processing), which only requires a heat treatment time of about several tens of seconds, has been frequently used. In such a device process, for example, the total thermal history of all heat treatments may only correspond to a heat treatment of about 1000 ° C for about 2 hours. I can't expect things to grow. Therefore, it is desirable that oxygen precipitates of a detectable size having high IG capability be formed at a high density in a stage before the device process is introduced, for a device process at a low temperature and a short time. On the other hand, if oxygen precipitates exist in the device fabrication region near the wafer surface, the device characteristics are degraded. Therefore, it is desirable that oxygen precipitates do not exist near the wafer surface.

In general, when a single crystal is grown by the CZ method, the single crystal may be grown in a V region where the pulling speed can be increased for reasons such as improvement in productivity. In this case, In addition to the above-described grown-in precipitation nuclei, voids such as COPs formed by the aggregation of atomic vacancies (vacancies), There are (hole) type defects. It is known that the presence of such a void type defect such as COP in the device fabrication region deteriorates the device characteristics, particularly the breakdown voltage characteristics of the oxide film, which is an important characteristic. Therefore, the device fabrication area It is desirable that void-type defects do not exist in the surface layer of the wafer (usually, the area of the wafer surface force of about several meters) as well as oxygen precipitates.

Therefore, in order to eliminate such void-type defects existing in the surface layer of the wafer, for example, the wafer is subjected to a high-temperature heat treatment at about 1200 ° C. in an inert atmosphere such as hydrogen or argon. Is being done. Furthermore, in order to eliminate void-type defects such as COP existing in the surface layer of the wafer and to form oxygen precipitates inside the wafer (balta), for example, a method of adding nitrogen during crystal growth has been proposed. (For example, Japanese Patent Publication No. 11-322490, Japanese Patent Application Laid-Open No. 11-322491, Japanese Patent Application Laid-Open No. 2000-211995).

[0024] As described above, by growing a single crystal by adding nitrogen and manufacturing a wafer from the single crystal, the size of the voids existing in the wafer becomes smaller. In addition, the growth nuclei formed in the single crystal due to the thermal history of the crystal grow larger, so even if high-temperature heat treatment is performed, the precipitate nuclei grow without forming an disappearance in the Ahabarta part and form oxygen precipitates. IG capability can be added to e-ha. Furthermore, recently, a method of making the in-plane distribution of the density of oxygen precipitates uniform has also been proposed (Japanese Patent Application Laid-Open No. 2002-57160).

[0025] However, even when a wafer to which nitrogen is added is manufactured, a heat treatment at a high temperature of about 1200 ° C is necessary to eliminate void-type defects in the surface layer of the wafer. There is a possibility that small void-type defects that cannot be detected even after heat treatment may remain. In addition, large-sized growth-in precipitation nuclei may remain on the wafer surface layer because they are thermally stable and are hardly extinguished. If such void-type defects, ie, grown-in precipitation nuclei, remain in the surface layer of the wafer, problems may occur such as deterioration of device characteristics when the device is manufactured thereafter.

Furthermore, when nitrogen is added during crystal growth as described above, there are problems that the crystal manufacturing process becomes complicated and that it takes time to control the nitrogen concentration.

Disclosure of the invention

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide The oxide surface of the wafer surface area, which is a vice manufacturing area, has excellent withstand voltage characteristics, and the density of oxygen precipitates in the wafer balta section is uniform and high in the plane before the device process is introduced. An object of the present invention is to provide an annealed wafer having excellent IG capability and a method of manufacturing the annealed wafer.

[0027] In order to achieve the above object, according to the present invention, there is provided an annealed wafer obtained by subjecting a silicon wafer produced from a silicon single crystal grown by the Czochralski method to a heat treatment, wherein the entire surface of the wafer has a grown-in defect. In the N region where OSF does not exist, the non-defective rate of the oxide film breakdown voltage characteristic is 95% or more in the region where the surface tension of the wafer is at least 5 μm, and the density of the oxygen precipitate inside the wafer is less than 95%. in IX 10 ⁹ ZCM ³ than on, Aniruueha is provided, wherein a value of the ratio between the maximum value and the minimum value of the density of oxygen precipitates in Ueha plane (maximum value Z minimum value) is 1 one 10 Is done.

The annealed wafer of the present invention has an N region on the entire surface of the wafer, a non-defective rate of oxide film breakdown voltage characteristics of 95% or more, and an oxygen precipitate density of 1 × 10 ⁹ Zcm inside the wafer (balta portion). ^{Since the} value of (maximum value Z minimum value) of the oxygen precipitate density in the wafer surface is 1 to 10 when it is ³ or more, the oxide film breakdown voltage characteristics of the wafer surface layer, which is the device fabrication area, are very low. It is excellent, and the density of oxygen precipitates is uniform and high density in the plane at the stage before the device process is injected into the Ehbar balta part.

[0029] The present invention also relates to an annealed wafer obtained by subjecting a silicon wafer produced from a silicon single crystal grown by the Czochralski method to a heat treatment, wherein the entire surface of the silicon wafer has neither a grown-in defect nor an OSF. !, An anneal wafer characterized by having a large number of vacancies in the Nv region and heat-treating the silicon wafer.

As described above, the entire surface of the wafer has neither a grown-in defect nor OSF! If the silicon wafer in the Nv region with many vacancies is subjected to a heat treatment, not only the surface of the wafer but also the surface of the wafer, for example, The region from to 5 μm is the defect-free layer (DZ layer), which makes it possible to make the wafer excellent in the breakdown voltage characteristics of the oxide film on the surface layer of the wafer. The object has a high density of, for example, 1 X 10 ⁹ Zcm ³ or more. Since it is formed uniformly inside, it is possible to obtain a wafer having excellent IG capability.

[0031] In this case, the diameter of the annealing wafer can be 200 mm or more.

The anneal wafer of the present invention has oxygen precipitates formed at high density and in-plane uniformly as described above, and the oxygen precipitates have, for example, slip dislocation due to thermal stress when the wafer is heat-treated. It is known to have the effect of suppressing the occurrence. Therefore, as long as the anneal 本 eno of the present invention has a diameter of 200 mm or more in which slip dislocation is easily generated by heat treatment, for example, a large diameter wafer that can suppress the occurrence of slip dislocation due to thermal stress during a device process is used. It will be a very effective wafer especially for wafers of 300mm or more, which will become mainstream in the future.

[0032] Further, according to the present invention, in the method for producing a silicon wafer by producing a silicon wafer from a silicon single crystal grown by the Czochralski method and subjecting the produced silicon wafer to a heat treatment, As a wafer, a silicon wafer having an Nv region with many vacancies in which the entire surface of the wafer does not have a green-in defect or OSF was prepared, and then the prepared silicon wafer was heated at a temperature of 500 ° C or more to 700 ° C or more. Temperature T below ° C

Hold at 11 ° C for a predetermined time t, then

11 Heat treatment at a temperature rise rate of 5 ° CZ or less to a temperature of 1000 ° C or more and 1230 ° C or less to a temperature τ12 ° C, and then hold at the temperature τ12 ° c for a predetermined time t

12

And a method for producing annealed wafers.

[0033] As described above, a silicon wafer having a large number of atomic vacancies and an Nv region is produced, and the silicon wafer is held at a temperature of 500 ° C or more and 700 ° C or less for a predetermined time. The grown-in precipitate nuclei in C become difficult to grow and disappear, and new oxygen precipitate nuclei can be generated on the wafer.Then, at a temperature rise rate of 5 ° CZ or less, 1000 ° C or more and 1 230 ° C By raising the temperature to the following temperature, high-density glowin precipitate nuclei and oxygen precipitate nuclei existing in the ewa can be efficiently grown without extinction, and then maintained at that temperature for a predetermined period of time. Growing green precipitate nuclei and oxygen precipitate nuclei into oxygen precipitates increases the density of the oxygen precipitates, and at the same time, diffuses oxygen near the surface of the wafer outward and grows glow-in precipitate nuclei and oxygen on the surface layer of the wafer. Eliminate precipitation nuclei It is possible to form a DZ layer free of oxygen precipitates and grown-in precipitation nuclei on the surface layer of e-wafer. As a result, the oxide film withstand voltage characteristics of the surface layer portion of the wafer, which is the device fabrication area, are extremely excellent, and the oxygen precipitates are uniformly present at high density in the plane before the device process is injected into the wafer barrier section. As a result, it is possible to easily manufacture an aniline wafer having excellent IG capability.

At this time, the silicon wafer is kept at a temperature T ° C of 500 ° C. or more and 700 ° C. or less.

11

Preferably, the time t is 15 minutes or more.

11

Thus, the time t for holding the silicon wafer at a temperature of 500 ° C or more and 700 ° C or less is set as follows.

11

By setting the time to 15 minutes or longer, it is possible to more effectively eliminate the grown-in precipitate nuclei, further effectively generate new oxygen precipitate nuclei in the wafer, and form oxygen precipitate nuclei with higher density it can.

Further, when the silicon wafer is held at a temperature T ° C. of 1000 ° C. or more and 1230 ° C. or less,

12

It is preferable that the interval t be 30 minutes or more.

12

Thus, the time to hold the silicon wafer at a temperature of 1000 ° C or more and 1230 ° C or less t

By setting 12 to 30 minutes or more, oxygen precipitates can be grown stably to a size having gettering ability, and a DZ layer can be formed with a sufficient width near the wafer surface.

Further, according to the present invention, in the method for producing a silicon wafer from a silicon single crystal grown by the Czochralski method and subjecting the produced silicon wafer to a heat treatment to produce an annealed wafer, As a silicon wafer, a silicon wafer having an Nv region with many vacancies in which the entire surface of the wafer has neither a glow-in defect nor an OSF was manufactured, and then the manufactured silicon wafer was heated at a temperature of at least T ° C. T ° C

21 A heating step A in which the temperature is raised at a heating rate of R ° CZ at 22 ° C, and the temperature T ° C to T ° C

1 1 22 23

R different from 1 heating rate

A heat treatment including a temperature raising step B for raising the temperature at a rate of 2 ° CZ and a holding step C for holding the temperature T ° C. for a predetermined time t is performed.

1 23 21 1

A method for producing an annealed wafer is provided.

As described above, a silicon wafer having a large number of vacancies and an Nv region is produced, and the silicon wafer is subjected to a temperature raising step so that the grown-in precipitation nuclei in the wafer are reduced as much as possible. Oxygen precipitates near the wafer surface can be grown without being extinguished, and then heated to a high temperature in a short time by performing a heating process with a heating rate different from that of the heating process. After that, by applying the holding step C, the fine oxygen precipitates grown in the heating step A and the heating step B can be further grown to a size having IG capability in the evaporator section. In the vicinity of the wafer surface, oxygen precipitates disappear and a DZ layer can be formed. As a result, the oxide film withstand voltage characteristics of the surface layer of the wafer, which is the device fabrication area, are extremely excellent, and oxygen precipitates are uniformly present at a high density in the wafer, at the stage before the device process is introduced. Annealed wafers having excellent IG capability can be easily manufactured.

At this time, it is preferable that the temperature raising step A, the temperature raising step B, and the holding step C are performed successively.

As described above, by continuously performing the temperature raising process A, the temperature raising process B, and the holding process C, the process time of the entire heat treatment process can be shortened, and the efficiency of the heat treatment process and the productivity can be improved. Can be planned.

In the temperature raising step A, the temperature T is set to 700 ° C. or less and the temperature T is set to 800

1 21 22

It is preferable that the heating rate R is not more than 3 ° CZ and not more than 1000 ° C.

By performing the temperature raising step A under such conditions, it is possible to grow the grown-in precipitation nuclei formed in the crystal growth step efficiently without extinction as much as possible and to increase the density of oxygen precipitates. This leads to a reduction in the processing time.

In this case, the temperature T may be maintained at the temperature T for 30 minutes or more before performing the temperature raising step A.

1 21

preferable.

Thus, before performing the heating step A, the silicon wafer is held at the temperature T for 30 minutes or more.

1 21

As a result, the growth nuclei of the grown-in nuclei can be made more difficult to be eliminated.In addition to the nuclei of the grown-in nuclei, new oxygen nuclei can be effectively generated, and a higher-density oxygen nuclei can be formed on the silicon wafer. Can be formed.

Further, in the temperature raising step B, the temperature T is set to 800 ° C. or more and 1000 ° C. or less,

1 22

The temperature T should be 1050 ° C or more and 1230 ° C or less, and the heating rate R should be 5 ° CZ minutes or more.

23 2

preferable. By performing the temperature raising step under such conditions, it is possible to raise the temperature to the holding temperature of the holding step in a short time, thereby suppressing the growth of oxygen precipitates in the vicinity of the wafer surface. C can make oxygen precipitates near the surface disappear easily.

[0042] In the holding step C, the temperature T is set to 1050 ° C or more and 1230 ° C or less,

one two Three

Preferably, the holding time t is 30 minutes or more.

twenty one

By performing the holding step C under these conditions, the oxygen precipitates in the ehabalta part grown in the heating steps A and B can be grown stably, and at the same time, the oxygen precipitates in the vicinity of the ewa surface A DZ layer free of oxygen precipitates can be formed stably with a sufficient width.

[0043] In the method for producing an annealing wafer of the present invention, it is preferable to use a silicon wafer produced from a silicon single crystal grown without adding nitrogen as the silicon wafer to be subjected to the heat treatment.

[0044] As described above, by using a silicon wafer fabricated from a silicon single crystal grown without adding nitrogen, a thermally stable grown-in precipitation nucleus, for example, Since there is no precipitation nucleus with a diameter of 40 nm or more, the force near the surface of the evaporator during thermal treatment can easily eliminate the grown-in precipitation nuclei and form a DZ layer. In addition, since it is not necessary to add nitrogen when growing a silicon single crystal, there is an advantage that the crystal growing process is not complicated and work and management are easy.

Further, it is preferable that the oxygen concentration of the silicon wafer subjected to the heat treatment be 14 ppma or more.

When the oxygen concentration of the silicon wafer subjected to the heat treatment is 14 ppma or more, the heat treatment can form a higher density of oxygen precipitates in the ember barta portion, and the IG capability which is superior to the anneal wafer Can be added. In addition, by increasing the oxygen concentration of silicon wafer to 14 ppma or more, the growth rate of oxygen precipitates is increased, so that the overall process time can be reduced.

[0046] In the present invention, the diameter of the annealed wafer to be manufactured is 200 mm or more. be able to.

The method for producing annealed wafers of the present invention can be particularly suitably applied to the case of producing large-diameter annealed wafers having a diameter of 200 mm or more, in which slip dislocations are easily generated by heat treatment in the past. That is, according to the present invention, oxygen precipitates having a large size can be uniformly formed at a high density in the wafer surface as described above, so that the slip dislocation generated during the heat treatment is more likely to be pinned and the slip dislocation is increased. Can be suppressed. Therefore, it is possible to stably produce a large-diameter annealed wafer having no slip dislocation.

As described above, according to the present invention, heat treatment is performed under predetermined conditions on a silicon wafer that has many atomic vacancies and an Nv region in which the entire surface of the wafer has neither a grown-in defect nor an OSF. By manufacturing an anneal wafer, the oxide film withstand voltage characteristic of the surface layer of the wafer, which is the device fabrication area, is extremely excellent, and the oxygen precipitates are uniformly distributed in the plane before the device process is injected into the wafer barrier part. The present invention can provide an annealed wafer having excellent IG capability.

Brief Description of Drawings

FIG. 1 is a flowchart showing an example of a method for producing an annealing machine according to a first embodiment of the present invention.

FIG. 2 is a schematic view schematically showing a pattern of a heat treatment applied to a silicon wafer in the first embodiment of the present invention.

FIG. 3 is a flowchart showing an example of a method for producing an annealing device according to a second embodiment of the present invention.

FIG. 4 is a schematic view schematically showing a pattern of a heat treatment applied to a silicon wafer in a second embodiment of the present invention.

FIG. 5 is a schematic configuration diagram showing an example of a single crystal pulling apparatus that can be used in the method for producing annealed wafers of the present invention.

FIG. 6 is a graph showing temperature distributions of the single crystal pulling apparatus used in the example and the single crystal pulling apparatus used in the comparative example. FIG. 7 is a diagram showing a result of identifying a crystal defect region and a result of obtaining an initial oxygen concentration and an amount of precipitated oxygen with respect to a vertically divided sample of an example.

FIG. 8 is a view showing a result of identifying a crystal defect region in a vertically divided sample of a comparative example.

FIG. 9 is a graph showing density values and in-plane distributions of oxygen precipitates (BMD) in annealed wafers manufactured in Examples and Comparative Examples.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described, but the present invention is not limited thereto.

The inventors of the present invention have reported that the ィ wafer surface layer has a very excellent oxygen-withstand voltage characteristic, and the バル wafer, in which oxygen precipitates are uniformly and densely present in the plane before the device process is introduced, in the バル balta section. In order to manufacture it, intensive experiments and studies were repeated. As a result, when oxygen precipitation heat treatment was performed, for example, at 800 ° C for 4 hours + 1000 ° C for 16 hours, the oxygen precipitation amount (i.e., the initial oxygen concentration before the oxygen precipitation heat treatment and the oxygen Silicon wafers with a difference from oxygen concentration) of Ippma CiEIDA (Japan Electronic Industry Development Association standard) or higher have moderately thermally stable glow-in deposition nuclei. It was found that by performing the heat treatment, the grown-in precipitate nuclei could be grown in the で eno and Balta portions without disappearing, and oxygen precipitates could be formed stably.

On the other hand, in order to improve the breakdown voltage characteristics of the silicon oxide film of the wafer, a silicon wafer whose entire surface is an N region where neither a grown-in defect nor an OSF exists is used. When heat treatment is performed to form oxygen precipitates on the wafer, a DZ layer can be formed near the surface of the wafer, and oxygen precipitates can be formed on the Balta portion of the wafer. As described above, the N region includes the Nv region and the Ni region as described above, and the Ni region is a region in which oxygen precipitation is less likely to occur than the Nv region. When heat treatment is performed on silicon wafers in which Nv regions are mixed, the density of oxygen precipitates becomes non-uniform in the plane of the wafer, and as a result, the gettering ability of the wafer becomes non-uniform in the plane. It became clear that it becomes. Furthermore, in this case, the wafer may be warped due to the in-plane variation in the density of the oxygen precipitate. I also understood.

Thus, the present inventors have conducted further experiments and studies and found that, in the Nv region of silicon wafer, the amount of precipitated oxygen becomes lppma or more when the above oxygen precipitation heat treatment is performed. If annealed silicon wafers are manufactured by heat-treating silicon wafers in which the Nv region spreads over the entire surface of the wafer, the oxide film withstand pressure characteristics of the surface layer of the wafer are extremely excellent, and oxygen precipitates are formed on the wafer bar. The present invention has been completed by conceiving that a high-quality annealed wafer can be obtained in which the particles exist uniformly at high density in the plane.

That is, the annealing wafer of the present invention is an annealing wafer obtained by subjecting a silicon wafer produced from a silicon single crystal grown by the CZ method to a heat treatment, and the entire silicon wafer has both a grown-in defect and an OSF. It is characterized by having a large number of atomic vacancies and being in the Nv region, which is obtained by subjecting the silicon wafer to a heat treatment.

[0053] Further, such an anneal wafer of the present invention is a non-defective product having excellent surface pressure characteristics of an oxidized film in an area where the entire surface of the wafer is free of a grown-in defect and an OSF, and the surface area of the wafer is at least up to a depth of 5 m. Ratio is 95% or more, and the density of oxygen precipitates inside the eaves is 1 × 10 ⁹ Zcm ³ or more, and the ratio (maximum value) The characteristic value is that the value of (Z minimum value) is 1 to 10.

As described above, in the anneal wafer of the present invention, since the defect-free layer is formed not only on the surface of the wafer but also on the surface of the wafer at a depth of at least 5 μm, the yield rate is 95%. % Or more, and has excellent withstand voltage characteristics of the oxide film. For example, even when a device is manufactured up to a relatively deep region of the surface portion of the wafer, the wafer is not degraded in device characteristics. be able to. Here, the oxide film compression characteristic in the present invention means a TZDB (Time Zero Dielectric Breakdown) characteristic, and the non-defective rate is, for example, assuming that the determination current value is ImAZcm ² and the dielectric breakdown electric field is 8 MVZcm or more. Show the ratio of

As a simple method for detecting a defect on the surface layer of the wafer, for example, a particle cow And selective etching methods. However, even when a defect is inspected by using these methods, a defect having a small size equal to or smaller than the lower detection limit may be present, which may deteriorate the withstand voltage characteristics of the oxide film. Therefore, as described above, it is extremely important to have an excellent silicon oxide film withstand voltage characteristic such that the non-defective product of the present invention is 95% or more and further 100%.

[0056] Further, Aniruueha of the present invention, the density of Ueha internal (Butler portion) oxygen precipitate above size having an IG capability is detected Te odor as described above is 1 X 10 ⁹ Zcm ³ or more, It has excellent IG capability at the stage before device process introduction, and even in recent years of low temperature and short-time device processes, the oxygen precipitates in the Aehbarta part are also used as gettering sites for the initial stage of the device process. It can function as an aera that can exhibit sufficient gettering ability without adding special heat treatment. At this time, in consideration of the mechanical strength of the anneal wafer, the density of oxygen precipitates is preferably set to 1 × 10 ¹³ Zcm ³ or less in order to prevent deterioration due to excessive precipitation.

In the present invention, the size of the oxygen precipitate having IG capability is based on the size of the oxygen precipitate (for example, about 30 to 40 nm in diameter) which can be detected experimentally. The size of the oxygen precipitate having the ability is preferably about 40 nm or more in diameter. In general, it is considered that an oxygen precipitate having a size that cannot be detected experimentally has IG capability. It can be determined that it has sufficient IG capability. Such oxygen precipitates can be detected, for example, by infrared scattering tomography, which is one of the light scattering methods.

[0058] Furthermore, in the case of the conventional ゥ Aha, the value of the ratio (maximum value Z minimum value) between the maximum value and the minimum value of the density of oxygen precipitates in the ゥ a plane is 20 or more, or an order of magnitude higher! According to the present invention, the ratio of the maximum density to the minimum density (maximum value Z minimum value) of the oxygen precipitates in the wafer surface is 110, and more preferably 115. Therefore, the in-plane variation of the IG capability at the ehabalta section can be significantly reduced, and the ewa can have an extremely excellent gettering ability uniformly over the entire surface of the eha. In this case, the density of oxygen precipitates in the Problems such as warpage of the wafer, which have occurred due to the knock, can be easily solved.

[0059] In addition, in the case of a wafer having a diameter of 200 mm or more in which slip dislocation is likely to be generated by the annealing treatment of the present invention, oxygen precipitates having an effect of suppressing the occurrence of slip dislocation are uniformly formed on the surface of the wafer. Because of its high density and high density, it becomes a large-diameter wafer that suppresses the occurrence of slip dislocations in the device process, and becomes a very effective wafer especially in the future mainstream wafers of 300 mm or more.

Next, a method for producing the above-described anneal wafer of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.

First, the method for manufacturing an annealing wafer according to the first aspect of the present invention is a method for manufacturing a silicon wafer from a silicon single crystal grown by the CZ method and subjecting the manufactured silicon wafer to a heat treatment to manufacture an annealing wafer. In addition, as the silicon wafer, a silicon wafer having an Nv region with many vacancies in which the entire surface of the wafer has neither a grown-in defect nor an OSF is prepared. , At least at a temperature of 500 ° C or more and 700 ° C or less at T ° C for a predetermined time,

11 t 11 ° C At a heating rate of 11 ° C or less, the temperature is raised to a temperature T ° C of 1000 ° C or more and 1230 ° C or less, and then the temperature T ° C

It is characterized in that a heat treatment for holding for a predetermined time t is performed at 12 12.

12

[0061] Hereinafter, the method for producing an anneal wafer according to the first embodiment of the present invention will be described more specifically. Here, FIG. 1 is a flow chart showing an example of a method for producing an annealing wafer according to the first embodiment of the present invention, and FIG. 2 is a schematic drawing schematically showing a heat treatment pattern applied to a silicon wafer. It is.

First, a silicon wafer, which is a raw material for annealed wafer, is produced from a silicon single crystal grown by the CZ method (Step 101 in FIG. 1). At this time, there is no grown-in defect or OSF on the entire surface of the silicon wafer to be manufactured. If there is a lot of atomic vacancies and Nv region, the manufacturing method is particularly limited. For example, as described in WO 01Z057293 pamphlet, WO 02,002852 pamphlet, and Japanese Patent Publication No. 2002-226296, the pulling speed when growing a single crystal The ratio between F and the temperature gradient G near the solid-liquid interface in the pulled crystal. A wafer can be manufactured using a method of pulling a crystal. Here, an example of a method for manufacturing a silicon wafer in the present invention will be specifically described.

FIG. 5 shows an example of a single crystal pulling apparatus for pulling a silicon single crystal. As shown in FIG. 5, the single crystal pulling apparatus 20 includes a crucible driving mechanism including a quartz crucible 5 containing a raw material melt 4 and a graphite crucible 6 protecting the quartz crucible 5 in a main chamber 1. (Not shown) rotatably and vertically supported by a holding shaft 19, and a heater 7 and a heat insulating material 8 are arranged so as to surround these crucibles 5 and 6. A pulling chamber 2 for containing and removing the grown single crystal 3 is connected to the upper portion of the main chamber 1, and a single crystal 3 is pulled above the pulling chamber 2 while rotating the single crystal 3 with a wire 16 above the pulling chamber 2. A lifting mechanism (not shown) is provided.

A gas rectifying cylinder 13 is provided inside the main chamber 1, and a heat shield member 14 is provided below the gas rectifying cylinder 13 so as to face the raw material melt 4. The radiation from the surface of the melt 4 is cut, and the surface of the raw material melt 4 is kept warm. At this time, the heat shield member 14 is installed such that the distance between the lower end thereof and the surface of the raw material melt 4 is about 2 to 20 cm, for example. Further, a cooling cylinder 11 is provided above the gas rectification cylinder 13 so that the single crystal 3 can be forcibly cooled by flowing a cooling medium from the refrigerant inlet 12.

Further, an inert gas such as argon gas or the like can be introduced from a gas inlet 10 provided in the upper part of the pulling chamber 2, and passes between the single crystal 3 being pulled and the gas rectifying cylinder 13. After that, it can pass between the heat shield member 14 and the melt surface of the raw material melt 4 and be discharged from the gas outlet 9.

Further, a magnet (not shown) can be provided outside the main chamber 1 in the horizontal direction, whereby a magnetic field such as a horizontal direction or a vertical direction is applied to the raw material melt 4 so that the raw material melt 4 is applied. The so-called MCZ method, which suppresses the convection of the crystal and stably grows the single crystal, can be used.

When a silicon single crystal is grown by the CZ method using such a single crystal pulling apparatus 20, for example, first, a high-purity polycrystalline silicon material is melted in a quartz crucible 5 at a melting point (about 1420 ° C.). Heat and melt as above. Next, the wire 16 is unwound and the silicon melt 4 is unwound. The seed crystal 17 fixed to the seed holder 18 is brought into contact with or immersed in the approximate center of the surface of the substrate. After that, the crucible holding shaft 19 is rotated in an appropriate direction, and the wire 16 is wound while the wire 16 is not rotated and the seed crystal is pulled up to start growing the single crystal. Thereafter, by adjusting the pulling speed of the single crystal and the temperature of the silicon melt appropriately, a substantially cylindrical silicon single crystal 3 can be grown.

[0068] At this time, the pulling speed when growing the single crystal straight body portion was F [mmZmin], and the crystal temperature gradient in the pulling axis direction from the melting point of silicon to 1400 ° C was represented by G [° CZmm]. At this time, a silicon single crystal is grown by controlling the pulling speed F so that the value of FZG [mm ² Z ° C · min] is in the Nv region. In this case, for example, by setting the distance between the lower end of the heat shield member 14 and the surface of the raw material melt 4 to about 2 to 20 cm as described above, the temperature gradient Gc at the center of the crystal and the temperature gradient Ge at the periphery of the crystal can be obtained. In addition, the furnace temperature can be controlled so that the difference in crystallinity is small, and the temperature gradient around the crystal is lower than the crystal center, so that the entire surface in the crystal diameter direction can easily be in the Nv region. It becomes possible. Furthermore, for example, the cooling zone 11 installed above the gas flow straightening column 13 can rapidly cool the temperature zone (1080-1150 ° C) in which void defects are formed, thereby expanding the Nv region in the crystal growth axis direction. Therefore, it is possible to easily grow a single crystal in which the entire body is in the Nv region over the entire radial direction.

[0069] The silicon wafer obtained by slicing the silicon single crystal obtained as described above is a silicon wafer that has no atomic defects and no OSF and is an Nv region with many atomic vacancies. With such a silicon wafer, it is preferable to use a silicon wafer that does not have any grown-in defects or oxygen precipitates in the surface layer of the wafer when heat treatment is performed thereafter, and that a high oxygen deposition amount can be obtained in the wafer bar part. it can.

[0070] In this case, the silicon wafer is preferably manufactured from a silicon single crystal grown without adding nitrogen. In the case of a silicon wafer fabricated from a silicon single crystal grown without adding nitrogen as described above, there is no thermally stable grown-in precipitation nucleus, for example, a precipitation nucleus having a diameter of 40 nm or more in the wafer. When the heat treatment of the present invention is performed as shown in the figure, the force near the surface of the wafer can eliminate the grown-in precipitate nuclei and form the DZ layer stably. Also, since it is not necessary to add nitrogen when growing a silicon single crystal, the crystal growing process is not complicated, and the operation and management are simplified. Have.

In the present invention, the method for producing a silicon wafer from a silicon single crystal is not particularly limited. For example, after slicing a silicon wafer from a silicon single crystal, chamfering, lapping, By sequentially performing each process such as etching and mirror polishing, a silicon wafer can be easily manufactured.

Next, after the silicon wafer manufactured as described above is put into a heat treatment furnace maintained at a temperature T ° C. of, for example, 500 ° C. or more and 700 ° C. or less (Step 102 in FIG. 1), Shown in Figure 2

11

As a result, the temperature is maintained at the temperature T ° C. for a predetermined time t (step 103 in FIG. 1). Like this

11 11

By holding for a predetermined time t at a temperature T ° C, the wafers

11 11

By growing the grown-in precipitation nuclei, it is possible to eliminate the precipitation nuclei existing in the ehabalta part, and to generate new oxygen precipitation nuclei in the eha.

At this time, the holding temperature T is a temperature at which the grown-in precipitation nuclei can be grown.

11

Therefore, the lower the temperature, the higher the density of the oxygen precipitates in the annealed wafer after heat treatment.The longer the process time, the lower the productivity may be.Therefore, the temperature T is 500 ° C or more. Is desirable. On the other hand, when the temperature T exceeds 700 ° C

11 11

If the temperature is too high, the density of oxygen precipitates may not be sufficiently increased.

[0074] Further, in this case, the time t for holding the silicon wafer at the temperature T is 15 minutes or more.

11 11

Therefore, it is possible to make the grown-in precipitation nuclei more difficult to eliminate, and to generate new oxygen precipitation nuclei effectively on the wafer to form oxygen precipitation nuclei with higher density. it can. In addition, if the holding time t is too long,

11

Holding time t is about 6

11

It is preferable to set the time to 0 minutes or less. Incidentally, the silicon wafer is maintained at the temperature T as described above.

In the case of 11, the temperature is not limited to being maintained at a constant temperature with high accuracy.

It can also be accompanied by a temperature change (eg, temperature rise or fall of about ± 100 ° C). That is, the temperature T may be 500 ° C or more and 700 ° C or less, and when maintaining the temperature,

11

It is not always necessary to keep the temperature constant, as long as it is maintained within the temperature range. In other words, the term “maintaining at a temperature T ° C for a predetermined time” in the present invention means that the temperature T 500-700 ° C This includes the case where it is varied and held.

Next, FIG. 2 shows a silicon wafer held at a temperature T of 500 ° C. or more and 700 ° C. or less.

11

As a result, the temperature rises from 1000 ° C to 1230 ° C at a temperature increase rate of 5 ° CZ or less to T ° C.

12 Warm up (step 104). As described above, by raising the temperature of the silicon wafer at a rate of 5 ° CZ or less, high-density grown-in precipitate nuclei existing in the wafer can be grown efficiently without disappearing as much as possible. The lower the heating rate, the higher the precipitate density. Therefore, by performing the temperature raising step in this manner, the grown-in precipitation nuclei formed when growing a single crystal can be effectively grown, so that, for example, oxygen precipitation nuclei are newly formed on the wafer. The precipitate density can be sufficiently increased without separately performing a heat treatment step, and the entire process time can be reduced. At this time, the temperature T

11 to temperature T

If the rate of temperature rise to 12 ° C is so high as to exceed 5 ° CZ, the rate at which the grown-in precipitate nuclei do not grow and disappear will increase, resulting in insufficient density of oxygen precipitates. There is. On the other hand, if the speed is too low, the process time becomes longer than necessary.

In the present invention, the lower the temperature T, the longer the holding time t at the temperature T.

11 11 11 The lower the rate of temperature rise from temperature τ to the temperature τ,

11 12

It is possible to increase the density of oxygen precipitates in the annealed wafer after the heat treatment, which facilitates the formation of new oxygen precipitated nuclei, and to increase the temperature τ according to the desired quality of the annealed wafer.

, Holding time t, and heating rate from temperature T to temperature T can be set as appropriate.

1 11 11 12

The

[0077] Then, as described above, the silicon wafer is heated to a temperature T ° C of not less than 1000 ° C and not more than 1230 ° C.

After the temperature is raised in step 12, the temperature is maintained at the temperature T ° C for a predetermined time t (step 105). Like this

12 12

Oxygen precipitates in Aehbarta are further grown by holding at a temperature τ for a predetermined time.

12

As a result, oxygen can be increased to a size having gettering ability, and at the same time, oxygen in the vicinity of the surface of the evaporator can be diffused outward to eliminate oxygen precipitate nuclei, thereby forming a DZ layer free of oxygen precipitates on the surface layer of the evaporator.

At this time, when the temperature T becomes lower than 1000 ° C., the oxygen precipitates The time required to grow large amounts of metal becomes longer, and the overall process time becomes longer. On the other hand, the higher the temperature T, the more the oxygen precipitates have a desired size, that is, the gettering ability.

12

The time required to grow to a size having a short time and the power that can shorten the overall process time.At high temperatures exceeding about 1230 ° C, there is a risk of significant metal contamination in the heat treatment furnace. The temperature is preferably set to 1230 ° C or lower. Furthermore, during heat treatment,

12

In order to suppress the occurrence of slip dislocations that occur in wafers, the temperature T should be 1200 ° C or less.

12

In this way, it is more preferable to keep the silicon wafer at a temperature of 1200 ° C or less, and even 1150 ° C or less, so that the oxygen precipitate in the wafer balta part grows. At the same time, a DZ layer can be formed on the surface of the wafer, which is particularly effective when heat-treating large-diameter wafers with a diameter of 200 mm or more, in which slip dislocations are likely to occur.

[0079] The time t maintained at this temperature T is determined by the growth-in precipitation nuclei in the Ehabarta part.

12 12

It is preferable that the heating time is 30 minutes or more in order to surely grow the DZ layer to a size having gettering ability, and to form a DZ layer having a sufficient width on the surface layer of the wafer. By increasing the retention time t in this way to 30 minutes or longer, oxygen precipitates in the

12

Can be grown to have a diameter of about 30 nm to 40 nm, or even about 50 nm or more, and at the same time, to form a DZ width near the wafer surface and increase its width be able to. If the time t becomes too long,

12

The time t should be about 4 hours or less, or even about 2 hours or less, as this may reduce productivity.

12

Preferably, the size of the oxygen precipitate to be grown is less than 100 nm. On the other hand, if the holding time t is shorter than 30 minutes,

12

There is a possibility that oxygen precipitates and DZ widths of the same size cannot be obtained.

Further, in the step of maintaining the temperature at the temperature T (step 105), the silicon wafer is heated

12

In the process (steps 102-104) from the time of charging into the processing furnace until the temperature rises to the temperature T ° C

12

The purpose is to further grow oxygen precipitates in the grown barta and to form a DZ layer near the surface. Therefore, if the purpose can be achieved, it is not limited to maintaining the temperature at a constant temperature with high accuracy.

12

(For example, temperature rise and fall of about ± 100 ° C.). That is, the temperature T is 1 It is sufficient if the temperature is maintained between 000 ° C and 1230 ° C, so it is sufficient to maintain the temperature within this temperature range, and it is not necessary to keep the temperature constant. At the temperature T in the present invention,

12 To hold for a specified time means to change the temperature T within the range of 1000

12

Including the case of holding. Furthermore, in the present invention, by adjusting the temperature τ for holding the silicon wafer at a high temperature and the holding time t, the oxygen formed on the anneal wafer is adjusted.

12 12

The size of the precipitate can be easily controlled.

After performing the heat treatment as described above, for example, as shown in FIG.

After cooling down from 12 ° C to 700 ° C at a rate of about 2 ° CZ (temperature lowering step: Step

106), the silicon wafer is taken out of the heat treatment furnace (step 107). The temperature drop rate and the temperature at which the wafer is taken out after the temperature is lowered are not particularly limited. For example, it is preferable that slip dislocation due to thermal stress does not occur when the temperature of the wafer is dropped or when the wafer is taken out.

[0082] Further, in the present invention, the heat treatment atmosphere when performing the above heat treatment is not particularly limited. For example, the heat treatment can be performed in an oxygen atmosphere, a mixed atmosphere of oxygen and nitrogen, an argon atmosphere, a hydrogen atmosphere, or the like. In particular, in the case of a non-oxidizing atmosphere of argon or hydrogen, since an oxide film is not formed on the surface of the evaporator, outward diffusion of oxygen is promoted as compared with the case of the oxidizing atmosphere, which may be more preferable.

As described above, after the silicon wafer serving as the Nv region is manufactured, the manufactured silicon wafer is subjected to a heat treatment under the above conditions, whereby the above-described anneal wafer of the present invention, that is, the silicon wafer is manufactured. The entire surface is free of any grown-in defects or OSFs.Ν The area is ゥ A surface area of the wafer. The non-defective rate of the oxide film breakdown voltage characteristic is at least 95% in the area up to a depth of 5 μm. at a density of things IX 10 ⁹ / cm ³ or more, a high quality value of the ratio between the maximum value and the minimum value of the density of oxygen precipitates in Ueha plane (maximum value Z minimum value) is 1 one 10 Aniruueha Can be easily and stably manufactured.

Further, in the present invention, by using a silicon wafer to be subjected to the above heat treatment, the oxygen concentration of the wafer being 14 ppma or more, it is possible to form oxygen precipitates at a higher density on the wafer barter part. With better IG capability for Anil @ eha can do. In addition, if the oxygen concentration of silicon wafer is increased to 14 ppma or more, the growth rate of oxygen precipitates is increased, so that the entire process time can be shortened. Then, the oxygen concentration of the silicon wafer subjected to the heat treatment is preferably 23 ppma or less, more preferably 17 ppma or less.

Next, a method for producing an annealing wafer according to the second embodiment of the present invention will be described. In the method for manufacturing an annealing wafer according to the second embodiment of the present invention, a silicon wafer is grown from a silicon single crystal grown by the CZ method. In the method of producing and subjecting the produced silicon wafer to a heat treatment to produce an annealing wafer, the silicon wafer does not have any grown-in defects or OSF on the entire surface of the silicon wafer !, a large number of atomic vacancies, Nv After the silicon wafer serving as a region is manufactured, the manufactured silicon wafer is at least heated to a temperature T.

2

From the temperature T to the temperature T ° C at a temperature rise rate of R ° CZ.

1 22 1 1 2

From ° C to temperature T ° C, the heating rate of R ° CZ different from the heating rate in the heating step A

2 23 1 2

And a holding step C of holding the temperature T ° C for a predetermined time t.

1 23 21 1 is performed.

[0086] Hereinafter, the method for producing an anneal wafer according to the second embodiment of the present invention will be described more specifically. Here, FIG. 3 is a flow chart showing a method for producing an annealing wafer according to the second embodiment of the present invention, and FIG. 4 is a schematic drawing showing a pattern of a heat treatment applied to a silicon wafer.

[0087] First, a silicon wafer to be used as a raw material for annealed silicon is produced from a silicon single crystal grown by the CZ method (Step 201 in FIG. 3). The silicon wafer can be manufactured using the same method as the method for manufacturing the silicon wafer in the first embodiment (step 101 in FIG. 1).

Next, the produced silicon wafer is subjected to a heat treatment maintained at, for example, a temperature T ° C.

twenty one

After charging the furnace (step 202 in FIG. 3), as shown in FIG.

Heating process A is performed in which the temperature is raised at a rate of R ° CZ up to 21-22 (Step 203 in Fig. 3). By performing the heating step A as described above, the density of oxygen precipitates can be increased by efficiently growing the grown-in precipitation nuclei formed in the crystal growth step without extinction as much as possible. The

At this time, if the temperature T exceeds the temperature S 700 ° C., the gross

twenty one

The temperature T is preferably set to 700 ° C or lower, since the concentration of oxygen precipitates in the annealed wafer after the heat treatment may not be sufficiently obtained because the precipitate nuclei easily disappear.

twenty one

No. Also, the lower the temperature τ, the higher the density of grown-in precipitate nuclei

twenty one

Can further increase the density of oxygen precipitates, but the process time required to grow the grown-in precipitation nuclei increases, which may lead to a decrease in productivity.

twenty one

It is preferable to be 0 ° C or more!

[0090] In addition, the heating rate R from the temperature T to the temperature T in the heating step A

If the temperature exceeds 1 21 22 1 ° CZ, the growth-in precipitation nuclei may not be sufficiently grown, and the growth-in precipitation nuclei may disappear in the subsequent process. It is preferable that the temperature be not more than ° CZ. Also, the lower the heating rate R, the lower the rate of growth of the grown-in precipitation nuclei without extinction, which is desirable.However, if the heating rate R is too low, the process time becomes longer and it is not efficient. Is preferably 0.5 ° CZ or more.

[0091] Further, in this case, the temperature T after the heating is increased to 800

Preferably between 22 ° C and 1000 ° C

. If the temperature T is less than 800 ° C, there are not enough grown-in precipitation nuclei in the heating step A.

22 1

In some cases, the rate of disappearance in the subsequent heating step B1 increases, and the density of oxygen precipitates may not be sufficiently obtained. On the other hand, the temperature T

If the temperature of 22 exceeds 1000 ° C, the grown-in precipitation nuclei near the wafer surface also grow large, and the oxygen precipitates remain near the surface even after the subsequent heating step B and holding step C. DBecause a DZ layer cannot be formed on the surface of the wafer, the breakdown voltage characteristics of the oxide film may be reduced.

[0092] Further, in the present invention, it is possible to maintain the temperature T at the temperature T for 30 minutes or more before performing the heating step A.

1 21

preferable. Thus, before the heating step A, the silicon wafer is kept at the temperature T for 30 minutes or more.

1 21

With this, the growth-in precipitation nuclei can be further eliminated, and new oxygen precipitation nuclei can be effectively generated in addition to the growth-in precipitation nuclei, so that a higher oxygen concentration can be obtained in the silicon wafer. Precipitation nuclei can be formed. At this time, hold at temperature T

If the time is too long, the process time becomes unnecessarily long. Therefore, it is preferable to set the time to about 4 hours or less. When the silicon wafer is held at the temperature T, the temperature is kept constant. Not only high accuracy is maintained, but also slight temperature change around temperature τ depending on conditions.

twenty one

You can also. In other words, if the temperature T is 700 ° C or less,

twenty one

It is necessary to keep the temperature within the range of 700 ° C or less.

[0093] After performing the heating step A, as shown in Fig. 4, the temperature is raised from the temperature T ° C to the temperature T ° C.

1 22 23 Heating process B, in which the temperature is raised at a rate of R ° CZ faster than that of temperature process A, is performed (step in Fig. 3).

1 2 1 up 204). By performing the heating step B in this manner, the growth of oxygen precipitates in the vicinity of the wafer surface can be suppressed, and the temperature can be raised to the high temperature T in a short time.

twenty three

It is possible to suppress the growth of the oxygen precipitate in the surface layer more than necessary, and to easily eliminate the oxygen precipitate in the vicinity of the wafer surface in the subsequent holding step C.

[0094] At this time, if the heating rate from temperature T to temperature T is less than 5 ° C

22 23 2

Since there is a risk that oxygen precipitates in the vicinity will grow large and become difficult to disappear in the subsequent holding step C, the heating rate R2 in the heating step B1 should be 5 ° CZ min or more. preferable. On the other hand, if the heating rate R2 is too high, the oxygen precipitates in the ehabalta area may disappear in the holding step C, and it is considered that the oxygen precipitate density may decrease. Is desirably 10 ° CZ or less.

[0095] In the heating step B, the temperature T after the heating is set to 1050 ° C or more and 1230 ° C or less.

one two Three

Is preferred. Temperature T force S If the temperature is lower than 1050 ° C, the oxygen precipitates in the

23 1

It takes a long time to grow the desired size, and there is a risk that productivity may be reduced. By setting the temperature T to 1050 ° C or more, the holding process C

23 1 In addition to efficiently growing oxygen precipitates in the Balta part to a sufficient size, oxygen near the surface can be diffused outward to eliminate oxygen precipitate nuclei near the surface. The higher the temperature T, the larger the oxygen precipitates in the balter section and the larger the DZ width.

twenty three

If the temperature is higher than 1230 ° C, metal contamination of the heat treatment furnace may occur, so the temperature T is preferably set to 1230 ° C or less. In addition, it occurs on wafers during heat treatment

twenty three

In order to suppress the occurrence of slip dislocation, the temperature T should be 1200 ° C or less, or 1150 ° C

twenty three

The following is more preferable.

[0096] After performing the temperature raising step B, as shown in Fig. 4, the temperature is maintained at a temperature T ° C for a predetermined time t.

The holding process C is performed (step 205 in FIG. 3). By performing the holding process C in this manner, The fine oxygen precipitates grown in the temperature raising step and in the temperature raising step are grown to a size having an IG capability in the Aehark section, for example, a diameter of about 40 nm or more, and further, a diameter of about 5 Onm or more. In addition, since oxygen precipitates can be more completely eliminated near the wafer surface, an extremely high-quality DZ layer can be efficiently formed.

[0097] At this time, if the holding time t of the holding step C is shorter than 30 minutes, slight variations in the time may occur.

1 21

Therefore, the retention time t is preferably set to 30 minutes or more, since oxygen precipitates and DZ widths of desired sizes may not be obtained due to the above. Also, as the holding time t becomes longer,

21 21

This is preferable because the size of oxygen precipitates in the weld zone increases and the DZ width increases.However, in consideration of the productivity of Rinyl wafers, it is desirable that the retention time t be about 4 hours or less.

twenty one

No.

[0098] In the holding step C, the temperature T and the temperature at which the silicon wafer is held at a high temperature.

1 23 By adjusting the retention time t, the oxygen precipitation formed on the

twenty one

It is possible to easily control the size of the product and the DZ width of the surface layer of the wafer, and it is possible to efficiently and stably obtain an anneal wafer having a desired quality. Note that, in the holding step C, the constant temperature T is used as in the method according to the first embodiment of the present invention.

In addition to maintaining high accuracy at 23, slight temperature changes around temperature T (for example, about ± 100 ° C)

twenty three

Temperature rise, temperature decrease, etc.). That is, the temperature T is more than 1050 ° C and 1230 ° C

twenty three

If the temperature is maintained, it is sufficient to maintain the temperature within this temperature range, but it is not necessary to keep the temperature constant. When maintained for a predetermined time at the temperature T ° c referred to in the present invention.

twenty three

This includes the case where the temperature T is maintained within the range of 1050-1230 ° C.

twenty three

No.

[0099] After performing the heat treatment as described above, as shown in FIG.

twenty three

After the temperature is lowered to about 3 ° C / minute to about ° C (temperature drop process: Step 206), the silicon wafer is taken out of the heat treatment furnace (Step 207). The temperature drop rate and the temperature at which the wafer is taken out after the temperature is lowered are not particularly limited. For example, it is preferable to set conditions such that slip dislocation due to thermal stress does not occur when the temperature of the wafer is lowered or when the wafer is taken out. . Further, in the present invention, the heat treatment atmosphere when performing the heat treatment is also the first mode. There is no particular limitation as in the above.

[0100] In the method for producing an anneal wafer according to the second aspect of the present invention, for example, the wafer is heated between the above-mentioned heating step A and the heating step B and between the heating step B and the holding step C. A force that can be taken out of the heat treatment furnace and individually perform the heating step A, the heating step B, and the holding step C. In the present invention, the heating step A, the heating step B, and the holding step C are continuously performed. It is preferable to perform the heat treatment step, whereby the entire process time of the heat treatment step can be shortened, and the efficiency of the heat treatment step can be improved and the productivity can be improved.

[0101] After the silicon wafer serving as the Nv region is manufactured as described above, the manufactured silicon wafer is subjected to a heat treatment including at least the temperature raising step A, the temperature raising step B, and the holding step C. As a result, the above-described anneal wafer can be easily and stably manufactured.

[0102] Further, in this case, it is preferable to use silicon wafers having an oxygen concentration of 14 ppma or more as the silicon wafer to be subjected to the heat treatment. It is possible to add even better IG capability to annealed wafers. Furthermore, if the oxygen concentration of silicon / a wafer is increased to 14 ppma or more, the growth rate of oxygen precipitates is increased, so that the overall process time can be reduced. However, if the oxygen concentration of the silicon wafer is too high, oxygen precipitates near the surface of the silicon wafer may not easily disappear at a high temperature when heat treatment is performed on the silicon wafer. Therefore, the oxygen concentration of the silicon wafer subjected to the heat treatment is preferably 23 ppma or less, particularly preferably 17 ppma or less.

[0103] The method for producing an anneal wafer according to the first and second aspects of the present invention is suitable for producing a large-diameter anneal wafer having a diameter of 200 mm or more, in which slip dislocations are easily generated by heat treatment. It can be particularly preferably used. That is, according to the present invention, as described above, large-size oxygen precipitates can be uniformly formed at high density in the wafer surface, so that the slip dislocation generated during the heat treatment is more likely to be pinned and the slip dislocation is reduced. Can be suppressed. Therefore, it is effective for large-diameter wafers in which slip dislocations are easily generated, and large-diameter annealed wafers in which slip dislocations are not generated. Ichino, in particular, will be able to produce stable, high-yield annealed wafers with a diameter of 200 mm or even 300 mm or more, which will become the mainstream in the future.

Hereinafter, the present invention will be described more specifically with reference to Examples and Comparative Examples, but the present invention is not limited thereto.

(Example)

As shown in FIG. 5, using a single crystal bow I pumping device 20 comprising a cooling cylinder 11 for forcibly cooling the single crystal by flowing a cooling medium and capable of applying a horizontal magnetic field to the raw material melt, A 24-inch quartz crucible is charged with 150 kg of silicon polycrystal, and while applying a horizontal magnetic field of a central magnetic field strength of 4000 Gauss, a silicon single crystal having a diameter of 200 mm, an orientation of 100> and an oxygen concentration of about 15 ppma (j EIDA) is directly transferred. It was raised so that the length of its torso was about 130 cm.

At this time, no nitrogen was added to the single crystal to be grown, and the difference between the crystal temperature gradients G in the single crystal plane (ie, the difference between the temperature gradient Gc at the center of the crystal and the temperature gradient Ge at the periphery of the crystal) The distance between the silicon melt surface and the heat-insulating member 14 was set to 60 mm so as to keep the crystal growth small, and a single crystal was grown by gradually lowering the crystal growth rate in the crystal growth axis direction.

[0106] Next, a sample was prepared by dividing the grown silicon single crystal vertically, and the vertically divided sample was subjected to selective etching to check the occurrence of FPD and LEPD, and was also subjected to thermal oxidation treatment at 1150 ° C for 100 minutes. And confirmed the occurrence of OSF. After 4 hours at 800 ° C, precipitation heat treatment was performed at 1000 ° C for 16 hours, and crystal defect regions of the silicon single crystal were identified by lifetime mapping and the like. Figure 7 shows the results. As shown in FIG. 7, it can be seen that the defect-free region, particularly the Nv region, is very large due to the quenching effect of the cooling cylinder 11.

[0107] In addition, the initial oxygen concentration before the precipitation heat treatment and the precipitated oxygen concentration after the precipitation heat treatment were measured in the growth axis direction of the vertically divided sample prepared above, and the initial oxygen concentration and the precipitated oxygen concentration after the precipitation heat treatment were measured. The oxygen precipitation amount, which is the difference from the concentration, was determined. FIG. 7 shows a graph showing the measured initial oxygen concentration and the amount of precipitated oxygen. As a result, it is clear that the amount of precipitated oxygen is equal to or more than lp pma QEIDA) in the Nv region, but hardly precipitates in the Ni region.

[0108] Next, based on the above results, the silicon single crystal was pulled at a growth rate such that a single crystal only in the Nv region was obtained. At this time, the initial oxygen concentration is 15 ppm as above. The production conditions were adjusted to be a. The silicon single crystal thus obtained was sampled at intervals of 2 Ocm in the growth axis direction, and the initial oxygen concentration was measured at in-plane intervals of 10 mm for the sampled wafer. After that, a heat treatment at 800 ° C. for 4 hours and a heat treatment for precipitation at 1000 ° C. for 16 hours were applied to the sample wafer to remove an oxide film caused by the heat treatment, and then the oxygen concentration was measured in the same manner as before the heat treatment. As a result, the amount of precipitated oxygen, which was obtained by subtracting the oxygen concentration after the precipitation heat treatment from the initial oxygen concentration force, exceeded lppma at all the measurement points in the plane for all of the sampled wafers. From this, it is considered that the silicon single crystal grown this time was able to be Nv region over the entire region of the single crystal straight body.

[0109] Then, after slicing the wafer from the silicon single crystal having the Nv region, chamfering, lapping, etching, and mirror polishing are performed to produce a mirror-polished silicon wafer, and argon is applied to the wafer. The following heat treatment was performed in an atmosphere. That is, after placing the silicon wafer in the heat treatment furnace heated to 700 ° C, holding it for 30 minutes, raise the temperature at a rate of 3 ° CZ up to 900 ° C, and further increase the temperature by 5 ° CZ up to 1150 ° C. The temperature was raised at a rate and maintained at 1150 ° C for 2 hours. After that, the temperature in the heat treatment furnace was lowered to 700 ° C at a rate of 3 ° CZ, and the wafer was taken out of the heat treatment furnace.

[0110] With respect to the annealed wafer subjected to the above heat treatment, the density of oxygen precipitates (BMD) inside the wafer was measured at 10 mm intervals from a position 10 mm from the center of the wafer by infrared scattering tomography, and the in-plane distribution was investigated. . According to the infrared scattering tomography method, an oxygen precipitate having a diameter of 40 nm or more can be detected. Figure 9 shows the results.

[0111] As shown in FIG. 9, the density of all of the oxygen precipitates in the measuring points Ueha plane becomes 1 X 10 ⁹ Zcm ³ or more, the density of the oxygen precipitates in Ueha plane at this time The value of the ratio of the maximum value to the minimum value (maximum value Z minimum value) was 2.7, indicating that oxygen precipitates existed uniformly and at high density in the Ehabarta area.

[0112] Further, in order to examine the breakdown voltage characteristics of the oxidized film of the above-described annealed wafer, the wafer was subjected to a thermal oxidation treatment in a dry atmosphere to form a 25 nm gate oxide film, and 8 mm of the gate oxide film was formed thereon. A phosphorus-doped polysilicon electrode having an electrode area of ² was formed. And this A voltage was applied to the polysilicon electrode formed on the silicon oxide film, and the TZDB evaluation was performed with the judgment current value set to ImAZcm ² and the dielectric breakdown electric field set to 8 MVZcm or more. As a result, it was found that the yield rate of the oxide film pressure resistance was 100%.

Further, another anneal wafer manufactured as described above was polished by mechanical and chemical polishing with a surface force of 5 m, and then subjected to the same TZDB evaluation as described above. As a result, the yield rate of the oxide film withstand voltage characteristics was 97%.

[0113] (Comparative example)

Next, the cooling cylinder 11 is removed from the single crystal pulling apparatus 20 shown in FIG. 5, and the cooling cylinder 11 is not provided. Charge 150 kg of the crystal and apply a horizontal magnetic field of central magnetic field strength of 4000 Gauss to a silicon single crystal with a diameter of 200 mm, an orientation of 100> and an oxygen concentration of about 15 ppma (jEIDA). It was raised so as to be gradually lowered. Here, FIG. 6 shows the result of analyzing the temperature distribution of the single crystal pulling apparatus used in the above example and comparative example. As shown in FIG. 6, it can be confirmed that the single crystal pulling apparatus of the comparative example has a lower degree of rapid cooling as compared with the example having the cooling cylinder.

[0114] Subsequently, similarly to the above example, a vertically divided sample was prepared from the grown silicon single crystal, and a crystal defect region of the silicon single crystal was identified. Fig. 8 shows the results. As shown in FIG. 8, it can be seen that it is almost impossible to grow a single crystal in which the defect-free region (N region) is very narrow and the entire surface is an Nv region as compared with the above example.

Next, based on the above results, the silicon single crystal was pulled at a growth rate such that a single crystal having a defect-free region having both the Nv region and the Ni region was obtained. At this time, the production conditions were adjusted so that the initial oxygen concentration was 15 ppma. Sample silicon was cut out from the silicon single crystal thus obtained at intervals of 20 cm in the growth axis direction, and the amount of precipitated oxygen was determined in the same manner as in the above example.

[0116] As a result, in all of the sampled wafers, the amount of oxygen precipitation did not exceed lppma at all measurement points in the plane. I was From this, the silicon single crystal grown this time It is considered that the Nv region and the Ni region coexist over the entire region.

[0117] A mirror-polished silicon wafer was produced from the silicon single crystal having the Nv region and the Ni region in the same manner as in the example, and was subjected to a heat treatment under the same conditions as in the example. For the annealed wafers subjected to the heat treatment, the density of oxygen precipitates (BMD) inside the wafers was measured by infrared scattering tomography at 10 mm intervals from the center of the wafers at 10 mm intervals, and the in-plane distribution was investigated. The results are shown in FIG.

[0118] As shown in FIG. 9, Aniruueha prepared in Comparative Example, the oxygen precipitates in at all measuring points the surface density in not become 1 X 10 ⁹ Zcm ³ or more, the low density of oxygen precipitate There were parts shown. At this time, the ratio of the maximum value to the minimum value of the oxygen precipitate density in the wafer surface (maximum value Z minimum value) was 25, and the in-plane distribution of oxygen precipitate density was uneven. there were.

[0119] The present invention is not limited to the above embodiment. The above embodiment is a mere example, and any one having substantially the same configuration as the technical idea described in the claims of the present invention and having the same function and effect will be described. Are also included in the technical scope of the present invention.

Claims

The scope of the claims

[1] An annealed wafer prepared by heat-treating a silicon wafer formed from a silicon single crystal grown by the Czochralski method, and the entire surface of the wafer is an N region where neither a grown-in defect nor OSF exists, and Keru us in the region to a depth of 5 m Sani匕膜breakdown voltage characteristic yield rate is 95% or more, and a density of oxygen precipitates inside Ueha is 1 X 10 ⁹ Zcm ³ or more, Ueha plane § ^ ~~ Norewe ¹ ~~ Nono the value of the ratio between the maximum value and the minimum value of the density of oxygen precipitate (the maximum value Z minimum value) characterized in that it is a 1 one 10 in.

[2] An annealed wafer obtained by heat-treating a silicon wafer produced from a silicon single crystal grown by the Czochralski method, wherein the entire surface of the silicon wafer has neither a grown-in defect nor an OSF. An annealed wafer having a large Nv region, wherein the silicon wafer has been subjected to a heat treatment.

3. The annealed wafer according to claim 1, wherein the diameter of the annealed wafer is 200 mm or more.

[4] In a method of manufacturing a silicon wafer from a silicon single crystal grown by the Czochralski method and subjecting the manufactured silicon wafer to a heat treatment to produce an annealing wafer, the silicon wafer is used as the silicon wafer. After producing a silicon wafer with Nv region with many vacancies, which has neither a grown-in defect nor OSF, the fabricated silicon wafer is specified at a temperature of at least 500 ° C and not more than 700 ° C T ° C. Time t hold

11 11 and then at a temperature T of 1000 ° C or more and 1230 ° C or less at a heating rate of 5 ° CZ or less.

12 Raise the temperature, and then perform a heat treatment to maintain the temperature T at this temperature T ° C for a predetermined time t.

12 12

Manufacturing method of Anil @ eha.

[5] The time t for keeping the silicon wafer at a temperature T ° C of 500 ° C or more and 700 ° C or less is set to 1

11 11

5. The method according to claim 4, wherein the time is 5 minutes or more.

[6] Time t for holding the silicon wafer at a temperature T ° C of 1000 ° C or more and 1230 ° C or less

The method for producing an annealed wafer according to claim 4 or claim 5, wherein the time is 12 minutes or more.

[7] In a method of producing a silicon wafer from a silicon single crystal grown by the Czochralski method and subjecting the produced silicon wafer to a heat treatment to produce an annealing wafer, the silicon wafer is treated as an entire surface of the wafer. However, after producing a silicon wafer with Nv region with many vacancies, which has neither a grown-in defect nor OSF, the fabricated silicon wafer has at least R ° CZ from temperature T ° C to temperature T ° C. At a heating rate

21 22 1

A temperature raising step A for raising the temperature, and a temperature raising in the temperature raising step A from the temperature T ° C to the temperature T ° C.

1 22 23 1 In the heating step B in which the heating rate is

An annealing characterized by performing a heat treatment having a holding step C for holding for a predetermined time t.

21 1

ゥ Manufacturing method of eha.

[8] The method of claim 7, wherein the heating step A, the heating step B, and the holding step C are sequentially performed.

[9] In the temperature raising step A, the temperature T is set to 700 ° C or less, and the temperature T is set to 800 ° C or less.

1 21 22

9. The method for producing an anneal wafer according to claim 7, wherein the temperature is not more than 1000 ° C., and the heating rate R is not more than 3 ° CZ.

[10] Before performing the temperature raising step A, the temperature T is maintained at the temperature T for 30 minutes or more.

1 21

The method for producing an annealed wafer according to any one of claims 7 to 9.

[11] In the heating step B, the temperature T is set to 800 ° C or more and 1000 ° C or less,

The temperature of 1 22 23 is 1050 ° C. or more and 1230 ° C. or less, and the heating rate R 2 is 5 ° C.Z or more. Method of producing annealed wafers

[12] In the holding step C, the temperature T is maintained at 1050 ° C or higher and 1230 ° C or lower.

one two Three

The time t is set to 30 minutes or more, any one of claims 7 to 11

twenty one

4. The method for producing an anneal wafer described in 1. above.

13. The method according to claim 4, wherein the silicon wafer to be subjected to the heat treatment is made of a silicon single crystal grown without adding nitrogen. The method for producing an anneal wafer described in the above.

14. The method according to claim 4, wherein the oxygen concentration of the silicon wafer subjected to the heat treatment is 14 ppma or more. 15. The method for producing annealed wafers according to claim 4, wherein the diameter of the manufactured annealed wafers is 200 mm or more.