JP2003243404A - Method of manufacturing annealed wafer and annealed wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an annealed wafer capable of reducing crystal defects in the outer layer of a wafer, uniform formation of a BMD (bulk micro-defect) in a bulk within a wafer surface and moreover suppressing the occurrence of slip dislocation. <P>SOLUTION: In a method of manufacturing an annealed wafer by growing a silicon single crystal by a Czochralski method, working the silicon single crystal to manufacture a silicon wafer and performing 10 to 600-minute high- temperature heat treatment to the manufactured silicon wafer at temperatures of 1,100°C to 1,350°C under an argon gas, hydrogen gas or mixed gas atmosphere of these, the silicon single crystal is grown by the Czochralski method under such a condition that an OSF (oxidation induced stacking fault) occurs on the entire surface of the silicon wafer. After performing pre-annealing to the silicon wafer that is manufactured by working the single crystal having the OSF occurring on the entire surface at the temperature below the heat-treatment temperature of the high-temperature heat treatment, the high-temperature heat treatment is performed by the method of manufacturing the annealed wafer. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an annealed wafer and an annealed wafer, and in particular, there are few crystal defects in the surface layer of the wafer, and internal microdefects (BMD) in the bulk are uniformly and densely in the plane of the wafer. The present invention relates to a method for manufacturing an annealed wafer and an annealed wafer which can be present in a wafer.

[0002]

2. Description of the Related Art In recent years, high integration and miniaturization of device processes and reduction of process temperature have been promoted, and obtained from a silicon single crystal grown by the Czochralski method (CZ method) which is mainly used. Of a silicon wafer to be processed, the integrity of the device active region in the surface layer, that is, a defect caused by a single crystal growth that deteriorates the oxide film breakdown voltage characteristic called a grown-in defect such as FPD, LSTD, and COP near the wafer surface. It is required to improve the gettering ability to capture impurities such as metal due to the increase of the BMD density of oxygen precipitates (nuclei) in the bulk.

Generally, in a silicon single crystal grown by a silicon single crystal pulling apparatus by the Czochralski method, atomic vacancies (vacancy, sometimes abbreviated as V hereinafter) and interstitial silicon (interstitial) are included.
-Si, which may be abbreviated as I hereinafter) occurs in two types of point defects, and there are V-regions in regions where there are many vacancy, that is, regions where there are many recesses caused by the lack of silicon atoms. A region having a large amount of dislocations and a lump of extra silicon atoms generated by doing so is called an I-region. Between this V-region and the I-region, there is a neutral region (Neutral region, hereinafter N-region) in which there is no excess or deficiency of atoms (neutral region, hereinafter N-region), and the V-region and the I-region
-OSF is applied near the boundary of the region by performing thermal oxidation.
(Oxidation Induced Stacki
It has been confirmed that defects called ng faults (oxidation-induced stacking faults) occur in a ring shape in a cross section perpendicular to the crystal growth axis.

The defect concentrations are the pulling rate (growth rate) V (mm / min) of the silicon single crystal when pulling the silicon single crystal by the CZ method and the crystal temperature gradient G (in the pulling axis direction near the solid-liquid interface). C / mm) relationship V / G
It is known to be decided from.

When classifying these defects caused by crystal growth,
For example, when the pulling speed is relatively high, such as around 0.6 mm / min or more, the grown-in defects, which are considered to be caused by voids that are a collection of vacancy-type point defects, are present at a high density in the entire crystal radial direction. The area where the defect exists is called a V-rich area. The pulling speed is 0.6mm
/ Min or less
L / D (Large Dislocation) is considered to be caused by dislocation loops in which F is generated in a ring shape and interstitial silicon type point defects are gathered outside the ring.
n: Abbreviation for interstitial dislocation loop, LSEPD, LFPD
Etc.) defects are present at a low density. The region where these defects exist is called the I-rich region.

In general, when a silicon single crystal is grown by the CZ method, it is often done under the growth condition of a V-rich region in order to improve productivity. At this time, the silicon single crystal to be grown is also doped with nitrogen in order to further improve the gettering ability of the wafer. Thereby, it is possible to manufacture a silicon single crystal in which oxygen precipitation is promoted and growth of grown-in defects is suppressed.

Further, a mirror-finished wafer sliced from the nitrogen-doped silicon single crystal and polished is subjected to an atmosphere of argon gas, hydrogen gas or a mixed gas thereof at 1100 to 1350 ° C. for about 10 to 600 minutes. By performing the high temperature heat treatment on the wafer, the crystal defects caused by the voids in the surface layer of the wafer caused by the voids disappear, and the density of oxygen precipitates in the bulk is increased to increase the IG (Inte
It is possible to manufacture a wafer (nitrogen-doped annealing wafer) having an rnal gettering effect.

However, as described above, when a silicon single crystal is grown by doping nitrogen under the growth conditions in which the V-rich region is predominant by the CZ method, a silicon wafer produced from this silicon single crystal is a wafer. A large grown-in defect such as COP was generated in the central region of the, and OSF was always generated in a ring shape in the peripheral portion of the silicon wafer.

Even if such a silicon wafer is subjected to high-temperature heat treatment in an atmosphere of argon gas or the like to grow oxygen precipitates in the bulk, oxygen precipitation occurs in the OSF region in the peripheral portion of the wafer and the V-rich region in the central portion. Because the behavior is different,
There is a problem that the BMD density in the in-plane of the wafer after the heat treatment is varied, and the uniformity of the in-plane of the BMD of the annealed wafer is low. Such variations in the BMD density on the wafer surface also cause a difference in the gettering ability of the wafer, which is one of the reasons for lowering the productivity and yield in the device process. It was.

Further, when a silicon single crystal is grown under such a condition that the V-rich region is dominant, the size of the vacancy-type crystal defects generated in the silicon wafer is large, so that high-temperature heat treatment is sufficient thereafter. In some cases, crystal defects could remain on the surface of the wafer without being able to eliminate them.

Further, when a large-diameter silicon wafer having a diameter of 200 mm or 300 mm or more, which is in great demand in recent years, is manufactured, when the wafer is subjected to high-temperature heat treatment under the atmosphere of argon gas or the like as described above, the obtained large size is obtained. Slip dislocations penetrating from the back surface to the front surface of the annealed wafer were significantly generated. Such slip dislocations grow further in the device process, cause defects in the device process, and are one of the factors that reduce the yield.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to reduce crystal defects in the surface layer of a wafer and to make BMD in the bulk uniform in the wafer surface. Can be formed in high density
Another object of the present invention is to provide an annealing wafer manufacturing method and an annealing wafer capable of suppressing the occurrence of slip dislocations.

[0013]

In order to achieve the above object, according to the present invention, a silicon single crystal is grown by the Czochralski (CZ) method, and the silicon single crystal is processed to produce a silicon wafer. Then, the prepared silicon wafer was exposed to argon gas, hydrogen gas, or a mixed gas atmosphere thereof at a temperature of 1100 to 1350 ° C. for 10 to 6 ° C.
In a method for producing an annealed wafer by performing a high temperature heat treatment for 00 minutes, a silicon single crystal is grown by the above-mentioned Czochralski method under the condition that an oxidation induced stacking fault (OSF) is generated on the entire surface of the silicon wafer, and the single crystal is processed. A method of manufacturing an annealed wafer is provided, which comprises performing pre-annealing at a temperature lower than the heat treatment temperature of the high temperature heat treatment on the silicon wafer on which OSF is generated on the entire surface produced by the above, and then performing the high temperature heat treatment. Item 1).

As described above, a silicon single crystal is grown by the CZ method under the condition that OSFs are generated on the entire surface of the silicon wafer, and the single crystal is processed to form a silicon wafer, thereby forming a void type in the wafer surface. It is not a mixture of crystal defects and OSF nuclei, but a silicon wafer in which OSF is generated on the entire surface of the wafer (O on the entire surface of the wafer).
It is possible to obtain a silicon wafer having SF nuclei). Further, by performing pre-annealing at a temperature lower than the high temperature heat treatment temperature on the silicon wafer on which OSFs are generated on the entire surface, oxygen precipitates can be uniformly grown in the wafer surface without growing slip dislocations.
By further performing high-temperature heat treatment thereafter, the size of the oxygen precipitates can be further grown while suppressing the growth of slip dislocations, and the crystal defects in the wafer surface layer can be surely eliminated. As a result, crystal defects in the surface layer of the wafer are reduced, and it is possible to manufacture an annealed wafer in which the BMD in the wafer surface is formed uniformly and at high density without slip dislocations.

At this time, it is preferable to dope nitrogen when growing the silicon single crystal by the Czochralski method (claim 2). As described above, since the OSF generation region is expanded by doping nitrogen when growing a silicon single crystal by the CZ method, it is possible to easily and stably grow a silicon wafer in which OSF is generated on the entire surface of the wafer. It will be possible. Moreover, since the generation of oxygen precipitation nuclei can be promoted by doping the silicon single crystal with nitrogen, the BMD density of the wafer can be further increased by subsequent heat treatment.

At this time, the silicon single crystal is doped.
The concentration of nitrogen is 1 x 10¹⁴/ Cm ^ThreeCan be less than
Preferred (Claim 3). Nitrogen doping of silicon single crystal
For making silicon wafers with high element concentration
Therefore, the OSF area generated on the silicon wafer is expanded.
Can be done, but the nitrogen concentration to be doped is too high
Secondary defects such as dislocation clusters in the OSF region, if
(Hereinafter referred to as LEP (Large Etch Pit)
May occur, and disappear by subsequent high temperature heat treatment.
May remain without. This secondary defect is the wafer surface
Existence in the vicinity, for example, when performing epitaxial growth
This causes defects in the epitaxial layer. Shi
Therefore, the concentration of nitrogen doped in the silicon single crystal is 1
× 10¹⁴/ Cm^ThreeIt is preferable to be less than
Therefore, OSF is generated on the entire surface of the wafer.
And the secondary defects
It is possible to reduce the occurrence of pre-annealing and high temperature heat.
Higher quality annealed wafers by processing
Can be manufactured.

Further, at this time, it is preferable that the pre-annealing at a temperature lower than the high temperature heat treatment temperature is performed in one step for at least 2 hours or more (claim 4). By performing the pre-annealing at a temperature lower than the high temperature heat treatment temperature in one step for at least 2 hours or more in this way, it is possible to surely grow the oxygen precipitates and suppress the growth of slip dislocations, and at the same time, crystal defects on the wafer surface The reducing effect can be further enhanced.

At this time, the temperature range of the pre-annealing is set to 9
The temperature is preferably set to 50 to 1050 ° C (claim 5).
Thus, by setting the temperature range in which pre-annealing is performed to 950 ° C. or higher, oxygen precipitates can be efficiently grown without taking time, and by setting it to 1050 ° C. or lower, slip dislocations are generated in pre-annealing. Oxygen precipitates can be grown without growing. Further, by performing pre-annealing in such a temperature range, the crystal defects on the wafer surface can be effectively eliminated by the subsequent high temperature heat treatment.

In this case, the pre-annealing is performed first.
2 of annealing (temperature T1) and second annealing (temperature T2)
It is preferable that T1 <T2 is satisfied in the step (Claim 6). In this way, the pre-annealing is performed in two steps,
By setting the relationship between the respective heat treatment temperatures to be T1 <T2, the size of the oxygen precipitates is grown to some extent in the first annealing, and then the second annealing is performed at a temperature T2 higher than that to ensure slip dislocation. While being suppressed, the oxygen precipitate can be further grown in a relatively short time.

Further, the temperature T1 of the first annealing is set to 1
It is preferable that the temperature T2 of the second annealing is 000 ° C. and 1050 ° C. (Claim 7). As described above, by setting the temperature T1 of the first annealing to 1000 ° C., the size of the oxygen precipitates can be increased without growing slip dislocations, and the oxygen precipitates can be increased to some extent in the first annealing at 1000 ° C. The growth of the size of (1) makes it possible to reliably suppress the growth of slip dislocations even if the second annealing is performed at 1050 ° C., and further grow the oxygen precipitates in a relatively short time.

Further, according to the present invention, the above manufacturing method reduces the crystal defects in the surface layer of the wafer, and the BMD.
It is possible to provide an annealed wafer in which is uniformly and densely formed on the surface of the wafer and slip dislocations are reduced. Such an annealed wafer has a high gettering ability and does not cause a difference in gettering ability in the plane of the wafer, so that an annealed wafer of high quality can be obtained.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below, but the present invention is not limited thereto. First, the Czochralski method (CZ used in the present invention
FIG. 4 shows an example of a silicon single crystal pulling apparatus according to the method). This silicon single crystal pulling apparatus 20 includes a quartz crucible 5 filled with a silicon melt 4, a graphite crucible 6 for protecting the quartz crucible 5, a heater 7 and a heat insulating material 8 arranged so as to surround the crucibles 5, 6. , And the upper heat insulating material 13 arranged thereon is installed in the main chamber 1,
A pulling chamber 2 for accommodating and taking out the grown single crystal 3 is connected to the upper part of the main chamber 1.

In order to grow the single crystal 3 using such a manufacturing apparatus, the seed crystal is immersed in the silicon melt 4 in the quartz crucible 5 and then gently pulled up while being rotated through a seed diaphragm to obtain a rod-like shape. The single crystal 3 is grown. On the other hand, crucibles 5 and 6
Can move up and down in the crystal growth axis direction, and raises the crucible so as to compensate for the decrease in the melt surface level that was crystallized and decreased during crystal growth, thereby keeping the melt surface height constant. ing. In addition, an inert gas such as argon gas is introduced into the main chamber 1 from a gas inlet 10 provided at the upper part of the pulling chamber 2, and the single crystal 3 being pulled
And the gas flow rectifying cylinder 11, and between the lower part of the heat shield member 12 and the melt surface, and is discharged from the gas outlet 9.

Conventionally, when a silicon single crystal is grown by doping nitrogen under the condition of a V-rich region by the CZ method and a silicon wafer is manufactured from the silicon single crystal, the V-rich region is formed at the center of the wafer. However, as shown by the range R in FIG. 1B, the OSF ring region was always present in the peripheral portion. After that, when such a silicon wafer is subjected to a high temperature heat treatment, the vacancy type crystal defects generated in the V-rich region are large in size and thus are hard to disappear, and the crystal defects remain on the surface layer of the annealed wafer. was there. Further, as described above, vacancy-type crystal defects and OS are present in the surface of the silicon wafer.
Since the F nuclei are mixed, the oxygen precipitation behavior during the high temperature heat treatment is different between the central portion and the peripheral portion of the wafer, which causes variations in the BMD density of the annealed wafer.
There is a problem that the in-plane uniformity of the BMD density on the wafer is poor.

When a large-diameter silicon wafer having a diameter of 200 mm or 300 mm or more is manufactured by using such a conventional method, the annealed wafer after the high temperature heat treatment is processed from the rear surface to the front surface of the wafer regardless of the presence or absence of nitrogen doping. There has been a problem that slip dislocations penetrating are remarkably generated.

In view of the above problems, the inventors of the present invention, in the production of an annealed wafer, first grow a silicon single crystal under the condition that the distribution of crystal defects is not mixed in the single crystal. It is possible to grow a silicon wafer by processing this single crystal, and then perform heat treatment to eliminate crystal defects in the surface layer of the wafer and to grow oxygen precipitates without generating slip dislocations. With this in mind, it is possible to manufacture annealed wafers with reduced crystal defects in the surface layer of the wafer and without slip dislocations, in which the BMD in the wafer surface is formed uniformly and at high density. The present invention has been completed.

That is, according to the present invention, a silicon single crystal is grown by the Czochralski (CZ) method, the silicon single crystal is processed to produce a silicon wafer, and the produced silicon wafer is subjected to argon gas and hydrogen gas. Alternatively, in a method for producing an annealed wafer by performing high temperature heat treatment for 10 to 600 minutes at a temperature of 1100 to 1350 ° C. in an atmosphere of a mixed gas of these, an oxidation-induced stacking fault (OS) of a silicon single crystal by the Czochralski method is performed.
F) is grown under the condition that the F) is generated on the entire surface of the silicon wafer,
A method for manufacturing an annealed wafer, which comprises performing pre-annealing at a temperature lower than the heat treatment temperature of the high temperature heat treatment on a silicon wafer on which OSF is generated on the entire surface produced by processing the single crystal, and then performing the high temperature heat treatment. Yes,
As a result, crystal defects on the surface layer of the wafer were reduced,
Further, the BMD formed in the bulk is uniformly and densely formed within the wafer surface, and it is possible to provide an annealed wafer in which slip dislocations are further reduced.

The method for manufacturing the annealed wafer of the present invention will be described in detail below. However, the present invention is not limited to these. First, regarding the growth of a silicon single crystal by the CZ method, the conditions for growing a silicon single crystal such that OSFs are generated on the entire surface of the wafer were examined. As the silicon single crystal growing apparatus used for growing the silicon single crystal this time, a conventionally used one as shown in FIG. 4 was used.

As described above, the distribution of crystal defects generated in the single crystal during the growth of the silicon single crystal is as described above between the pulling rate V of the silicon single crystal and the crystal temperature gradient G in the pulling axis direction near the solid-liquid interface. Determined by the relationship V / G. Therefore, the inventors of the present invention grow a silicon single crystal by changing the pulling rate V, slice this single crystal to produce a silicon wafer, and measure the crystal defects generated in the wafer to introduce it at the time of crystal growth. Crystal defects and V /
I investigated the relationship with G. At that time, when the silicon single crystal to be grown is not doped with nitrogen (nitrogen non-doped)
And nitrogen is doped (nitrogen concentration: 1 × 10 ¹³ / c
m ³ and 1 × 10 ¹⁴ / cm ³ ) were measured respectively. The result is shown in FIG.

As shown in FIG. 2, when a silicon single crystal is grown by the CZ method without doping with nitrogen (FIG. 2 (a)), V / G is controlled within the range shown by r. It becomes possible to manufacture a silicon wafer in which OSF is generated on the entire surface of the wafer as shown in the range of R in FIG. For example, when a silicon single crystal is grown by the silicon single crystal growing apparatus used this time, the condition that OSF is generated on the entire surface of the wafer is V of the silicon single crystal.
It was when the / G value was controlled to about 0.2 mm ² / min · ° C. In FIG. 2, NV indicates an N region located on the V-region side where vacancy type point defects are predominant, and NI is an N region located on the I-region side where interstitial silicon is predominant.
The area is shown.

Further, as shown in FIGS. 2B and 2C, when nitrogen is not doped by doping nitrogen when growing a silicon single crystal by the CZ method (FIG. 2).
Compared to (a), since the area where OSF is generated is expanded, it becomes possible to easily and stably grow a silicon single crystal under the condition that OSF is generated on the entire surface of the wafer.
By increasing the concentration of nitrogen to be doped, the region where OSF is generated can be further expanded. For example, when the silicon single crystal is doped with nitrogen at a concentration of 1 × 10 ¹³ / cm ³ using the single crystal growth apparatus shown in FIG. 4, the V / G value of the silicon single crystal is about 0.23 mm ² / min · ° C. It is possible to manufacture a silicon wafer in which OSF is generated on the entire surface of the wafer, and the nitrogen concentration is 1 × 10 ^14.
/ Cm ³ doping, V / G value is 0.4 mm ² / m
A target silicon wafer can be manufactured up to about in ° C.

In the present invention, the condition that the OSF is generated on the entire surface of the wafer includes the case where there is an N region which is unavoidably generated by the outward diffusion of point defects in the outer peripheral portion of the single crystal. Most of the unavoidable N region formed on the outer periphery of the grown single crystal disappears by the cylindrical polishing process for making the diameter of the growing single crystal bar uniform, or the chamfering process of the wafer, and the manufactured silicon wafer has the entire OSF. Can be regarded as a wafer in which

Further, by doping the silicon single crystal with nitrogen in this way, the effect of increasing the generation of oxygen precipitation nuclei in the silicon single crystal can be obtained, while the concentration of nitrogen doped in the silicon single crystal is increased. Is too high, there is a problem that secondary defects such as dislocation clusters occur in the OSF region. If such a secondary defect occurs in the silicon wafer and the defect cannot be eliminated even after the subsequent pre-annealing and high-temperature heat treatment and remains in the surface layer of the annealed wafer, it may cause a decrease in the yield in the subsequent device process. Become. Therefore, the concentration of nitrogen doped when growing a silicon single crystal is 1 × 10 ¹⁴
/ Cm ³ is preferable, and by doing so, the silicon single crystal can be easily grown under the condition that the OSF is generated on the entire surface of the wafer and the generation of oxygen precipitation nuclei in the single crystal is increased. It is possible to suppress the occurrence of secondary defects.

As described above, a silicon single crystal is grown by the CZ method under the condition that OSF is generated on the entire surface of a silicon wafer, and a silicon wafer is produced from this single crystal, whereby crystals other than OSF nuclei are formed in the wafer surface. It is possible to obtain a silicon wafer in which no defects are mixed. In addition, the OS generated on the silicon wafer in this way
Since the F nucleus has a small defect size like a vacancy type crystal defect such as COP generated in the V-rich region, it can be easily eliminated by subsequent high temperature heat treatment.

Next, a silicon wafer having OSF generated on the entire surface thereof is heated at a temperature of 1100 to 1350 ° C. under an atmosphere of argon gas, hydrogen gas, or a mixed gas thereof.
The high temperature heat treatment is performed for up to 600 minutes, but before that, the pre-annealing is performed at a temperature lower than the high temperature heat treatment temperature. As a result, the oxygen precipitates in the wafer can be grown to a size capable of suppressing the growth of slip dislocations by the subsequent high temperature heat treatment without generating or growing slip dislocations on the wafer. After that, by performing the above-mentioned high temperature heat treatment, defects near the wafer surface can be surely eliminated without growing slip dislocations, and since the defect distribution does not coexist, oxygen precipitates in the bulk are removed. It can be grown uniformly on the wafer surface.

The pre-annealing and the high temperature heat treatment may be performed continuously without taking out the wafer from the heat treatment furnace, or the temperature may be lowered once after the pre-annealing and the wafer may be taken out of the furnace and put into the heat treatment furnace again to perform the high temperature heat treatment. You may go.

Further, in the above heat treatment step, pre-annealing at a temperature lower than the high temperature heat treatment temperature is performed in one step for at least 2 hours or more, and then high temperature heat treatment is performed, whereby slip dislocations generated during the heat treatment step can be reliably suppressed. At the same time, the effect of reducing crystal defects on the surface layer of the wafer can be further enhanced.

At this time, if the pre-annealing temperature is lower than 950 ° C., it takes time to grow the oxygen precipitates, which is not efficient, and if it exceeds 1050 ° C., slip dislocations remarkably occur. 950-1
It is preferably 050 ° C.

Further, it is more preferable that the pre-annealing is performed in two steps. First, the size of the oxygen precipitates existing in the wafer is grown to a certain extent in the first annealing (temperature T1), and then the temperature is raised to a temperature higher than the temperature T1. Temperature T
By performing the second annealing at 2, the growth of slip dislocations in the second annealing is surely suppressed, and at the same time, further growth of oxygen precipitates is possible in a short time.
The growth of slip dislocations in the subsequent high temperature heat treatment at 1100 ° C. or more can be sufficiently suppressed, and further the crystal defects of the annealed wafer after the high temperature heat treatment can be further reduced.

At this time, although the slip dislocations do not grow at the heat treatment temperature of 1000 ° C., it takes time to grow the oxygen precipitates, and at the heat treatment temperature of 1050 ° C., the slip dislocations grow at the same time. May grow up. Therefore, the heat treatment temperature of the first annealing is 1000 ° C., and the heat treatment temperature of the second annealing is 105 ° C.
By setting the temperature to 0 ° C., the oxygen precipitates are grown to a size such that slip dislocations do not grow in the second annealing without growing slip dislocations in the first annealing, and then further oxygen precipitates grow in the second annealing. By doing so, oxygen precipitates can be grown in a short time, and crystal defects can be eliminated without growing slip dislocations even in high temperature heat treatment at 1100 ° C. or higher. Therefore, the first annealing temperature T1 is 1000 ° C. and the second annealing temperature T2 is 1
By setting the temperature to 050 ° C., slip dislocations can be efficiently suppressed, oxygen precipitates can be grown in a short time, and the defect density of the annealed wafer can be reduced.

Further, according to the present invention, the pre-annealing is performed not only by holding the temperature lower than the high temperature heat treatment temperature for a certain period of time but also by slowing the temperature rising rate up to the high temperature heat treatment temperature. You can also More specifically, in the conventional heat treatment, the heating rate up to the heat treatment temperature is generally about 5 to 10 ° C./min. However, in the present invention, the heating rate up to the high temperature heat treatment temperature is 3 ° C./min. Pre-annealing can be performed as follows. By slowing the rate of temperature rise to the high temperature heat treatment temperature in this way, oxygen precipitates in the wafer can be formed without growing slip dislocations, as in the case where the temperature is kept below the high temperature heat treatment temperature for a certain period of time. Can be grown to a size that can suppress the growth of slip dislocations by high-temperature heat treatment, and by subsequently performing high-temperature heat treatment, it is possible to eliminate crystal defects near the wafer surface without growing slip dislocations,
Oxygen precipitates in the bulk can be grown further. Furthermore, by performing the pre-annealing at such a slow temperature rising rate, it becomes possible to perform the pre-annealing during the temperature rising process up to the high temperature heat treatment temperature, which leads to a reduction in the heat treatment time as a whole, and thereby the wafer annealing. It is possible to increase the throughput and reduce the manufacturing cost.

In this way, according to the present invention, by manufacturing an annealed wafer by the above method,
Crystal defects on the wafer surface are reduced, and B in the bulk is
It is possible to obtain an annealed wafer having a uniform MD and a high density and a small amount of slip dislocations. Further, with such an annealed wafer, slip dislocations can be surely reduced even with a large diameter wafer having a diameter of 200 mm or more, and the gettering ability is high, so that the gettering ability in the plane of the wafer varies. Therefore, it is possible to obtain a high quality annealed wafer.

[0043]

EXAMPLES The present invention will now be described with reference to Examples and Comparative Examples.
However, the present invention is not limited to these.
Not of. (Examples and Comparative Examples 1 to 3) Single crystal drawing shown in FIG.
Using the lifting device, place the raw material polycrystalline silicon in the quartz crucible.
Charge and put a silicon wafer with a nitride film on it
The pulling speed is 0.65 mm / min (OSF
Area) and 0.85 mm / min (V-rich area)
Set, diameter 200mm, P type, orientation <100>
1 x 10 ^Thirteen/ Cm^ThreeDoped with the concentration (calculated value) of
A silicon single crystal was grown. Then, this single crystal is
After polishing, chamfering, lapping and polishing
I made a ha. One of these mirror-finished wafers
As a result of performing an oxidative heat treatment on the steel, the pulling rate was 0.
Is it a silicon single crystal grown at 65 mm / min?
The silicon wafer manufactured from
Occurred, but the pulling speed was 0.85 mm / m
In the case of a silicon wafer manufactured by setting to in,
-There is a vacancy type crystal defect in the center of the
An OSF ring was generated around Eha.

Next, with respect to both of the above-mentioned mirror-finished wafers, a vertical heat treatment furnace was used in an atmosphere of 100% Ar and the following Table 1 was used.
The heat treatment was performed under each heat treatment condition described in. When the wafer is put into the heat treatment furnace, the temperature of the heat treatment furnace is set to 700
℃, boat speed (entrance speed) 50mm / mi
set to n.

After the high temperature heat treatment, the slip dislocations generated on the surface of the produced annealed wafer were observed by an X-ray topographic image, and those having almost no slip dislocations were ranked as rank 1, and the slip dislocations were most generated. Was designated as Rank 5 and relative evaluation was performed in 5 stages. The measurement results are also summarized in Table 1 below. Further, the oxygen concentration of the produced annealed wafer was measured by the FT-IR method (Fourier transform infrared spectroscopy), and the in-plane distribution of the oxygen precipitation amount ΔOi of the annealed wafer was evaluated. FIG. 3 shows the results of observing the surfaces of the annealed wafers of Examples and Comparative Examples 2 and 3 by X-ray topography and the oxygen precipitation amount ΔOi.
Wafer in-plane distribution (arbitrary unit: arbitrary
unit) is shown.

[0046]

[Table 1]

First, a silicon single crystal is grown under the condition that OSFs are generated on the entire surface of the silicon wafer, and a silicon wafer is produced from the single crystal, followed by preannealing at 1000 ° C. for 2 hours and high temperature heat treatment at 1200 ° C. for 1 hour. As shown in Table 1 above, almost no slip dislocations were observed on the wafer surface of the annealed wafers (Examples) produced and it is understood that the occurrence of slip dislocations was suppressed. Further, as shown in FIG. 3, the oxygen precipitation amount of the annealed wafer is also uniform in the wafer surface,
OPP (Optical Precipitate P
When the BMD density was measured by a rofiler),
A high density of 1 × 10 ⁹ / cm ³ or more was obtained at any position in the plane. In addition, after performing the SC1 cleaning (cleaning with a mixed solution of H ₂ O / H ₂ O ₂ / NH ₄ OH) on the annealed wafer of the example, 0.12 μ existing in the wafer
Surface inspection equipment SP1 (KL
A Tencor Co., Ltd. product name) was used for the measurement. As a result, it was found that the density of crystal defects having a size of 0.12 μm or more present in the annealed wafer was 49 wafers / 200 mmφ wafer, which was extremely small, and the annealed wafer had a good quality.

On the other hand, when a silicon wafer in which OSF was generated on the entire surface of the wafer was subjected to high temperature heat treatment without pre-annealing (Comparative Example 1), slip dislocations were remarkably observed on the surface of the annealed wafer. As a result of measuring the amount of oxygen precipitation ΔOi in the annealed wafer surface, it was found to be uniform in the wafer surface, but the value of ΔOi was small, and it was not possible to obtain sufficient gettering ability. Further, similarly to the example, crystal defects having a size of 0.12 μm or more present in the annealed wafer of comparative example 1 were measured using a surface inspection device SP1 (trade name, manufactured by KLA Tencor Co., Ltd.). As a result, the crystal defect density of 0.12 μm size or more existing in the annealed wafer is 60.
It was larger than the number of pieces / 200 mmφ wafer and the example. From this, the pre-annealed and high-temperature heat-treated annealed wafers manufactured by the present invention (Example)
Is compared with the case where only high temperature heat treatment is performed (Comparative Example 1),
It was also observed that the effect of eliminating crystal defects was excellent.

In Comparative Example 2 and Comparative Example 3 in which the silicon single crystal was grown in the V-rich region, the oxygen precipitation amount ΔOi in the plane of the annealed wafer was measured after the high temperature heat treatment, and as a result, as shown in FIG. It was found that the oxygen precipitation amount in the wafer surface was uneven. Further, in Comparative Example 2, since pre-annealing was not performed, slip dislocations were remarkably observed on the surface of the annealed wafer.

The present invention is not limited to the above embodiment. The above-described embodiment is merely an example, and it has substantially the same configuration as the technical idea described in the scope of claims of the present invention, and has the same operational effect.
Anything is included in the technical scope of the present invention.

For example, in the above embodiment, the case of using argon gas as the atmosphere for the high temperature heat treatment has been taken as an example, but the present invention is exactly the same when the high temperature heat treatment is carried out under hydrogen gas or a mixed atmosphere of hydrogen gas and argon gas. The present invention is also applicable to the heat treatment temperature and heat treatment time within the scope of the present invention.

[0052]

As described above, according to the present invention,
A silicon single crystal is grown by the CZ method under the condition that OSFs are generated on the entire surface of a silicon wafer, and a silicon wafer produced by processing the single crystal is pre-annealed at a temperature lower than the heat treatment temperature of the high temperature heat treatment before the high temperature heat treatment. By doing so, crystal defects on the surface layer of the wafer are reduced, and B
It is possible to provide an annealed wafer in which MD is uniformly and densely present in the wafer surface and slip dislocations are reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a region of an OSF generated on a silicon wafer.

FIG. 2 is a diagram showing a relationship between a crystal defect introduced at the time of growing a single crystal and V / G. (A) In the case of non-doped nitrogen, (b) Nitrogen concentration 1 × 10
^In the case of ¹³ / cm ³ , (c) nitrogen concentration 1 × 10 ¹⁴ / c
In case of m ³ .

FIG. 3 is a diagram showing a result of observing an annealed wafer surface by an X-ray topography and a result of measuring an in-plane distribution of an oxygen precipitation amount ΔOi of the annealed wafer.

FIG. 4 is a schematic view of a single crystal pulling apparatus used in the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Main chamber, 2 ... Pulling chamber, 3 ... Single crystal, 4 ... Silicon melt, 5 ... Quartz crucible, 6 ... Graphite crucible, 7 ... Heating heater, 8 ... Thermal insulation member, 9 ... Gas outlet, 10 ... Gas Inlet port, 11 ... Gas flow straightener, 1
2 ... Heat shield member, 13 ... Upper heat insulating material, 20 ... Single crystal pulling device, R ... OSF generation region of silicon wafer, r ...
V / G area where OSF is generated on the entire surface of the silicon wafer.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4G077 AA02 BA04 CF10 EB01 EH05                       EH09 HA12                 5F004 AA14 AA16 BA19 DA23 DA24                       DB01 EA34

Claims (8)

[Claims] 1. A silicon single crystal is grown by the Czochralski (CZ) method, the silicon single crystal is processed to produce a silicon wafer, and the produced silicon wafer is provided with an argon gas, a hydrogen gas, or a mixture thereof. 10 to 600 at a temperature of 1100 to 1350 ° C. in a mixed gas atmosphere
In the method of manufacturing an annealed wafer by performing a high temperature heat treatment for a minute, a silicon single crystal is grown by the above-mentioned Czochralski method under the condition that an oxidation induced stacking fault (OSF) is generated on the entire surface of the silicon wafer, and the single crystal is processed. A method of manufacturing an annealed wafer, which comprises performing pre-annealing at a temperature lower than the heat treatment temperature of the high temperature heat treatment on a silicon wafer on which OSF is generated on the entire surface, and then performing the high temperature heat treatment. 2. The method for manufacturing an annealed wafer according to claim 1, wherein when the silicon single crystal is grown by the Czochralski method, nitrogen is doped. 3. The method for manufacturing an annealed wafer according to claim 2, wherein the concentration of nitrogen with which the silicon single crystal is doped is less than 1 × 10 ¹⁴ / cm ³ . 4. The method of manufacturing an annealed wafer according to claim 1, wherein the pre-annealing at a temperature lower than the high temperature heat treatment temperature is performed in one step for at least 2 hours or more. . 5. The temperature range of the pre-annealing is 950 to 950.
The method for producing an annealed wafer according to any one of claims 1 to 4, wherein the temperature is 1050 ° C. 6. The pre-annealing is performed in two stages of a first anneal (temperature T1) and a second anneal (temperature T2).
The method for manufacturing an annealed wafer according to any one of claims 1 to 5, wherein 1 <T2. 7. The temperature T1 of the first annealing is 1000.
7. The method for manufacturing an annealed wafer according to claim 6, wherein the temperature T2 of the second annealing is 1050.degree. 8. An annealed wafer manufactured by the method for manufacturing an annealed wafer according to any one of claims 1 to 7.