JP2013048137A - Method for manufacturing silicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon wafer which makes possible: to avoid increasing the size of a thermal treatment device and making the device more complex without reducing the efficiency of growth of a silicon monocrystalline ingot; to suppress the occurrence of slip dislocation during a thermal treatment; to reduce defects including COP and BMD; and to suppress the generation of thermal donors.SOLUTION: The method comprises the steps of: growing a silicon monocrystalline ingot which has a vacancy-rich region and has an oxygen density of 0.8×10atoms/cmor less by CZ (Czochralski) method with nitrogen non-doped; preparing a disk-like wafer including a vacancy-rich region; mirror-polishing a surface of the wafer subjected to a planarization treatment, which makes at least a semiconductor device-forming plane; and performing a first thermal treatment for keeping the wafer at a maximum achieving temperature between 1100°C and 1250°C in an inert gas-containing atmosphere for 30 minutes to 2 hours, and then performing a second thermal treatment for keeping the wafer at a maximum achieving temperature between 1150°C and 1200°C in an oxidizing gas atmosphere for 5 minutes to 10 hours.

Description

The present invention relates to a method for manufacturing a silicon wafer, and in particular, COP (Crystal Originated Particle) or BMD (Balk Micro) of a surface layer portion or a bulk portion of a silicon wafer.
The present invention relates to a silicon wafer manufacturing method capable of improving device characteristics by reducing defects such as defects.

Semiconductor devices are largely divided into integrated circuits (ICs) that integrate multiple electronic components to form a single circuit, and discrete devices that themselves become one electronic component (transistor, diode, thyristor, etc.). Separated.
In either case, a silicon wafer (hereinafter, also simply referred to as a wafer) is mainly used as a substrate material, but in the case of an IC, a portion that becomes a device formation region is a surface layer portion of the substrate (for example, from the surface to a depth of 5 μm). However, in the case of a discrete element, there is a great difference in that the entire thickness direction of the substrate is used.
Therefore, when a silicon wafer is used for a discrete element, it is necessary to reduce defects such as COP and BMD not only in the surface layer portion of the wafer but also in the bulk portion.

  As a method for reducing COP, Patent Document 1 discloses a V / G value (V: pulling speed, G: silicon fusion) when growing a silicon single crystal ingot by the Czochralski method (hereinafter also referred to as CZ method). By controlling the average temperature gradient in the pulling axis direction in the temperature range from the liquid to 1300 ° C., a defect-free region is formed in the entire radial direction of the single crystal, and there is no grown-in defect on the entire surface. A technique for manufacturing a wafer is disclosed.

  Further, as a method of almost erasing defect nuclei introduced at the time of pulling up, Patent Document 2 describes that a grown silicon single crystal ingot is held almost vertically in a heat treatment furnace and is at a temperature of 1150 ° C. or higher and 1400 ° C. or lower. A technique for heating and then cooling to a temperature of 1150 ° C. or lower in the heat treatment furnace is disclosed.

  However, since the technique described in Patent Document 1 needs to be performed while controlling the pulling speed to be low, there is a problem of reducing the growth efficiency of the silicon single crystal ingot. Moreover, since the technique described in Patent Document 2 heat-treats the silicon single crystal ingot itself, there is a problem that the heat treatment apparatus becomes large and complicated.

  In addition, in Patent Document 3, void defects existing in single crystal silicon are eliminated by oxidizing single crystal silicon manufactured by the CZ method and performing heat treatment at a temperature of at least about 1300 ° C. Technology is disclosed.

  Further, Patent Document 4 discloses that a silicon wafer cut out from a silicon single crystal doped with nitrogen is subjected to a heat treatment at a temperature of 1000 ° C. to 1350 ° C. for 50 hours or less in a hydrogen and / or inert gas atmosphere. After removing the defect inner wall oxide film, an oxidation heat treatment is performed for 50 hours or less in a temperature range of 800 ° C. or more and 1350 ° C. or less to forcibly inject interstitial silicon atoms, so that a grown-in defect is at least 10 μm from the surface. A technique for extinguishing is disclosed.

Japanese Patent Laid-Open No. 08-330316 JP 05-319988 A International Publication No. 2003/056621 Pamphlet JP 2000-203999 A

However, since the technique described in Patent Document 3 is heat-treated at a temperature of at least about 1300 ° C., slip dislocation tends to occur.
Furthermore, although the technique described in Patent Document 4 is doped with nitrogen for the purpose of reducing the size of COP and voids, a wafer doped with nitrogen has many as-grown precipitation nuclei of nitrogen in the crystal. Since it is formed, thermal donors are generated with this nitrogen as a nucleus, and there is a problem that the resistance value tends to become unstable.

  The present invention has been made in view of the above-described circumstances, and prevents the enlargement and complication of the heat treatment apparatus without reducing the growth efficiency of the silicon single crystal ingot, and the occurrence of slip dislocation during the heat treatment. It is an object to provide a method for manufacturing a silicon wafer that can suppress defects such as COP and BMD in the surface layer portion and bulk portion of the wafer, and can also suppress the generation of thermal donors. And

A first aspect of the method for producing a silicon wafer according to the present invention is a silicon single crystal having a V-rich region with nitrogen non-doping by a Czochralski method and having an oxygen concentration of 0.8 × 10 ¹⁸ atoms / cm ³ or less. A step of growing an ingot, a step of cutting the silicon single crystal ingot to produce a disk-shaped wafer made of a V-rich region, a step of flattening the front and back surfaces of the produced wafer, and the flattening A step of mirror polishing at least the surface of the wafer subjected to the chemical treatment, which is a semiconductor device forming surface, and the highest surface temperature of 1100 ° C. to 1250 ° C. in an inert gas-containing atmosphere with respect to the mirror-polished wafer, After the first heat treatment for 30 minutes to 2 hours, the maximum temperature of 1150 ° C. to 1200 ° C. in an oxidizing gas atmosphere Characterized in that it comprises the steps of: a second heat treatment for holding at temperature for 5 minutes over 10 hours or less, a.

A second aspect of the method for producing a silicon wafer according to the present invention is a silicon single crystal having a V-rich region with nitrogen non-doping by a Czochralski method and having an oxygen concentration of 0.8 × 10 ¹⁸ atoms / cm ³ or less. A step of growing an ingot, a step of cutting the silicon single crystal ingot to produce a disk-shaped wafer made of a V-rich region, a step of flattening the front and back surfaces of the produced wafer, and the flattening Etching the front and back surfaces of the processed wafer, and the highest temperature reached from 1100 ° C. to 1250 ° C. in an inert gas-containing atmosphere for the etched wafer at 30 minutes to 2 hours After the first heat treatment to be held, in an oxidizing gas atmosphere, at a maximum temperature of 1150 ° C. to 1200 ° C. for 5 minutes to 10 A step of performing a second heat treatment to be held below, a step of removing the oxide film of the heat-treated wafer, a step of mirror-polishing at least a surface of the wafer from which the oxide film has been removed to be a semiconductor device formation surface, It is characterized by providing.

The nitrogen concentration in the grown silicon single crystal ingot is preferably 6.0 × 10 ¹³ atoms / cm ³ or less.

  According to the present invention, without increasing the growth efficiency of the silicon single crystal ingot, the heat treatment apparatus can be prevented from becoming large and complicated, and the occurrence of slip dislocation during the heat treatment can be suppressed, and the surface layer of the wafer There is provided a method for producing a silicon wafer that can reduce defects such as COP and BMD in the portion and bulk portion, and can also suppress the generation of thermal donors.

It is a process flow figure showing a manufacturing method of a silicon wafer concerning a 1st embodiment of the present invention. It is a conceptual diagram which shows typically the relationship between V / G value and the point defect distribution in the silicon single crystal ingot grown. It is a conceptual diagram for demonstrating the mechanism in which the COP and BMD of the surface layer part and bulk part of a wafer in the manufacturing method of the silicon wafer which concern on this invention reduce (1st heat processing). It is a conceptual diagram for demonstrating the mechanism in which COP and BMD of the surface layer part and bulk part of a wafer reduce in the manufacturing method of the silicon wafer which concerns on this invention (2nd heat processing). It is a process flow figure showing a manufacturing method of a silicon wafer concerning a 2nd embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 is a process flow diagram showing a method for manufacturing a silicon wafer according to the first embodiment of the present invention.
As shown in FIG. 1, the silicon wafer manufacturing method according to this embodiment includes a pulling process (S101), a slicing process (S102), a planarization process (S103), a mirror polishing process (S104), and a heat treatment process (S105). ).

In the pulling step (S101), a silicon single crystal ingot having an oxygen concentration of 0.8 × 10 ¹⁸ atoms / cm ³ or less in a nitrogen non-doped nitrogen-doped region is grown by CZ method.
Specifically, using a known single crystal pulling apparatus, the seed crystal is brought into contact with the liquid surface of the silicon melt with nitrogen non-doping, and the seed crystal is pulled up while rotating the seed crystal and the quartz crucible, thereby causing a neck portion. And after forming a diameter-expanded portion that expands to a desired diameter, a V / G value (V: pulling speed, G: from the melting point of silicon to 1300 ° C. so as to be a V-rich region while maintaining the desired diameter. The straight body portion is formed by controlling the average value of the temperature gradient in the crystal in the pulling axis direction in the temperature range to a predetermined value (for example, 0.25 to 0.35 mm ² / ° C./min), and then the desired diameter This is performed by forming a reduced diameter part that is reduced in diameter from the silicon melt and separating it from the silicon melt.
The term “nitrogen non-doped” as used in the present invention means intentionally nitrogen doping (for example, simultaneously loading silicon wafer pieces on which a nitride film is formed when loading polysilicon into a quartz crucible) during the growth of a silicon single crystal ingot. It means not to do.
The oxygen concentration of the silicon single crystal ingot to be grown can be adjusted by adjusting the number of revolutions of the quartz crucible, the furnace pressure, the heater temperature, and the like.

FIG. 2 is a conceptual diagram schematically showing the relationship between the V / G value and the point defect distribution in the grown silicon single crystal ingot.
As shown in FIG. 2, after the neck portion 2 is formed, when the pulling speed V value of the silicon single crystal ingot 1 is gradually decreased from the enlarged diameter portion 3 side to the reduced diameter portion 4 side, the V / G value also decreases. Along with this, the defect distribution in the silicon single crystal ingot 1 also changes. In this case, the G value hardly changes.
When the pulling speed V value is large, that is, when the V / G value is large, the V-rich region 5 in which many atomic vacancies (COP) are taken in is formed. Below the critical V / G value at which the V-rich region 5 disappears, first, oxidation-induced stacking defects (Oxidation-induced Stacking)
A ring OSF region 6 in which a fault (hereinafter abbreviated as OSF) is generated in a ring shape is formed. Next, due to the balance between the vacancies and the interstitial silicon concentration, a defect-free region 7 with a shortage of atoms and few extras is formed. It is formed. When the V / G value further decreases, an I-rich region 8 in which a large amount of interstitial silicon is taken in is formed.

Thus, in the present invention, in order to grow a silicon single crystal ingot having a straight body portion including a V-rich region by controlling the V / G value, rather than growing a silicon single crystal ingot consisting of a defect-free region, The pulling speed V value can be increased. Therefore, a silicon single crystal ingot can be grown without reducing the growth efficiency.
Moreover, since the silicon single crystal ingot is grown by nitrogen non-doping, generation of nitrogen as-grown precipitation nuclei can be suppressed. Therefore, the generation of thermal donors with nitrogen as a nucleus can be suppressed.
Even when the silicon single crystal ingot is grown by nitrogen doping, it is possible to outwardly diffuse nitrogen in the surface layer portion of the wafer by providing a heat treatment step later. However, even in this case, nitrogen in the bulk portion inside the wafer is hardly diffused outward, and therefore remains in the bulk portion even after the heat treatment. Therefore, it is preferable to grow the silicon single crystal ingot by nitrogen non-doping.

In the slicing step (S102), the silicon single crystal ingot is cut using a known cutting device (wire saw or the like) to produce a disk-shaped wafer made of a V-rich region.
Here, “consisting of a V-rich region” does not exclude the above-described ring OSF region, but includes a case where both the V-rich region and the ring OSF region are included.

  In the flattening process (S103), the front and back surfaces of the produced wafer are flattened using a known flattening apparatus (lapping apparatus, grinding apparatus, etc.).

  In the mirror polishing step (S104), at least a surface to be a semiconductor device forming surface of the planarized wafer is mirror-polished using a known polishing apparatus.

  In the heat treatment step (S105), using a well-known heat treatment apparatus (vertical heat treatment apparatus or the like), the wafer that has been mirror-polished is subjected to a maximum attained temperature of 1100 ° C. or higher and 1250 ° C. or lower in an inert gas-containing atmosphere. The first heat treatment is performed for 30 minutes to 2 hours, and then the second heat treatment is performed in an oxidizing gas atmosphere at a maximum temperature of 1150 ° C. to 1200 ° C. for 5 minutes to 10 hours.

  3 and 4 are conceptual diagrams for explaining a mechanism for reducing COP and BMD in the surface layer portion and bulk portion of the wafer in the method for producing a silicon wafer according to the present invention, and FIG. 3 shows the first heat treatment. (A) is COP, (b) is BMD), FIG. 4 shows the reduction mechanism ((a) is COP, (b) is BMD) in the second heat treatment.

A mechanism for reducing COP and BMD in the method for producing a silicon wafer according to the present invention will be described with reference to FIGS.
In the method for producing a silicon wafer according to the present invention, first, the first heat treatment at the maximum temperature and holding time is performed in an inert gas-containing atmosphere. And then inwardly diffused into the bulk portion of the wafer. Accordingly, since the oxygen concentration in the surface layer portion decreases, the inner wall oxide film of COP existing in the surface layer portion is dissolved, and a COP from which the inner wall oxide film has been removed (hereinafter referred to as void) is formed. Thereafter, this void is considered to disappear due to rearrangement of silicon atoms (FIG. 3A, surface layer portion).
As described above, since the silicon single crystal ingot having a low oxygen concentration (0.8 × 10 ¹⁸ atoms / cm ³ or less) is used in the bulk portion, the inner wall of the COP existing in the bulk portion is used. It is considered that the oxide film also dissolves and voids are formed. However, the amount of interstitial Si consumed by rearrangement is limited, and it is preferentially consumed by COP annihilation in the surface layer part where early rearrangement occurs, so it is considered that voids in the bulk remain (see FIG. 3 (a) bulk part).

In addition, as described above, the BMD nucleus generated during the growth of the silicon single crystal ingot is dissolved in the wafer and disappears in the surface layer portion because the oxygen concentration decreases due to the outward diffusion of oxygen from the wafer surface. It can be considered (FIG. 3 (b) surface layer part). In the bulk portion, unlike the surface layer portion, oxygen is not easily diffused outward, and further, oxygen concentration from the surface layer portion is also difficult, so that the oxygen concentration is unlikely to decrease. Therefore, it is considered that BMD nuclei existing in the bulk part remain. However, as described above, since the oxygen concentration is low (0.8 × 10 ¹⁸ atoms / cm ³ or less), even if there is inward diffusion of oxygen from the surface portion of the wafer, precipitation and growth of BMD nuclei. Is considered to be very small (FIG. 3 (b) bulk part).

In the second heat treatment at the maximum temperature and holding time, since heat treatment is performed in an oxidizing gas atmosphere, a large amount of interstitial silicon (referred to as “i-Si” in the figure) is implanted into the surface layer portion of the wafer. Is done. The injected interstitial silicon diffuses to the bulk part and is injected into voids existing in the bulk part. Therefore, it is considered that the void remaining in the first heat treatment disappears in the second heat treatment (FIG. 4A).
Further, as described above, the BMD nuclei in the bulk part remaining in the first heat treatment have a low oxygen concentration (0.8 × 10 ¹⁸ atoms / cm ³ or less) in the wafer, and the first heat treatment is performed. Since the precipitation or growth of the BMD nuclei is very small, it is considered that the BMD nuclei dissolve and disappear in the wafer in the second heat treatment (FIG. 4B).
As described above, by performing the first and second heat treatments, defects such as COP and BMD can be reduced also in the surface layer portion and the bulk portion of the wafer.

In addition, since the silicon wafer manufacturing method according to the present invention performs heat treatment on a wafer obtained by cutting a silicon single crystal ingot, a currently known heat treatment apparatus can be used, so that the heat treatment apparatus is increased in size and complexity. Can be prevented. Furthermore, since the maximum temperature reached in the first heat treatment is 1100 ° C. or higher and 1250 ° C. or lower, and the maximum temperature reached in the second heat treatment is 1150 ° C. or higher and 1200 ° C. or lower, the heat treatment is performed more than in the vicinity of 1300 ° C. The occurrence of slip dislocations in can be suppressed.
Furthermore, the heat treatment member that holds the wafer used during the heat treatment is not limited to SiC, and a Si boat or the like can also be used. Therefore, impurity contamination during heat treatment can be suppressed. In addition, even if it uses a SiC boat, impurity contamination can be suppressed rather than performing in 1300 degreeC vicinity.

When the oxygen concentration in the silicon single crystal ingot exceeds 0.8 × 10 ¹⁸ atoms / cm ³ , the oxygen concentration in the bulk portion of the wafer becomes high, so that it exists in the bulk portion in the first heat treatment. The inner wall oxide film of COP becomes difficult to dissolve, and after the first heat treatment, COP remains in the bulk portion in the state where the inner wall oxide film exists. Also in the subsequent second heat treatment, the oxygen concentration is high in the bulk portion, so that the inner wall oxide film of the COP cannot be completely dissolved, and COP remains in the bulk portion even after the second heat treatment.
Further, in the BMD, since the oxygen concentration of the wafer becomes high, the precipitation and growth of BMD nuclei in the bulk part are promoted in the first heat treatment, and the size and density of the BMD nuclei in the bulk part are increased after the first heat treatment. Increase greatly. In addition, since the oxygen concentration in the bulk portion is high and the size and density of BMD nuclei are increased by the first heat treatment, it is difficult to eliminate the BMD nuclei by dissolution even when the second heat treatment is performed.
As described above, when the oxygen concentration in the silicon single crystal ingot exceeds 0.8 × 10 ¹⁸ atoms / cm ³ , COP and BMD remain in the bulk portion of the wafer, which is not preferable.

When the maximum temperature reached in the first heat treatment is less than 1100 ° C., the temperature is low, so that the inner wall oxide film of the COP and BMD nuclei are less likely to be dissolved. In this case, COP and BMD remain. If the maximum temperature exceeds 1250 ° C., the temperature becomes high, and it is difficult to suppress the occurrence of slip dislocation.
When the maximum temperature reached in the second heat treatment is lower than 1150 ° C., it is difficult to dissolve BMD nuclei remaining in the bulk portion of the wafer because the temperature is low. If the maximum temperature exceeds 1200 ° C., the temperature becomes high, and it is difficult to suppress the occurrence of slip dislocation.

In the case where the holding time of the maximum temperature reached in the first heat treatment is less than 30 minutes, the heat treatment time is short, and it may be difficult to sufficiently dissolve and extinguish the COP inner wall oxide film. When the holding time exceeds 2 hours, productivity is lowered, slip dislocation is likely to occur, and other problems such as impurity contamination may occur.
In the case where the retention time of the maximum temperature reached in the second heat treatment is less than 5 minutes, it may be difficult to eliminate the COP and BMD nuclei because the heat treatment time is short. When the holding time exceeds 10 hours, productivity decreases and slip dislocation is likely to occur, and other problems such as impurity contamination may occur.

When the first heat treatment is performed in an oxidizing gas atmosphere, oxygen diffuses inward into the surface layer portion of the wafer, so that the oxygen concentration in the surface layer portion increases. Therefore, it is difficult to dissolve the inner wall oxide film of COP existing in the surface layer portion in the first heat treatment. The same applies to the second heat treatment.
Therefore, it is difficult to reduce the COP of the surface layer portion after the second heat treatment. When the first heat treatment is performed in a hydrogen gas atmosphere, substantially the same effect as the inert gas-containing atmosphere as described above can be obtained. However, since the second heat treatment is performed in an oxidizing gas atmosphere, when the first heat treatment and the second heat treatment are continuously performed in the same heat treatment apparatus, hydrogen gas is used at the time of switching. And an oxidizing gas atmosphere, which is not preferable because there is a risk of explosion.
When the first heat treatment is performed in a nitrogen gas atmosphere, a nitride film may be formed on the surface of the wafer after the first heat treatment, and it is necessary to newly increase the number of steps for removing the nitride film. Yes, productivity may be reduced.

When the second heat treatment is performed in an inert gas or hydrogen gas atmosphere, oxygen inward diffusion from the surface layer portion to the bulk portion is promoted, so that BMD nuclei remaining in the bulk portion of the wafer are dissolved. It is difficult.
In this case, oxygen in the surface layer portion is further diffused outward in the second heat treatment, so that the oxygen concentration in the surface layer portion is greatly reduced, and the pinning force against slip dislocation of oxygen is reduced. Therefore, slip dislocation is likely to occur in the subsequent heat treatment for forming a semiconductor device.
In addition, when the second heat treatment is performed in a nitrogen gas atmosphere, a nitride film may be formed on the surface of the wafer as described above, and productivity is reduced.

The nitrogen concentration in the grown silicon single crystal ingot is preferably 6.0 × 10 ¹³ atoms / cm ³ or less. By setting it as such a nitrogen concentration range, generation | occurrence | production of a thermal donor can be suppressed reliably.

  Argon gas is suitably used as the inert gas-containing atmosphere in the first heat treatment. The partial pressure of the inert gas in the inert gas-containing atmosphere of the first heat treatment is preferably 95% or more and 100% or less. As described above, it is preferable to set the gas other than the inert gas (for example, oxygen gas or nitrogen gas) to less than 5% because the above-described effects can be obtained with certainty.

The partial pressure of oxygen gas in the oxidizing gas atmosphere of the second heat treatment is preferably 1% or more and 100% or less. When the oxygen partial pressure is less than 1%, the generation amount of interstitial silicon implanted into the surface of the wafer is lowered, and therefore, COP defects in the bulk portion are sufficiently reduced in the second heat treatment. May not be possible.
Argon gas is preferably used as the gas other than oxygen gas in the oxidizing gas. In this manner, by using argon gas as a gas other than oxygen gas, the second heat treatment can be performed without causing formation of other films such as a nitride film or chemical reaction.

The flattening process (S103) described above includes a known lapping process and double-sided grinding process. The mirror polishing process (S104) includes a well-known double-side polishing process.
That is, the flattening process (S103) in the present embodiment may be a process in which double-side grinding is performed after lapping the front and back surfaces of the wafer cut in the slicing process (S102), and the lapping is not performed. It may be a step of performing a double-side grinding process. In this case, the mirror polishing step (S104) is preferably performed on both sides.
Further, an etching process (described later) may be provided between the planarization process (S103) and the mirror polishing process (S104).
That is, the front and back surfaces of the wafer cut in the slicing step (S102) may be planarized, followed by etching, and mirror polishing may be performed on the etched wafer.

(Second Embodiment)
FIG. 5 is a process flow diagram showing a method for manufacturing a silicon wafer according to the second embodiment of the present invention.
As shown in FIG. 5, the silicon wafer manufacturing method according to the present embodiment includes a pulling process (S201), a slicing process (S202), a planarization process (S203), an etching process (S204), and a heat treatment process (S205). ), An oxide film removing step (S206), and a mirror polishing step (S207).
In the pulling process (S201), the slicing process (S202), and the flattening process (S203), the pulling process (S101), the slicing process (S102), and the flattening process (S103) described in the first embodiment. ), The description is omitted.

In the etching process (S204), the front and back surfaces of the planarized wafer are etched using a known etching apparatus. Specifically, the planarized wafer in an acid etching solution in which hydrofluoric acid (HF), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), and water (H ₂ O) are mixed at a certain ratio. Immerse the entire surface.

In the heat treatment step (S205), using a well-known heat treatment apparatus (vertical heat treatment apparatus or the like), the etched wafer is subjected to a maximum attained temperature of 1100 ° C. or higher and 1250 ° C. or lower in an inert gas-containing atmosphere. The first heat treatment is performed for 30 minutes to 2 hours, and then the second heat treatment is performed in an oxidizing gas atmosphere at a maximum temperature of 1150 ° C. to 1200 ° C. for 5 minutes to 10 hours.
Note that the configuration and effects of the gas atmosphere, the maximum temperature reached, the holding time thereof, and the like in this step are the same as those described in the first embodiment, and thus description thereof is omitted.

In the oxide film removing step (S206), the oxide film of the heat-treated wafer is removed using a known cleaning device or etching device. Specifically, it is performed by bringing at least a surface to be a semiconductor device formation surface of the heat-treated wafer into contact with a hydrofluoric acid solution (HF) or a buffered HF solution (NH ₄ F + HF). In the mirror polishing step (S207), at least the surface of the wafer from which the oxide film has been removed is mirror-polished using a known polishing apparatus.

That is, in the method for manufacturing a silicon wafer according to the present embodiment, the heat treatment step (S105) described in the first embodiment is performed after the etching process and before the mirror polishing.
By adopting such a method, it is possible to enhance the effect of oxygen out-diffusion in the first heat treatment and the effect of interstitial silicon implantation in the second heat treatment. That is, since the surface of the wafer after the etching process has a surface roughness larger than that after the mirror polishing, the contact area with the gas atmosphere at the time of the heat treatment is increased, so that the above-described effect can be enhanced.
Therefore, the effect of reducing defects such as COP and BMD in the surface layer portion and bulk portion of the wafer can be enhanced.

  In the case where the heat treatment step (S205) is performed after the flattening treatment step (S203) and before the etching treatment step (S204), the surface roughness of the wafer can be further increased (flattening treatment step ( S203) is a lapping process), but it is not preferable because of problems such as metal impurities from the viewpoint of cleanliness. The same applies to the case where it is performed after the slicing step (S202) and before the flattening step (S203).

EXAMPLES Hereinafter, although this invention is demonstrated further more concretely based on an Example, this invention is not limitedly interpreted by the following Example.
(Test 1: Examples 1-2, Comparative Examples 1-2)
Samples were prepared based on the process flow diagram shown in FIG.
Specifically, the V / G value (V: pulling speed, G: temperature range from the melting point of silicon to 1300 ° C.) is adjusted by adjusting the rotation speed of the quartz crucible and the pressure in the furnace and non-nitrogen doping by the CZ method. (Average value of temperature gradient in crystal) is controlled to 0.28 to 0.32 mm ² / ° C./min, and the straight body portion has a V-rich region, N-type, plane orientation (100), oxygen concentration 0. After growing a silicon single crystal ingot that is 8 × 10 ¹⁸ atoms / cm ³ (old-ASTM), the straight body portion of the ingot is cut and the nitrogen concentration of the V-rich region is 6.0 × 10 ¹³ / cm. ^A disk-shaped slice wafer having a diameter of ³ or less and having a diameter of 200 mm was obtained.
The oxygen concentration and nitrogen concentration are average concentrations from the surface on the device forming surface side of the wafer measured using a secondary ion mass spectrometer (SIMS) to a depth of 1 μm (the same applies hereinafter).

(Test 2: Examples 3-4, Comparative Examples 3-4)
The oxygen concentration was controlled by the CZ method, and the other conditions were the same as in Test 1, except that the oxygen concentration was 0.4 × 10 ¹⁸ atoms / cm ³ (old-ASTM) and the nitrogen concentration was 6.0 × 10 ¹³ / A disc-shaped slice wafer having a diameter of 200 mm that is ³ cm ³ or less was obtained.

(Test 3: Comparative Examples 5 to 8)
The oxygen concentration was controlled by the CZ method, and the other conditions were the same as in Test 1, except that the oxygen concentration was 1.2 × 10 ¹⁸ atoms / cm ³ (old-ASTM) and the nitrogen concentration was 6.0 × 10 ¹³ / A disc-shaped slice wafer having a diameter of 200 mm that is ³ cm ³ or less was obtained.

(Test 4: Comparative Examples 9-12)
Nitrogen was doped by the CZ method, and the other conditions were the same as in Test 1, except that the oxygen concentration was 0.8 × 10 ¹⁸ atoms / cm ³ (old-ASTM) and the nitrogen concentration was 1.0 × 10 ¹⁵ / cm. ³ , a disc-shaped slice wafer having a diameter of 200 mm was obtained.

Next, the sliced wafers obtained in Tests 1 to 4 were lapped and double-sided, and then double-side polished. Next, a first heat treatment is performed on the double-side polished wafer in a 100% argon gas atmosphere at a maximum temperature of 1200 ° C. for 60 minutes, and then the maximum temperature in oxygen 100% gas is changed. The second heat treatment was performed for 60 minutes.
In each heat treatment, 10 wafers were held on a silicon boat, which is a vertical boat.

The obtained heat-treated wafer was subjected to HF treatment, and after removing the front and back oxide films, the defect density on the surface to be the semiconductor device forming surface was evaluated. Furthermore, after evaluating the defect density of the surface, the surface was polished to evaluate the defect density of the bulk portion at a depth of 50 μm and 100 μm from the surface.
These defect densities were evaluated by detecting the number of defects in a region from the measurement surface to a depth of 5 μm using a LSTD scanner MO601 manufactured by Raytex.
Moreover, the slip length which generate | occur | produces on a wafer back surface with respect to the wafer after oxide film removal was evaluated by X-ray topography (Rigaku Co., Ltd. XRT300), and the average value of the slip length in 10 sheets was calculated.
In addition, the wafer surface after the oxide film removal was subjected to two-stage heat treatment (heat treatment at 780 ° C. for 3 hours, then heat treatment at 1000 ° C. for 16 hours), and the BMD density at a depth of 50 μm and 100 μm as IR It was evaluated by tomography (MO-411 manufactured by Raytex Co., Ltd.).
Further, the wafer after the oxide film was removed was subjected to low-temperature heat treatment at 450 ° C. for 1 hour, and the change in the resistivity of the wafer before and after the heat treatment (presence of occurrence of thermal donor) was evaluated. In this evaluation, when the change in resistivity before and after the heat treatment was less than 5%, it was “No”, and when it exceeded 5%, it was “Yes”.
Table 1 shows test conditions and evaluation results in this test.

As can be seen from Table 1, when nitrogen is non-doped, the oxygen concentration is 0.8 × 10 ¹⁸ atoms / cm ³ or less, and the maximum temperature reached in the second heat treatment is 1150 ° C. to 1200 ° C. In Examples 1 to 4, it is recognized that the defect density, BMD density, and slip length are low, and there is no change in resistivity. In the case where the maximum temperature reached by the second heat treatment is 1100 ° C. (Comparative Examples 1 and 3), the effect of reducing the defect density and BMD density in the bulk portion (depth 50 μm, 100 μm) is low (particularly BMD Density). Further, when the maximum temperature reached in the second heat treatment is 1250 ° C. (Comparative Examples 2 and 4), it is recognized that the slip length becomes long. In addition, when the oxygen concentration is 1.2 × 10 ¹⁸ atoms / cm ³ (Comparative Examples 5 to 8), it is recognized that the defect density and the BMD density are increased. Furthermore, when nitrogen doping is performed (Comparative Examples 9 to 12), it is recognized that there is a change in resistivity.

(Test 5)
The second heat treatment was performed under the same conditions as in Examples 1 to 4 except that the highest temperature of the first heat treatment was 1100 ° C.
After removing the oxide films on the front and back surfaces of the obtained heat-treated wafer, the surface and bulk part defect density, slip length, BMD density, and resistivity were evaluated in the same manner as in Test 1.
The results are shown in Table 2.

  As can be seen from Table 2, even when the maximum temperature of the first heat treatment is 1100 ° C. (Examples 5 to 8), the defect density, the BMD density, the slip length are low, and the resistivity does not change. It is recognized that

(Test 6)
The second heat treatment was performed under the same conditions as in Examples 1 to 4 except that the maximum temperature of the first heat treatment was 1000 ° C.
After removing the oxide films on the front and back surfaces of the obtained heat-treated wafer, the surface and bulk part defect density, slip length, BMD density, and resistivity were evaluated in the same manner as in Test 1.
The results are shown in Table 3.

  As can be seen from Table 3, when the maximum temperature of the first heat treatment is 1000 ° C. (Comparative Examples 13 to 16), it is recognized that both the surface and the bulk part have a high defect density.

(Test 7)
The second heat treatment was performed under the same conditions as in Examples 1 to 4 except that the highest temperature of the first heat treatment was 1300 ° C.
After removing the oxide films on the front and back surfaces of the obtained heat-treated wafer, the surface and bulk part defect density, slip length, BMD density, and resistivity were evaluated in the same manner as in Test 1.
The results are shown in Table 4.

  As can be seen from Table 4, it is recognized that the slip length increases when the maximum temperature reached in the first heat treatment is 1300 ° C. (Comparative Examples 17 to 20).

(Test 8)
A sample was prepared based on the process flow diagram shown in FIG. Specifically, the V / G value (V: pulling speed, G: temperature range from the melting point of silicon to 1300 ° C.) is adjusted by adjusting the rotation speed of the quartz crucible and the pressure in the furnace and non-nitrogen doping by the CZ method. (Average value of temperature gradient in crystal) is controlled to 0.28 to 0.32 mm ² / ° C./min, and the straight body portion has a V-rich region, N-type, plane orientation (100), oxygen concentration 0. After growing a silicon single crystal ingot that is 8 × 10 ¹⁸ atoms / cm ³ (old-ASTM), the straight body portion of the ingot is cut and the nitrogen concentration of the V-rich region is 6.0 × 10 ¹³ / cm. ^A disk-shaped slice wafer having a diameter of ³ or less and having a diameter of 200 mm was obtained. Further, a circle having a diameter of 200 mm having a V-rich region having an oxygen concentration of 0.4 × 10 ¹⁸ atoms / cm ³ (old-ASTM) and a nitrogen concentration of 6.0 × 10 ¹³ / cm ³ or less by a similar method. A plate-shaped slice wafer was obtained.

The resulting slice wafer was lapped and double-sided, and the front and back surfaces of the wafer were flattened, and then hydrofluoric acid (concentration 49%): nitric acid (concentration 69%): acetic acid: water = The wafer was dipped in an acid etching solution of 1: 15: 3: 1 to etch the front and back surfaces of the wafer.
Thereafter, the etched wafer is subjected to a first heat treatment that is held for 60 minutes at a maximum temperature of 1200 ° C. in an atmosphere of 100% argon, and then the maximum temperature of 1150 ° C. in 100% oxygen gas. The second heat treatment was performed by holding for 60 minutes at two conditions of 1200 ° C.
The resulting heat-treated wafer was subjected to HF treatment to remove the front and back oxide films, and then subjected to double-side polishing (polishing allowance (single side): about 20 μm).
Similar to Test 1, the obtained wafer was evaluated for changes in surface and bulk defect density, slip length, BMD density, and resistivity.
The results are shown in Table 5.

  As can be seen from Table 5, when the process flow shown in FIG. 5 is performed, it is recognized that the defect density tends to be improved compared to the process flow shown in FIG.

DESCRIPTION OF SYMBOLS 1 Silicon single crystal ingot 2 Neck part 3 Expanded diameter part 4 Reduced diameter part 5 V-rich area 6 Ring OSF area 7 Defect-free area 8 I-rich area

Claims (3)

A step of growing a silicon single crystal ingot having an oxygen concentration of 0.8 × 10 ¹⁸ atoms / cm ³ or less in a nitrogen non-doped V-rich region by Czochralski method;
Cutting the silicon single crystal ingot to produce a disk-shaped wafer comprising a V-rich region;
A step of planarizing the front and back surfaces of the produced wafer;
A step of mirror polishing at least a surface of the planarized wafer to be a semiconductor device forming surface;
The mirror-polished wafer is subjected to a first heat treatment in an inert gas-containing atmosphere at a maximum attained temperature of 1100 ° C. to 1250 ° C. for 30 minutes to 2 hours, and then in an oxidizing gas atmosphere A step of performing a second heat treatment for holding at a maximum attained temperature of 1150 ° C. or higher and 1200 ° C. or lower for 5 minutes to 10 hours;
A method for producing a silicon wafer, comprising: A step of growing a silicon single crystal ingot having an oxygen concentration of 0.8 × 10 ¹⁸ atoms / cm ³ or less in a nitrogen non-doped V-rich region by Czochralski method;
Cutting the silicon single crystal ingot to produce a disk-shaped wafer comprising a V-rich region;
A step of planarizing the front and back surfaces of the produced wafer;
Etching the front and back surfaces of the planarized wafer;
A first heat treatment is performed on the etched wafer in an inert gas-containing atmosphere at a maximum attained temperature of 1100 ° C. to 1250 ° C. for 30 minutes to 2 hours, and then in an oxidizing gas atmosphere. A step of performing a second heat treatment for holding at a maximum attained temperature of 1150 ° C. or higher and 1200 ° C. or lower for 5 minutes to 10 hours;
Removing the oxide film of the heat-treated wafer;
A step of mirror-polishing a surface to be at least a semiconductor device forming surface of the wafer from which the oxide film has been removed;
A method for producing a silicon wafer, comprising: ^{3. The} method for producing a silicon wafer according to claim 1, wherein a nitrogen concentration in the grown silicon single crystal ingot is 6.0 × 10 ¹³ atoms / cm ³ or less. 4.

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