JP2011222842A - Manufacturing method for epitaxial wafer, epitaxial wafer, and manufacturing method for imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for an epitaxial wafer that can form a silicon epitaxial layer substantially without defect, an epitaxial wafer manufactured by the method, and a manufacturing method for an imaging device.SOLUTION: The manufacturing method for an epitaxial wafer comprises: RIE elimination step of eliminating defects that are detected by the RIE method and measurable in an area up to at least 0.5 μm depth from the surface of the silicon substrate, by applying rapid heat treatment to the silicon substrate; and a step of forming the silicon epitaxial layer on the surface of the silicon substrate where defects having been detected by the RIE method are eliminated.

Description

  The present invention relates to an epitaxial wafer manufacturing method for forming an epitaxial layer on a silicon substrate, an epitaxial wafer manufactured by the method, and an imaging device manufacturing method.

2. Description of the Related Art With the recent increase in integration and performance of semiconductor elements, it has become important to reduce crystal defects in semiconductors, particularly crystal defects on and near the surface. For this reason, the demand of the epitaxial wafer which formed the epitaxial layer excellent in crystallinity on the silicon substrate is increasing year by year.
Here, a method for manufacturing an epitaxial wafer will be described by taking single-wafer vapor deposition as an example (see Patent Document 5). FIG. 6 is a schematic view of a general single wafer type vapor phase growth apparatus.

  A vapor phase growth apparatus 100 shown in FIG. 6 includes a susceptor 101 having a counterbore 101a on which a silicon substrate W is placed and a thickness of several millimeters, and a susceptor support member 103 that supports and rotates the susceptor 101 from the lower surface side. A heating device 104 for heating the silicon substrate W, a reaction gas introduction pipe 105 for introducing a reaction gas into the reaction vessel 102, a purge gas introduction pipe 106 for introducing a purge gas provided on the same side, a gas And an exhaust pipe 107 for exhausting the air.

  First, the silicon substrate W is placed on the disc-shaped susceptor 101 in the reaction vessel 102. Hydrogen gas is introduced into the reaction vessel 102 in advance from a reaction gas introduction pipe 105 and a purge gas introduction pipe 106. Next, the silicon substrate W is heated to a predetermined temperature (for example, about 1000 ° C. to 1200 ° C.) by the heating device 104. Next, a gaseous phase etching process in which hydrogen chloride gas is introduced into the silicon substrate W from the reaction gas introduction pipe 105 to perform vapor phase etching of about 0.1 μm to 0.3 μm, or 10% at a predetermined temperature while flowing hydrogen gas. -Perform hydrogen annealing for about 30 seconds. Next, the temperature of the silicon substrate W is set to the growth temperature. Then, a reactive gas (for example, trichlorosilane (TCS) and a carrier gas (for example, hydrogen gas) is supplied from the reactive gas introduction pipe 105, and an epitaxial layer is grown on the silicon substrate W by vapor phase growth (vapor phase growth step). A wafer can be manufactured, and the manufactured epitaxial wafer is cooled to a set temperature (for example, about 700 ° C.) and taken out from the vapor phase growth apparatus 100.

Here, the effect of performing vapor phase etching with hydrogen chloride before growing the epitaxial layer is that the linear shape defects existing on the surface layer of the silicon substrate can be changed into a shape that easily disappears by etching. By performing the step, defects can be buried in the epitaxial layer and disappear so that they are hardly observed. In addition to this, it is known that the occurrence of stacking faults in the epitaxial layer can be suppressed by performing a gas phase etching process.
In this way, in consideration of the case where there are defects that cannot be induced or completely eliminated in the epitaxial layer on the surface layer of the silicon substrate and remain, these defects can be easily removed or the defects can be removed in advance. In order to eliminate this, in the epitaxial growth process, there are two types of processes, that is, the case of performing vapor phase etching with hydrogen chloride gas and the case of performing H ₂ annealing before the epitaxial growth step, both of which are widely adopted in mass production processes. .

  However, as a problem of epitaxial wafer manufacturing, for example, when an epitaxial layer is formed on a silicon substrate having a glow-in defect such as COP, the epitaxial layer has a defect even if the above-described vapor phase etching or the like is performed in advance. It sometimes occurred.

  This grow-in defect is a vacancy-type point defect called interstitial-silicon (vacancy, which may be abbreviated as Va hereinafter) incorporated into a silicon single crystal when a single crystal is grown by the CZ method. Interstitial type silicon point defects called Interstitial-Si (hereinafter sometimes abbreviated as I) are complex defects that become supersaturated during crystal cooling and agglomerate with oxygen. FPD, LSTD, COP, OSF, etc. is there. Further, as a method for evaluating such a glow-in defect, there is an RIE method or the like (see Patent Document 10).

  In explaining these defects, first, what is generally known about the factors that determine the respective concentrations of Va and I taken into the silicon single crystal will be explained.

FIG. 7A is an explanatory diagram showing the relationship between the defect region and the pulling speed of a silicon single crystal ingot grown by the CZ method described in Patent Document 1, and FIG. It is explanatory drawing which shows the in-plane defect distribution of the silicon single crystal wafer cut out.
FIG. 7A shows an average value G (° C.) of the temperature gradient in the crystal in the pulling axis direction in the temperature range from the silicon melting point to 1300 ° C. by changing the pulling rate V (mm / min) during single crystal growth. V / G, which is a ratio to / mm).

  In general, the temperature distribution in a single crystal depends on the structure in the CZ furnace (hereinafter referred to as hot zone (HZ)), and it is known that the distribution hardly changes even if the pulling rate is changed. For this reason, in the case of a CZ furnace having the same structure, V / G corresponds to only a change in pulling speed. That is, the pulling speed V and V / G are approximately directly proportional. Therefore, the pulling speed V is used on the vertical axis of FIG.

As shown in FIG. 7A, in the region where the pulling rate V is relatively high, glow-in defects such as FPD, LSTD, and COP, which are considered to be voids in which the above-described point defects called vacancy, are aggregated, are crystallized. A region having a high density in almost the entire radial direction and having these defects is called a V-rich region.
As the growth rate is decreased, the OSF ring generated in the periphery of the crystal contracts toward the inside of the crystal and eventually disappears. When the growth rate is further slowed down, a neutral (Neutral: hereinafter referred to as “N”) region in which there is little excess or deficiency of Va and I appears. Although this N region has a bias of Va and I but is below the saturation concentration, it does not aggregate and form a glow-in defect.

The N region is divided into an Nv region where Va is dominant and an Ni region where I is dominant. It has been found that a large amount of oxygen precipitates (Bulk Micro Defect, hereinafter referred to as BMD) are generated in the wafer in the Nv region during thermal oxidation treatment, whereas this oxygen precipitate is hardly generated in the wafer in the Ni region.
When the growth rate is further slowed, I becomes supersaturated. As a result, there is a low density of glow-in defects of L / D (Large Dislocation: abbreviations for interstitial dislocation loops, LSEPD, LEPD, etc.) that are considered to be dislocation loops in which I is aggregated. It becomes an area called an I-Rich area.
From these facts, the single crystal pulled up while controlling the growth rate in a range that becomes the N region from the center of the crystal to the entire radial direction is cut and polished so that the entire surface of the wafer becomes an N region. Can be obtained.

  As an example, as shown in FIG. 7B, the entire surface of the wafer cut out from the position AA in FIG. 7A becomes the Nv region. As shown in FIG. 7B, the wafer cut out from the position B-B in FIG. 7A has an Nv region at the center of the wafer and an Ni region at the outer periphery. As shown in FIG. 7B, the entire surface of the wafer cut out from CC in FIG. 7A becomes the Ni region.

  However, even if the silicon epitaxial layer is formed on the silicon substrate cut out from the silicon single crystal ingot in the N region as described above, defects may occur in the epitaxial layer. As a method for suppressing defects in the epitaxial layer, for example, There is a method described in Patent Document 6.

Patent Document 6 describes that when epitaxial growth is performed under normal pressure, the COP disappears on the surface of the epitaxial layer unless the thickness of the epitaxial layer is 2 μm or more. As a countermeasure, in Patent Document 6, when a silicon substrate is heat-treated at 1150 to 1200 ° C. for 1 to 10 minutes in an H ₂ gas atmosphere and then epitaxially grown under normal pressure, 0.4 μm or more, and when epitaxially grown under reduced pressure Reported that by forming an epitaxial layer having a thickness of 4 μm or more, the disappearance of COPs having a size of 130 nm or more can be suppressed to 0.3 pieces / cm ² or less.

  However, at the present time when device miniaturization has progressed, the requirement for defect size is that no defect having a size of 50 nm or less is generated, and the required quality cannot be satisfied. In order to eliminate the disappearance of COP, there is a limitation on the growth conditions because it is necessary to form an epitaxial layer with a certain thickness or more, and the epitaxial growth conditions under reduced pressure are effective unless the pressure is 200 Torr or higher. There is a problem that there is.

  In order to reduce or eliminate such oxygen-related defects such as COP, OSF nuclei, oxygen precipitates, etc. on the silicon substrate surface, it is necessary to make the oxygen concentration below the solid solubility limit. For example, defects can be reduced or eliminated by a method in which the heat treatment is performed at 1150 ° C. or higher using a normal heat treatment furnace and the oxygen concentration in the surface layer is reduced using oxygen out-diffusion to bring it below the solid solution limit. . However, since the heat treatment time is long, the oxygen concentration in the surface layer is remarkably reduced due to the outward diffusion of oxygen, the mechanical strength of the surface layer is also lowered, and slip dislocation is liable to occur during epitaxial growth.

  Another possible method is to perform heat treatment for eliminating or reducing the COP described in Patent Document 6 in an epitaxial furnace, and then performing epitaxial growth continuously. However, even in this case, if the heat treatment is performed for 1 to 10 minutes in the epitaxial growth process, particularly in the case of a single-wafer type vapor phase growth apparatus, the productivity of the epitaxial wafer is remarkably lowered, which causes an increase in production cost. There is also a point.

Further, in Patent Document 7, a series of annealing-epitaxial processes are performed in which an epitaxial layer is continuously formed after isothermal / isobaric heat treatment at a temperature of 1100 ° C. or higher using a silicon substrate having a COP size of 130 nm or less. Thus, it has been reported that the COP shape can be made shallow in the annealing process, and the COP can be filled by epitaxial growth performed continuously thereafter.
However, this is the remaining data of COPs with a size of 120 nm or more. As described above, with the progress of miniaturization of devices, the requirement for defect size is that there is no generation of defects with a size of 50 nm or less. Therefore, the required quality cannot be satisfied. In order to eliminate the disappearance of COP, it is necessary to form an epitaxial layer with a certain thickness or more, which is basically the same as in Patent Document 6, and the COP size of the silicon substrate is 130 nm or less. There is a restriction that it is necessary, and it is a problem.

  The problems of Patent Document 6 and Patent Document 7 are that COP and the like are easily disappeared or reduced by heat treatment before epitaxial growth, and the defects are eliminated by completely annihilating or filling the COP groove during epitaxial growth. Of course, there is a fundamental problem that the epitaxial growth conditions are limited.

  Further, as a general problem of an epitaxial wafer, in addition to the defects on the surface of the silicon substrate, epitaxial growth is normally performed in a hydrogen atmosphere at 1100 ° C. or higher. There is a problem that the necessary BMD cannot be obtained because the oxygen precipitates present therein disappear.

The presence of such BMD in the bulk other than the device active region is effective because it functions as a gettering site for capturing metal impurities mixed during the device process.
In addition, since BMD suppresses the movement of dislocation when the size is small, it is effective to increase the strength of the wafer, that is, the so-called precipitation strengthening effect. However, if the density is too high or the BMD size is too large, Therefore, it is important to control the density and size within an appropriate range according to the device to be used. For this purpose, a technique for accurately controlling the BMD is important.

Recently, as a method for forming BMD in a silicon substrate such as a Ni region where BMD hardly occurs, a method of RTP (Rapid Thermal Process) treatment (hereinafter also referred to as rapid heating / cooling treatment or rapid heat treatment) has been proposed. Has been.
The RTP treatment is performed in an atmosphere of a nitride forming atmosphere gas such as N ₂ or NH ₃ or a mixed gas of these gases and a non-nitride forming atmosphere gas such as Ar or H ₂ , for example, at 50 ° C. / This is a heat treatment method in which the temperature is rapidly increased from room temperature at a temperature increase rate of seconds, heated and held at a temperature of about 1200 ° C. for about several tens of seconds, and then rapidly cooled at a temperature decrease rate of 50 ° C./second.

Here, the mechanism by which BMD is formed by performing oxygen precipitation heat treatment after RTP treatment will be briefly described (see Patent Document 2 and Patent Document 3).
First, in the RTP process, for example, Va is injected from the wafer surface while maintaining a high temperature of 1200 ° C. in an N ₂ atmosphere, and the temperature range of 1200 ° C. to 700 ° C. is cooled at a rate of temperature decrease of 5 ° C./second, for example. , Va redistribution due to diffusion and disappearance of I occurs.

  As a result, Va is unevenly distributed in the bulk. When the wafer in such a state is heat-treated at, for example, 800 ° C., oxygen is rapidly clustered in a high Va concentration region, but oxygen is not clustered in a low Va concentration region.

  Next, when heat treatment is performed at 1000 ° C. for a certain time in this state, for example, clustered oxygen grows to form BMD. As described above, when the oxygen precipitation heat treatment is performed on the silicon substrate after the RTP process, a BMD having a distribution in the wafer depth direction is formed according to the concentration profile of Va formed by the RTP process. Therefore, the desired Va concentration profile is formed on the silicon substrate by controlling the conditions such as the atmosphere, maximum temperature, and holding time of the RTP process, and then the desired DZ is performed by performing the oxygen precipitation heat treatment on the silicon substrate. Wafers with BMD profiles in the width and depth directions can be manufactured.

Patent Document 4 discloses that when RTP treatment is performed in an oxygen gas atmosphere, an oxide film is formed on the surface, so that I is injected into the wafer from the oxide film interface, thereby suppressing BMD formation. Yes.
As described above, the RTP treatment can promote BMD formation or conversely, depending on the atmospheric gas, the maximum holding temperature, and other conditions. In addition, since the RTP process is an extremely short time annealing, oxygen outdiffusion hardly occurs, and the oxygen concentration in the wafer surface layer is hardly lowered.

  Further, Patent Document 8 discloses that a void is newly formed in a silicon substrate by performing a rapid heating / cooling heat treatment (RTP process) for 10 to 30 seconds at a temperature of 1200 ° C. or higher and a melting point or lower. A manufacturing method is disclosed in which it is formed and then epitaxially grown at a temperature of 1170 ° C. or lower and 30 ° C. or lower than the RTP processing temperature.

  Patent Document 8 describes that the difference between the RTP temperature and the epitaxial growth temperature is preferably 65 to 115 ° C. in order to control BMD. For this reason, since Patent Document 8 defines the epitaxial growth temperature as 1170 ° C. or lower, the RTP temperature is 1285 ° C. at the maximum. In fact, the maximum temperature of the RTP process in the example of Patent Document 8 is 1200 ° C. Although this method is certainly effective for forming BMD on an epitaxial wafer, no investigation has been made on glow-in defects such as COP of a silicon substrate for epitaxial growth.

On the other hand, it has been reported that glow-in defects such as COP and OSF disappear due to RTP processing.
For example, in Patent Document 9, COP disappears by RTP treatment at a temperature of 1200 ° C. or higher in a hydrogen gas atmosphere, a DZ layer is formed on the surface layer, and TZDB (Time Zero Dielectric Breakdown) is one of oxide film reliability. It is disclosed that TDDB (Time Dependent Dielectric Breakdown) characteristics, which are dielectric breakdown characteristics over time, which are characteristics and long-term reliability, are improved.

JP 2007-191320 A JP 2001-203210 A Special table 2001-503209 gazette JP 2003-297839 A JP 2003-197547 A Japanese Patent No. 3763629 JP 2001-68420 A Japanese Patent No. 3791446 Japanese Patent Laid-Open No. 10-326790 JP 2000-58509 A JP 2009-249205 A

  However, any of the above methods cannot sufficiently suppress defects having a size of 50 nm or less generated in the silicon epitaxial layer.

  The present invention has been made in view of the above problems, and provides an epitaxial wafer manufacturing method capable of forming a silicon epitaxial layer having almost no defects, an epitaxial wafer manufactured by the method, and an imaging device manufacturing method. The purpose is to do.

  In order to achieve the above object, the present invention is a method of manufacturing an epitaxial wafer by forming a silicon epitaxial layer on the surface of a silicon substrate cut out from a silicon single crystal ingot grown by the Czochralski method. An RIE defect extinguishing step of extinguishing defects detected by an RIE method existing at least in a region from the surface of the silicon substrate to a depth of 0.5 μm by performing rapid thermal processing on the silicon substrate; And a step of forming the silicon epitaxial layer on the surface of the silicon substrate from which defects detected by the method have been eliminated, and a method for producing an epitaxial wafer.

Thus, by performing a rapid heat treatment on the silicon substrate, by performing an RIE defect extinction step of eliminating defects detected by the RIE method existing at least in a region from the surface of the silicon substrate to a depth of 0.5 μm, Even if the surface layer of the silicon substrate is removed by polishing, vapor phase etching or the like, defects are not exposed on the surface of the silicon substrate, and a silicon epitaxial layer having almost no defects is formed in the subsequent steps regardless of growth conditions. be able to. Furthermore, since polishing and vapor phase etching before forming the silicon epitaxial layer can be sufficiently performed, contamination and defects can be further reduced. Moreover, if it is rapid thermal processing, an internal BMD density can be controlled effectively.
As described above, according to the present invention, a high quality epitaxial wafer having a desired BMD density and almost no defects can be manufactured.

At this time, in the RIE defect disappearance step, the rapid thermal treatment is performed at a temperature higher than 1300 ° C. and 1400 ° C. in an atmosphere containing at least one kind of a gas for forming a nitride film and an Ar gas using a rapid heating / rapid cooling device. In the silicon epitaxial layer forming step, the silicon epitaxial layer can be formed at a growth temperature of 1175 ° C. or lower on the surface of the silicon substrate.
As described above, the rapid heat treatment is performed at a temperature higher than 1300 ° C. and lower than 1400 ° C. in an atmosphere containing at least one kind of gas of the nitride film forming atmosphere and Ar gas using a rapid heating / rapid cooling device. By applying for 60 seconds, defects detected by the RIE method existing at least in the region from the surface of the silicon substrate to a depth of 0.5 μm can be surely eliminated, and at the same time, new vacancies are formed inside the silicon substrate. can do. Then, while forming a silicon epitaxial layer having no defect in the silicon epitaxial layer forming step, if the growth temperature is 1175 ° C. or less, the temperature is 125 ° C. or more lower than the rapid thermal processing, and thus the formed new vacancy is an epitaxial layer. Disappearance in the formation process can also be suppressed. As a result, during the device manufacturing process or the like, BMD formation is greatly promoted and the gettering ability can be improved efficiently.

In the RIE defect elimination step, the rapid thermal treatment is performed in an oxygen atmosphere at a temperature higher than 1300 ° C. and lower than 1400 ° C. for 1 to 60 seconds using a rapid heating / rapid cooling device, and in the silicon epitaxial layer forming step, The silicon epitaxial layer can be formed on the surface of the silicon substrate at a growth temperature of 1175 ° C. or lower.
In this way, the rapid heat treatment is performed at a temperature higher than 1300 ° C. and not higher than 1400 ° C. for 1 to 60 seconds using a rapid heating / rapid cooling device to at least a depth of 0.5 μm from the surface of the silicon substrate. Defects detected by the RIE method existing in the previous region can be surely eliminated, and at the same time, new interstitial silicon can be formed inside the silicon substrate. Then, while forming a silicon epitaxial layer having no defect in the silicon epitaxial layer forming step, if the growth temperature is 1175 ° C. or less, the temperature is 125 ° C. or more lower than the rapid heat treatment, and thus the newly formed interstitial silicon is epitaxially formed. Disappearance in the layer forming process can also be suppressed. Thereby, BMD formation can also be suppressed in the device manufacturing process or the like.

At this time, the silicon substrate is preferably a silicon single crystal wafer cut out from a silicon single crystal ingot whose entire surface is an OSF region, the entire surface is an N region, or a region where the OSF region and the N region are mixed.
Thus, if the silicon substrate is a silicon single crystal wafer cut out from a silicon single crystal ingot whose entire surface is an OSF region, the entire surface is an N region, or a region where the OSF region and the N region are mixed, rapid thermal annealing is performed. Defects that exist in deeper regions from the surface of the silicon substrate can be eliminated, and even if polishing, etching, etc. before the formation of the silicon epitaxial layer are sufficiently performed, there is no exposure of defects on the silicon substrate surface, resulting in higher quality An epitaxial wafer can be manufactured.

At this time, it is preferable that the silicon substrate is a silicon single crystal wafer containing oxygen at a concentration equal to or lower than 9 × 10 ¹⁷ atoms / cm ³ (JEIDA: conversion coefficient by Japan Electronics Industry Promotion Association).
In this way, by making the silicon substrate a silicon single crystal wafer containing oxygen at a concentration of 9 × 10 ¹⁷ atoms / cm ³ (JEIDA) or less, the size of the glow-in defect is smaller. Defects can be eliminated.

At this time, the silicon substrate is made of a silicon single substance containing nitrogen having a concentration of 1 × 10 ¹¹ to 1 × 10 ¹⁵ atoms / cm ³ and / or carbon having a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ^3. A crystal wafer is preferable.
In this way, the silicon substrate is made of silicon containing nitrogen at a concentration of 1 × 10 ¹¹ to 1 × 10 ¹⁵ atoms / cm ³ and / or carbon at a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ^3. By setting it as a crystal wafer, the intensity | strength of the silicon epitaxial wafer manufactured can be improved more, and BMD formation promotion can also be performed more efficiently.

Moreover, the epitaxial wafer manufactured by the manufacturing method of the epitaxial wafer of this invention is provided.
If it is the epitaxial wafer manufactured by the manufacturing method of the epitaxial wafer of this invention, it can be set as the high quality epitaxial wafer which has a desired BMD density and has few defects.

Moreover, the imaging device manufacturing method characterized by manufacturing an imaging device using the epitaxial wafer of this invention is provided.
Since the epitaxial wafer of the present invention has almost no defects and has a uniform BMD over the entire wafer, in-plane variation in characteristics of CCD and MOS image sensors can be reduced by using it for manufacturing imaging devices. it can.

  As described above, according to the present invention, a high quality epitaxial wafer having a desired BMD density and almost no defects can be manufactured.

It is a flowchart which shows an example of the embodiment of the manufacturing method of the epitaxial wafer of this invention. It is explanatory drawing which showed the relationship of the result of having evaluated the TDDB characteristic about the temperature at the time of carrying out RTP processing of the silicon single crystal wafer obtained from the pulled silicon single crystal, RTP processing, and the wafer after RTP processing. . The growth rate of silicon single crystal ingot and each defect distribution are shown. It is the schematic which shows a rapid heating and rapid cooling apparatus. It is explanatory drawing for demonstrating the evaluation of the defect by RIE method. 1 is a schematic view of a general single wafer type vapor phase growth apparatus. FIG. FIG. 7 (a) is an explanatory view showing the relationship between the defect region of the silicon single crystal ingot grown by the CZ method and the pulling speed, and FIG. 7 (b) the in-plane defects of the silicon single crystal wafer cut out from the silicon single crystal ingot. It is explanatory drawing which shows distribution. It is the schematic of a single crystal pulling apparatus.

In recent devices, an epitaxial wafer having no oxygen-related glow-in defects or glow-in oxygen precipitates in the device operating region, and appropriately controlled BMD in the bulk deeper than the device operating region is effective.
Therefore, the present inventors considered the prior art, and in order to obtain an epitaxial wafer as described above, conducted extensive research on the relationship between RTP processing, TDDB characteristics, RIE defects, and oxygen concentration on the wafer surface layer. .

First, in Patent Document 2 described above, a method is described in which a silicon substrate is cut out from a single crystal in an N region where Va and I aggregates are not present, and a silicon substrate having an entire N region is subjected to RTP treatment.
In this method, since there is no glow-in defect in the silicon substrate as a material, it can be considered that there is no problem even if the RTP process is performed. However, after preparing the silicon substrate having the entire N region and performing the RTP process, When the TDDB characteristic, which is the long-term reliability of the oxide film, is measured, the TZDB characteristic is hardly lowered in the Nv region of the silicon substrate, but the TDDB characteristic may be lowered (see Patent Document 1).

FIG. 2 shows the pulling speed V of the silicon single crystal described in Patent Document 1, the temperature when the silicon single crystal wafer obtained from the pulled silicon single crystal is RTP processed, and the TDDB characteristics of the wafer after the RTP processing. It is explanatory drawing which showed the relationship of the result ((circle): favorable, (triangle | delta): some fall, x: fall).
As can be seen from FIG. 2, when the pulling speed V is 0.56 mm / min or less, that is, when the entire surface of the wafer shown in FIG. 7A is a Ni region, the wafer is subjected to RTP treatment, and then the TDDB characteristics are evaluated. The TDDB characteristics are good regardless of the RTP treatment temperature.

However, in the case of a wafer cut from a silicon single crystal ingot pulled up at 0.57 mm / min, when the RTP processing temperature is 1190 ° C. or higher, the non-defective product rate of the γ mode, which is an intrinsic failure mode of the oxide film, decreases. It can be seen that it remains lowered even at 1270 ° C.
The wafer corresponds to the wafer BB shown in FIG. 7B, and is a wafer having an Nv region at the center and a Ni region on the outer periphery thereof.

  Here, in the experimental results of Patent Document 1, the TDDB characteristics are deteriorated by the RTP process, whereas in the results disclosed in FIGS. 5 and 6 of Patent Document 9, when the RTP process is performed at a temperature of 1200 ° C. or higher, the TZDB characteristic is reduced. Both the characteristics and the TDDB characteristics are improved and seem to be contradictory.

The difference between Patent Document 1 and Patent Document 9 is that Patent Document 1 uses an Nv region and Ni region mixed wafer and performs RTP treatment in a mixed gas atmosphere of NH ₃ and Ar gas. In the experiment disclosed in Document 9, the TDDB characteristics were evaluated after RTP treatment was performed in hydrogen gas on a wafer in the V-Rich region where COPs, which are glow-in defects, in which vacancies, which are point defects, were agglomerated, were generated. There is in point.

Patent Document 2 discloses that the RTP treatment in a hydrogen gas atmosphere has higher COP decomposability than the RTP treatment in an Ar gas or Ar gas and N ₂ gas mixed atmosphere.
Patent Document 9 also reports that the TZDB and TDDB characteristics are reduced by about 15 to 20% when an oxidation treatment is performed at 1050 ° C. for 30 minutes after the RTP treatment.

Judging from these facts, in Patent Document 9, in the RTP treatment in the H ₂ gas atmosphere, the COP only in the surface or in the extremely shallow region from the surface disappeared, so that the TDDB characteristic was recovered. After the partial oxidation treatment and the formation of the ultrathin oxide film, the oxide film is removed, and when the super shallow region of the surface layer is removed, the TDDB characteristics are deteriorated. That is, the present inventors have found that the COP at the position where the depth is removed by the thickness of the oxide film cannot be completely decomposed.

In the Nv region, glow-in oxygen precipitates exist, that is, RIE defects exist. In the experiment of Patent Document 1, RTP treatment is performed at a temperature of 1270 ° C. or less and in an NH ₃ and Ar mixed atmosphere in which defect decomposition is inferior to H ₂ gas. In this temperature range, glow-in oxygen present in the Nv region It is considered that the TDDB was lowered because the precipitate was not completely dissolved.
From the above, it can be seen that there is no contradiction between Patent Document 1 and Patent Document 9.

  As described above, in the epitaxial growth step, a step of performing vapor phase etching of the surface layer of the silicon substrate by about 0.1 to 0.3 μm with hydrogen chloride gas before the growth of the epitaxial layer is widely adopted. In the method described in Patent Document 9, COP remains within 0.3 μm from the surface layer, which is a problem.

Next, the present inventors diligently studied the relationship between RIE defects and TDDB characteristics.
Here, the RIE method is disclosed in Patent Document 10 as a method for evaluating a minute crystal defect containing silicon oxide (hereinafter referred to as SiOx) in a semiconductor single crystal substrate while providing resolution in the depth direction. Method is known.
This method evaluates crystal defects by performing highly selective anisotropic etching such as reactive ion etching at a constant thickness on the main surface of the substrate and detecting the remaining etching residue. is there.

  Since the etching rate is different between the crystal defect forming region containing SiOx and the non-forming region not containing (the former has a lower etching rate), when the reactive ion etching is performed, the main surface of the substrate is formed. Remains a cone-shaped hillock with a crystal defect containing SiOx as a vertex. Crystal defects are emphasized in the form of protrusions by anisotropic etching, and even minute defects can be easily detected.

When comparing the RIE method and the TDDB characteristics as described above, for example, as described in Patent Document 11, there are a region where the RIE defect exists and a region where the RIE defect does not exist, and a region where there is no RIE defect. It has been found that the TDDB characteristics do not deteriorate.
It was also found that even if RIE defects exist, the TDDB characteristics do not deteriorate when the density is low. That is, it has been found that the defect evaluation method based on the RIE method has higher defect detection accuracy than the TDDB characteristic.

Based on the above considerations, further investigations were made, and the present inventors diligently investigated the cause of the decrease in TDDB characteristics after RTP processing using the RIE method.
As a result, by controlling the BMD density by rapid thermal processing, the RIE defects from the substrate surface to a depth of 0.5 μm are eliminated, so that the epitaxial layer can be removed even if the surface layer is removed by subsequent vapor phase etching or the like. It has been found that defects can be effectively reduced. In addition, when RTP treatment is performed at a temperature range of 1300 ° C. or lower, which has been reported in the past, only surface defects can be removed, and RTP treatment is performed at a temperature higher than 1300 ° C. even when TDDB characteristics deteriorate. Thus, the present inventors have found that RIE defects at least from the substrate surface to a depth of 0.5 μm can be reliably eliminated. With RTP treatment at such a high temperature, COP and OSF nuclei on the surface layer can also be eliminated.
As a result, an epitaxial layer was formed on the rapidly heat-treated silicon substrate of the present invention, and the defects were evaluated for defects having a size of 47 nm or more using a laser particle inspection apparatus. The inventors have found that a good epitaxial wafer can be obtained and completed the present invention.

Hereinafter, the present invention will be described in detail as an example of an embodiment with reference to the drawings, but the present invention is not limited thereto.
FIG. 1 is a flow chart showing an example of an embodiment of a method for producing an epitaxial wafer of the present invention.

As shown in FIG. 1A, in the manufacturing method of the present invention, a silicon single crystal ingot is first grown, and a silicon substrate cut out from the silicon single crystal ingot is manufactured.
The diameter or the like of the silicon single crystal ingot to be grown is not particularly limited, and can be, for example, 150 mm to 300 mm or more, and can be grown to a desired size according to the application.

As for the defect region of the silicon single crystal ingot to be grown, for example, the entire surface can be grown from a V-Rich region, an OSF region, an N region, or a region in which these regions are mixed. Then, a silicon single crystal ingot in which the entire surface is an OSF region, the entire surface is an N region, or a region where the OSF region and the N region are mixed is grown.
Even if it is a silicon substrate cut out from a silicon single crystal ingot including a V-Rich region where COP or the like is likely to occur, an epitaxial wafer with few defects can be manufactured according to the present invention. In addition, since a silicon substrate cut out from a silicon single crystal ingot whose entire surface is an OSF region, the entire surface is an N region, or a region where the OSF region and the N region are mixed, the COP hardly hardly disappears. This is particularly effective because the rapid thermal processing of the invention can surely eliminate the defects, and it is easy to eliminate the RIE defects at deeper positions.

Here, a single crystal pulling apparatus that can be used in the manufacturing method of the present invention will be described.
FIG. 8 shows a single crystal pulling apparatus 30. The single crystal pulling apparatus 30 includes a pulling chamber 31, a crucible 32 provided in the pulling chamber 31, a heater 34 disposed around the crucible 32, a crucible holding shaft 33 that rotates the crucible 32, and a rotation mechanism thereof. (Not shown), a seed chuck 41 that holds a seed crystal of silicon, a wire 39 that pulls up the seed chuck 41, and a winding mechanism (not shown) that rotates or winds the wire 39. ing. The crucible 32 is provided with a quartz crucible on the inner side containing the silicon melt (hot water) 38 and on the outer side with a graphite crucible. A heat insulating material 35 is disposed around the outside of the heater 34.

Further, according to the manufacturing conditions, an annular graphite tube (rectifying tube) 36 can be provided as shown in FIG. 8, or an annular outer heat insulating material (not shown) can be provided on the outer periphery of the solid-liquid interface 37 of the crystal. . Further, it is possible to provide a cylindrical cooling device that blows cooling gas or cools the single crystal by blocking radiant heat.
Further, a magnet (not shown) is installed outside the pulling chamber 31 in the horizontal direction, and a magnetic field in the horizontal direction or the vertical direction is applied to the silicon melt 38 to suppress the convection of the melt, thereby producing a single crystal. It is also possible to use a so-called MCZ method apparatus for achieving stable growth.
Each part of these apparatuses can be the same as that of the prior art, for example.

Below, an example of the single crystal growth method by the above single crystal pulling apparatus 30 is demonstrated.
First, in a crucible 32, a high-purity polycrystalline silicon raw material is heated to a melting point (about 1420 ° C.) or higher and melted. Next, by unwinding the wire 39, the tip of the seed crystal is brought into contact with or immersed in the substantially central portion of the surface of the silicon melt 38. Thereafter, the crucible holding shaft 33 is rotated in an appropriate direction, and the wire 39 is wound while being rotated, and the seed crystal is pulled up to start growing the silicon single crystal ingot 40.
Thereafter, the silicon single crystal ingot 40 having a substantially cylindrical shape is obtained by appropriately adjusting the pulling speed and temperature.

  In order to efficiently control the desired pulling rate (growth rate), for example, an ingot is grown in advance while changing the pulling rate, and a preliminary test is performed to investigate the relationship between the pulling rate and the defect region, and then Based on the relationship, the silicon single crystal ingot can be manufactured again so that a desired defect region can be obtained by controlling the pulling rate in this test.

The preliminary test and the main test will be described below.
In the preliminary test, when pulling up the silicon single crystal ingot, the growth rate was controlled to gradually decrease from the crystal head to the tail in the range of 0.7 mm / min to 0.4 mm / min. The oxygen concentration of the single crystal was grown so as to be 6 × 10 ^{17 to} 7 × 10 ¹⁷ atoms / cm ³ (JEIDA).

The pulled silicon single crystal ingot was vertically cut in the crystal axis direction to produce a plurality of plate-like blocks.
The first of these plate-like blocks is cut to a length of every 10 cm in the crystal axis direction, heat treated in a wafer heat treatment furnace at 650 ° C. for 2 hours in a nitrogen atmosphere, and then heated to 800 ° C. for 4 hours. After holding, the temperature was changed to an oxygen atmosphere, the temperature was raised to 1000 ° C., held for 16 hours, and then cooled and taken out.

Thereafter, an X-ray topography image was taken, and a wafer lifetime map was created using WT-85 manufactured by SEMILAB.
The second block was subjected to seco etching after 1 hour OSF heat treatment in a wet oxygen atmosphere at 1100 ° C. for 1 hour to confirm the OSF distribution.

  Based on these findings, the V-Rich region, OSF region, Nv region, Ni region, and I-Rich region were identified. The growth rate and each defect distribution of the silicon single crystal ingot by this preliminary test are shown in FIG.

In the following, the growth rate at the boundary of each defect region of the pulled single crystal shown in FIG. 3 is shown as an example.
V-Rich / OSF region boundary: 0.591 mm / min
OSF extinction boundary: 0.581 mm / min
Nv / Ni region boundary: 0.520 mm / min
Ni / I-Rich region boundary: 0.503 mm / min

  Here, as the main test, based on the relationship between the growth rate and the defect distribution, the pulling rate is controlled so as to have a desired defect region in the same in-furnace structure where the defect region is identified. A silicon single crystal ingot 40 is grown.

For example, in the case of FIG. 3, if a silicon single crystal ingot is grown while controlling the pulling speed V to be 0.610 mm / min and cut out in the radial direction, the V-Rich region where COP exists over almost the entire surface of the wafer. Thus, a mixed wafer of a V-Rich region and an OSF region in which an OSF region exists in the vicinity of the outermost peripheral portion can be obtained (hereinafter referred to as a V-Rich + OSF wafer).
Further, if the silicon single crystal ingot is grown while controlling the pulling speed V to be 0.586 mm / min and cut out in the radial direction, the wafer center is the OSF region, and the outer peripheral portion is the Nv region. A mixed wafer of the OSF region and the Nv region can be obtained (hereinafter referred to as OSF + Nv wafer).

  Of course, the present invention is not limited to these defect regions, and it is possible to grow a silicon single crystal ingot having a desired defect region as described above in the radial direction by adjusting the pulling speed and the in-furnace structure.

Also, the oxygen concentration of the silicon single crystal ingot to be grown is not particularly limited. For example, by growing the ingot so as to contain oxygen at a concentration of 9 × 10 ¹⁷ atoms / cm ³ (JEIDA) or less, It is preferable to slice and obtain a silicon single crystal wafer containing oxygen at a concentration of 9 × 10 ¹⁷ atoms / cm ³ (JEIDA) or less to obtain a silicon substrate used in the present invention.
Thus, if the silicon single crystal wafer has an oxygen concentration of 9 × 10 ¹⁷ atoms / cm ³ (JEIDA) or less, it is possible to prevent the size of glow-in defects and glow-in oxygen precipitates from becoming too large. This eliminates the need for a higher temperature / longer time than necessary under the conditions of the rapid heat treatment, and enables the production method of the present invention to be carried out more efficiently, which is advantageous for industrial production.

Further, for example, by doping a ^{1 × 10 11 ~1 × 10 15} atoms / cm 3 concentration of nitrogen in silicon single crystal ingot growing, the ^{1 × 10 11 ~1 × 10 15} atoms / cm 3 concentration of It is preferable to obtain a silicon single crystal wafer containing nitrogen to obtain a silicon substrate used in the present invention.
If the wafer has such a nitrogen concentration, it is possible to improve the wafer strength and promote the formation of BMD in the bulk portion.

Furthermore, for example, by doping carbon concentration of the silicon single crystal ingot to ^{1 × 10 16 ~1 × 10 17} atoms / cm 3 to develop, the concentration of ^{1 × 10 16 ~1 × 10 17} atoms / cm 3 It is preferable to obtain a silicon single crystal wafer containing the above carbon and use it as the silicon substrate used in the present invention.
If the wafer has such a carbon concentration, when the heat treatment during the device process is performed at a low temperature for a long time (for example, 400 to 600 ° C.), formation of oxygen donors generated during the heat treatment can be suppressed. In addition, it is possible to promote the formation of BMD in the bulk portion.

  Next, as shown in FIG. 1B, the silicon substrate manufactured as described above is subjected to rapid thermal processing, and is detected by the RIE method existing at least in a region from the surface of the silicon substrate to a depth of 0.5 μm. RIE defect extinction process is performed to eliminate the defects to be generated.

  In this RIE defect extinction process, defects detected by the RIE method existing in the region from the surface of the silicon substrate to a depth of 0.5 μm are extinguished, so that vapor phase etching with hydrogen chloride gas usually performed in the epitaxial growth process is performed, for example. Even if the thickness is about 0.3 μm, no defects are exposed on the surface of the silicon substrate, so that epitaxial growth can be performed on the surface of the silicon substrate having no defects. Can be suppressed.

Here, a crystal defect evaluation method using the RIE method will be described with reference to FIG.
First, as shown in FIG. 5A, in the silicon substrate W, oxygen precipitation defects 111 are formed in which oxygen dissolved in supersaturation by heat treatment or the like is precipitated as SiOx.
The silicon substrate W is included in the silicon substrate W from the main surface of the silicon substrate W in a halogen-based mixed gas (eg, HBr / Cl ₂ / He + O ₂ ) atmosphere using a commercially available RIE apparatus. When anisotropic etching with a high selection ratio is performed on the oxygen precipitation defect 111, the result is as shown in FIG. That is, a conical protrusion due to the oxygen precipitation defect 111 is formed as an etching residue (hillock 112). Therefore, crystal defects can be evaluated based on the hillock 112.

For example, if the number of hillocks 112 obtained is counted, the density of BMD in the silicon substrate W in the etched range can be obtained.
Defects that can be detected by this RIE method (RIE defects) are oxygen precipitate-related defects, which are complex defects in which vacancies are agglomerated with oxygen, such as COP and OSF nuclei, and glow-in oxygen precipitates in which oxygen alone is agglomerated. It is.

  In the production method of the present invention, the surface of the silicon substrate after the rapid heat treatment is removed by 0.5 μm by etching, polishing, etc., and the surface is subjected to defect evaluation by the RIE method, whereby the rapid heat treatment conditions can be examined. As described above, since the RIE method has high defect detection accuracy, it is possible to surely determine whether or not defects from the substrate surface to a depth of 0.5 μm have disappeared by rapid thermal processing, and defects of 50 nm or less generated in the epitaxial layer. Can also be effectively suppressed.

In addition, the rapid heating / cooling apparatus that can be used for the rapid thermal processing of the present invention is not particularly limited, and a commercially available conventional one can be used. FIG. 4 shows a schematic view of an example of a rapid heating / cooling device that can be used.
The rapid heating / cooling device 52 has a chamber 53 made of quartz, and the silicon substrate W can be rapidly heat-treated in the chamber 53. Heating is performed by a heating lamp 54 (for example, a halogen lamp) disposed so as to surround the chamber 53 from above, below, left, and right. The heating lamps 54 can control power supplied independently.

On the gas exhaust side, an auto shutter 55 is provided to block outside air. The auto shutter 55 is provided with a wafer insertion port (not shown) configured to be opened and closed by a gate valve. Further, the auto shutter 55 is provided with a gas exhaust port 51 so that the furnace atmosphere can be adjusted.
The silicon substrate W is disposed on a three-point support portion 57 formed on the quartz tray 56. A quartz buffer 58 is provided on the gas inlet side of the quartz tray 56, and can prevent an introduced gas such as an oxidizing gas, a nitriding gas, and an Ar gas from directly hitting the silicon substrate W. .

  The chamber 53 is provided with a temperature measurement special window (not shown), and the pyrometer 59 installed outside the chamber 53 can measure the temperature of the silicon substrate W through the special window.

Such a rapid heating / cooling apparatus is used to perform rapid thermal processing on the silicon substrate. The rapid thermal processing conditions are detected by the RIE method existing at least in a region from the surface of the silicon substrate to a depth of 0.5 μm. Although it will not specifically limit if a defect can be eliminated, It is preferable to perform rapid heat processing for 1 to 60 second at the temperature of 1400 degreeC or more higher than 1300 degreeC.
With rapid thermal processing under such heat treatment conditions, glow-in defects and RIE defects existing in a region from the surface of the silicon substrate to a depth of 0.5 μm can be effectively eliminated, and new vacancies and the like can be created at the same time. It can be formed in a silicon substrate. In addition, when a silicon substrate cut out from a silicon single crystal ingot in which the entire surface is an OSF region, the entire surface is an N region, or a region where the OSF region and the N region are mixed, is used at least 5 μm from the surface of the silicon substrate by rapid thermal processing. The RIE defect up to the depth can be eliminated. For this reason, even if polishing is performed with a polishing allowance of about 4 μm, for example, in order to remove foreign matters and contamination before the silicon epitaxial layer forming step, RIE defects are not exposed on the substrate surface. Further, by such polishing, a region where the oxygen concentration of the surface layer is reduced can be completely removed to obtain a silicon substrate that does not have a decrease in the oxygen concentration of the surface layer, so that slip dislocation occurs due to the temperature during epitaxial growth. The epitaxial wafer can be manufactured with higher productivity.

  Further, as the temperature increase / decrease rate of the rapid heat treatment of the present invention, for example, the temperature can be increased at a temperature increase rate of 50 ° C./second, held for a certain time, and then decreased at a temperature decrease rate of 50 ° C./second. . The temperature increase rate and temperature decrease rate can be set as appropriate.

As an atmosphere for such rapid thermal processing, for example, an atmosphere containing at least one kind of a gas for forming a nitride film such as nitrogen and NH ₃ and an Ar gas can be used.
In such an atmosphere, RIE defects on the surface layer of the substrate can be eliminated, and point defects such as new vacancies can be uniformly formed inside the substrate. At times, the formation of BMD is greatly promoted, and an epitaxial wafer having a high gettering ability can be manufactured.

Moreover, as an atmosphere of rapid thermal processing, it can also be set as an oxygen atmosphere, for example.
In this case, RIE defects on the surface layer of the substrate can be eliminated, and at the same time, point defects such as new interstitial silicon can be uniformly formed inside the substrate. BMD formation is greatly suppressed.
Thus, in the manufacturing method of the present invention, the BMD density formed in the post-process can be controlled with high accuracy and greatly depending on the atmosphere during the rapid heat treatment.

Next, as shown in FIG. 1C, a silicon epitaxial layer is formed on the silicon substrate from which the RIE defects in the surface layer have been eliminated. Before this epitaxial growth, it is preferable to perform vapor phase etching to remove foreign matter, contamination, and the like on the surface of the silicon substrate. Further, it is more preferable to perform further polishing.
In the case of such a silicon substrate subjected to the rapid thermal processing of the present invention, even if the above polishing and vapor phase etching are performed, defects are not exposed on the substrate surface, so that a silicon epitaxial layer having almost no defects is formed. Can do.

The epitaxial growth conditions at this time are not particularly limited. For example, it is preferable to form a silicon epitaxial layer on the surface of the silicon substrate at a growth temperature of 1175 ° C. or lower.
Thus, by setting the growth temperature to 1175 ° C. or less, the temperature is 125 ° C. or more lower than that when the rapid heat treatment of the present invention is performed at a temperature higher than 1300 ° C. It is possible to suppress the disappearance of holes, interstitial silicon, and the like during epitaxial growth. Thereby, the BMD density control in the epitaxial wafer in a post process can be performed effectively.

  From the above, the present invention is freed from the limitations of the conventional method for eliminating defects during epitaxial growth, such as increasing the thickness of the silicon epitaxial layer, and is free from defects regardless of the epitaxial growth conditions and the thickness of the epitaxial layer. It is possible to manufacture an epitaxial wafer having a very small and good quality.

  As described above, an epitaxial wafer manufactured by the manufacturing method of the present invention has almost no defects and has a uniform BMD over the entire wafer. In-plane variation in characteristics can be reduced.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Example 1-4, Comparative Example 1-6)
Using the single crystal pulling apparatus of FIG. 8, a lateral magnetic field is applied to grow silicon single crystal ingots (diameter 12 inches (300 mm), orientation <100>, conductivity type P type) in various defect regions by the MCZ method. A silicon substrate cut out therefrom was prepared.
In the preliminary test regarding the relationship between the growth rate of the silicon single crystal ingot and the defect region, the same relationship as in FIG. 3 is obtained, and based on this relationship, the desired defect region (V-Rich + OSF and OSF + Nv) is obtained. An ingot having the structure was grown and a silicon substrate was cut out.

  Next, using the rapid heating / rapid cooling device of FIG. 4 (here, VANTAGE manufactured by Applied Materials), the temperature was rapidly raised from room temperature at a heating rate of 50 ° C./second in an Ar gas atmosphere, and 1200-1350 ° C. Was held at the maximum temperature for 10 seconds, and then rapidly cooled at a temperature drop rate of 50 ° C./second to prepare three silicon substrates (samples 1-3). In addition, three silicon substrates (samples 1-3) not subjected to the RTP treatment were also prepared.

  Sample 1 was polished by about 0.5 μm and then etched using a magnetron RIE apparatus (P-5000 manufactured by Applied Materials). Thereafter, hillocks after etching were measured with a laser scattering foreign matter inspection apparatus (SP1 manufactured by KLA-Tencor). Moreover, the number of hillocks was measured using an electron microscope, and the defect density was calculated.

  Sample 2 was polished for about 5 μm and then etched using a magnetron RIE apparatus (P-5000 manufactured by Applied Materials). Then, the hillock after an etching was measured with the laser scattering type foreign material inspection apparatus (SP1 made by KLA-Tencor). Moreover, the number of hillocks was measured using an electron microscope, and the defect density was calculated.

Sample 3 was epitaxially grown using a commercially available single wafer epitaxial growth apparatus (Centura manufactured by Applied Materials). Epitaxial growth was first heated to 1150 ° C. under normal pressure, 0.5 μm vapor phase etching was performed by flowing hydrogen chloride gas, and then epitaxial growth was performed by flowing TCS gas.
The thickness of the epitaxial layer is 0.5 μm, the conductivity type is P type, and the resistivity is 10 Ωcm. Thereafter, a defect having a size of 47 nm or more on the surface of the epitaxial layer was measured with a laser scattering foreign matter inspection apparatus (SP2 manufactured by KLA-Tencor).

The epitaxial wafer fabrication conditions of Example 1-4 and Comparative Example 1-6 are as follows.
Example 1 (V-Rich + OSF)
Lifting speed: 0.610 mm / min, RTP processing temperature: 1320 ° C.
(Example 2) (V-Rich + OSF)
Lifting speed: 0.610 mm / min, RTP processing temperature: 1350 ° C.
Example 3 (OSF + Nv)
Lifting speed: 0.585 mm / min, RTP processing temperature: 1320 ° C.
(Example 4) (OSF + Nv)
Lifting speed: 0.585 mm / min, RTP processing temperature: 1350 ° C.

(Comparative Example 1) (V-Rich + OSF)
Lifting speed: 0.610 mm / min, no RTP treatment (Comparative Example 2) (V-Rich + OSF)
Lifting speed: 0.610 mm / min, RTP processing temperature: 1250 ° C.
(Comparative Example 3) (V-Rich + OSF)
Lifting speed: 0.610 mm / min, RTP processing temperature: 1270 ° C.
(Comparative Example 4) (OSF + NV)
Lifting speed: 0.585 mm / min, no RTP treatment (Comparative Example 5) (OSF + NV)
Lifting speed: 0.585 mm / min, RTP processing temperature: 1250 ° C.
(Comparative Example 6) (OSF + NV)
Lifting speed: 0.585 mm / min, RTP processing temperature: 1270 ° C.

  Table 1 shows the defect density detected by the RIE method of Samples 1 and 2 and the number of defects on the surface of the epitaxial wafer of Sample 3.

As is clear from Table 1, in both the V-Rich + OSF wafer and the OSF + Nv wafer, when the RTP temperature is higher than 1300 ° C. (Example 1-4), the number of defects decreases rapidly and is detected by the RIE method. The defect has disappeared completely. In any case, it can be seen that the RIE defects existing at a depth of 0.5 μm from at least the surface of the wafer disappeared by the RTP process of the example.
In addition, in the case of OSF + Nv wafer, since there is no COP that hardly disappears, even when polished by 5 μm after RTP treatment (Sample 2), the RIE defect is completely disappeared. It can be seen that if the RTP treatment is performed at a high temperature, defects from the surface to a position deeper than at least 5 μm can be completely eliminated.

In addition, the defect of the epitaxial wafer epitaxially grown after the RTP treatment of Sample 3 is 10 or less even in the case of the RTP treatment performed at a temperature higher than 1300 ° C. in any case, even when the defect having an extremely small size of 47 nm is evaluated. It can be seen that the epitaxial wafer manufactured by the manufacturing method of the present invention has good quality.
In this embodiment, vapor phase etching with hydrogen chloride gas is performed at 0.5 μm immediately before the epitaxial growth step. From this, it can be seen that in the silicon substrate subjected to the RTP treatment at a temperature higher than 1300 ° C., all the defects existing in the range of at least 0.5 μm from the surface disappeared. On the contrary, as shown in the comparative example, when the RTP temperature is 1300 ° C. or lower, the number of defects is 10 or more, and it can be seen that the defects remaining in the epitaxial layer are generated.

(Examples 5 and 6, Comparative Example 7-9)
Based on the relationship between the growth rate and defect region of the silicon single crystal ingot shown in FIG. 3, the silicon single crystal ingot was grown to prepare an OSF + Nv wafer.
Next, using the rapid heating / rapid cooling device (Applied Materials VANTAGE) shown in FIG. 4, the temperature was rapidly raised from room temperature at a heating rate of 50 ° C./second in an Ar gas atmosphere, and the maximum temperature of 1200 to 1350 ° C. Was held for 10 seconds, and then rapidly cooled at a temperature drop rate of 50 ° C./second to prepare a silicon substrate (sample) for epitaxial wafer growth. Further, a silicon substrate (sample) prepared in the same manner but not subjected to the RTP treatment was also prepared.

After polishing these samples by about 5 μm, epitaxial growth was performed using a commercially available single wafer epitaxial growth apparatus (Centura manufactured by Applied Materials). Epitaxial growth was first heated to 1150 ° C. under normal pressure, 0.5 μm vapor phase etching was performed by flowing hydrogen chloride gas, and then epitaxial growth was performed by flowing TCS gas.
The thickness of the epitaxial layer is 0.5 μm, the conductivity type is P-type, and the resistivity is 10 Ωcm. Thereafter, defects with a size of 47 nm or more were measured with a laser scattering foreign matter inspection apparatus (SP2 manufactured by KLA-Tencor).

The epitaxial wafer production conditions of the examples and comparative examples are as follows.
(Example 5) (OSF + Nv)
Lifting speed: 0.585 mm / min, RTP processing temperature: 1320 ° C.
(Example 6) (OSF + Nv)
Lifting speed: 0.585 mm / min, RTP processing temperature: 1350 ° C.
(Comparative Example 7) (OSF + NV)
Lifting speed: 0.585 mm / min, no RTP treatment (Comparative Example 8) (OSF + NV)
Lifting speed: 0.585 mm / min, RTP processing temperature: 1250 ° C.
(Comparative Example 9) (OSF + NV)
Lifting speed: 0.585 mm / min, RTP processing temperature: 1270 ° C.

  Table 2 shows the number of defects on the surface of the epitaxial wafer produced for each sample.

As is clear from Table 2, in Examples 5 and 6, in the case of the OSF + Nv wafer, the number of defects in the epitaxial layer is 3 even after polishing with an excess of 5 μm after RTP treatment at a temperature higher than 1300 ° C. and epitaxial growth. It is good.
Considering these results together with the results in Table 1, OSF nuclei and RIE defects present in the OSF + Nv wafer can be completely extinguished from the surface over at least 5 μm at temperatures higher than 1300 ° C. It can be seen that even if polishing of 5 μm is performed later, the surface of the silicon substrate is maintained in a defect-free state without defects, and a high-quality epitaxial layer free from defects can be formed when epitaxially grown on this surface. For this reason, when a wafer in which an OSF region and an Nv region are mixed is used for a silicon substrate for epitaxial growth, the surface can be polished after the RTP process. There is an advantage that both yield improvement and quality improvement can be achieved.

(Examples 7 and 8, Comparative Example 10)
Based on the relationship between the growth rate and defect region of the silicon single crystal ingot shown in FIG. 3, the silicon single crystal ingot was grown and three OSF + Nv wafers were prepared.

The first sheet is rapidly heated from room temperature at a heating rate of 50 ° C./second in an Ar gas atmosphere using the rapid heating / rapid cooling device of FIG. 4 (here, VANTAGE manufactured by Applied Materials), and 1350 ° C. Was held at the maximum temperature for 10 seconds, and then rapidly cooled at a temperature decrease rate of 50 ° C./second, and then the surface was polished by about 5 μm (silicon substrate-1).
The second sheet was rapidly heated from room temperature in an oxygen gas atmosphere at a temperature increase rate of 50 ° C./second, held at the maximum temperature of 1350 ° C. for 10 seconds, and then rapidly cooled at a temperature decrease rate of 50 ° C./second. The surface was polished by about 5 μm (silicon substrate-2).
The third sheet was polished about 5 μm without performing RTP treatment (silicon substrate-3).
Epitaxial growth was performed on the silicon substrate-1, the silicon substrate-2, and the silicon substrate-3 by using a commercially available single wafer epitaxial growth apparatus (Centura manufactured by Applied Materials).

Epitaxial growth was carried out under normal pressure by first heating to 1150 ° C., flowing hydrogen chloride gas and performing 0.5 μm vapor phase etching, and then flowing TCS gas for epitaxial growth. The thickness of the epitaxial layer is 5 μm. Thereafter, a heat treatment was performed at 800 ° C. for 4 hours in an N ₂ gas atmosphere as an oxygen precipitation heat treatment, and then a heat treatment was further performed at 1000 ° C. for 16 hours. Thereafter, BMD measurement was performed on the silicon substrate.
Table 3 shows the BMD measurement results.

As is clear from Table 3, BMD of an epitaxial wafer in which an epitaxial layer is formed on a silicon substrate subjected to RTP treatment in an Ar atmosphere (Example 7) has an extremely high density of 3 × 10 ⁷ BMD. This is a result of the vacancies newly formed in the silicon substrate during the RTP process acting as non-uniform nuclei for the formation of precipitation nuclei in the heat treatment during the epitaxial growth process and the subsequent heat treatment.
Conversely, the BMD when an epitaxial layer is formed on a silicon substrate that has been RTP treated in an oxygen atmosphere is (Example 8), 1 × 10 ³ , and an epitaxial wafer fabricated without RTP treatment (Comparative Example 10). The occurrence of BMD is suppressed by about 2 digits from 1 × 10 ^{5 of} BMD.

This is a result of the interstitial silicon newly formed in the silicon substrate during the RTP process suppressing the formation of precipitate nuclei by the heat treatment during the epitaxial growth process and the subsequent heat treatment.
Thus, BMD can be increased or suppressed by changing the atmosphere of the RTP process. In addition to the atmosphere, by appropriately selecting conditions such as the holding temperature, holding time, or cooling rate of the RTP treatment, it becomes possible not only to dissolve defects in the silicon substrate but also to form a desired BMD at the same time. Thus, there is no generation of defects in the epitaxial layer required for the device, and an epitaxial wafer in which a BMD in an amount necessary for improving the gettering capability and strength is formed in the silicon substrate can be manufactured.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

30 ... Single crystal pulling device, 31 ... Pulling chamber, 32 ... Crucible,
33 ... crucible holding shaft, 34 ... heater, 35 ... heat insulating material, 36 ... rectifying cylinder,
37 ... solid-liquid interface, 38 ... silicon melt, 39 ... wire,
40 ... Silicon single crystal ingot, 41 ... Seed chuck,
51 ... Gas exhaust port, 52 ... Rapid heating / cooling device, 53 ... Chamber,
54 ... Heating lamp, 55 ... Auto shutter, 56 ... Quartz tray,
57 ... support part, 58 ... buffer, 59 ... pyrometer W ... silicon substrate.

Claims (8)

A method for producing an epitaxial wafer by forming a silicon epitaxial layer on the surface of a silicon substrate cut out from a silicon single crystal ingot grown by the Czochralski method, comprising:
RIE defect extinguishing step for eliminating defects detected by the RIE method existing at least in a region from the surface of the silicon substrate to a depth of 0.5 μm by performing a rapid heat treatment on the silicon substrate, and detecting by the RIE method And a step of forming the silicon epitaxial layer on the surface of the silicon substrate from which the defects to be eliminated have been eliminated.   In the RIE defect extinction step, the rapid thermal treatment is performed at a temperature higher than 1300 ° C. and lower than 1400 ° C. in an atmosphere containing at least one of a nitride film forming atmosphere gas and an Ar gas using a rapid heating / cooling apparatus. 2. The epitaxial wafer according to claim 1, wherein the silicon epitaxial layer is formed at a temperature of 1175 ° C. or less on the surface of the silicon substrate in the silicon epitaxial layer forming step. Manufacturing method.   In the RIE defect disappearance step, the rapid thermal treatment is performed in an oxygen atmosphere at a temperature higher than 1300 ° C. and lower than 1400 ° C. for 1 to 60 seconds using a rapid heating / rapid cooling device, and in the silicon epitaxial layer forming step, The method for producing an epitaxial wafer according to claim 1, wherein the silicon epitaxial layer is formed on the surface of the silicon substrate at a growth temperature of 1175 ° C. or lower.   The silicon substrate is a silicon single crystal wafer cut out from a silicon single crystal ingot whose entire surface is an OSF region, and whose entire surface is an N region, or a region where the OSF region and the N region are mixed. The manufacturing method of the epitaxial wafer as described in any one of Claim 3. 5. The silicon substrate according to claim 1, wherein the silicon substrate is a silicon single crystal wafer containing oxygen at a concentration of 9 × 10 ¹⁷ atoms / cm ³ (JEIDA) or less. Epitaxial wafer manufacturing method. A silicon single crystal wafer containing nitrogen at a concentration of 1 × 10 ¹¹ to 1 × 10 ¹⁵ atoms / cm ³ and / or carbon at a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ ; An epitaxial wafer manufacturing method according to any one of claims 1 to 5, wherein:   An epitaxial wafer manufactured by the method for manufacturing an epitaxial wafer according to any one of claims 1 to 6.   An imaging device is manufactured using the epitaxial wafer according to claim 7, wherein the imaging device manufacturing method is characterized.

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