JP2017208470A - Epitaxial wafer manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer manufacturing method capable of inhibiting stacking fault.SOLUTION: An epitaxial wafer manufacturing method comprises a preparation process, a heat treatment process, a vapor-phase etching process and a growth process. In the preparation process, a phosphor-doped and low resistivity substrate W is prepared. In the heat treatment process, the substrate W is subjected to a heat treatment in an argon atmosphere and at temperature not less than 1000°C and less than 1200°C and for a period not less than 30 minutes and not more than 120 minutes. In the vapor-phase etching process, a principal surface of the substrate W is subjected to vapor-phase etching by a hydrogen chloride gas for 0.025 μm and over after the heat treatment process. In the growth process, an epitaxial layer is grown on the substrate W after the vapor-phase etching process.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an epitaxial wafer manufacturing method.

  For example, an epitaxial wafer is used as a substrate of a semiconductor element used for a mobile terminal or the like. In such a semiconductor element, it is required to lower the on-resistance due to a demand for power saving. As a specific method for reducing the on-resistance, there are a method for reducing the thickness of the semiconductor element substrate and a method for decreasing the resistivity of the semiconductor element substrate. There are limits. Therefore, an epitaxial layer is grown on a low resistivity silicon single crystal substrate doped with a dopant at a high concentration, and a low resistivity epitaxial wafer as a semiconductor element substrate is produced.

  A silicon single crystal substrate that is the basis of such an epitaxial wafer is manufactured based on an ingot that is pulled up by doping with a high concentration of dopant. However, when an n-type dopant such as Sb (antimony) or As (arsenic) is used as this dopant, the doped dopant evaporates during the pulling. Therefore, if the silicon single crystal substrate on which the epitaxial layer is grown is n-type, a silicon single crystal substrate doped with phosphorus as a dopant when pulling up the single crystal in the form of red phosphorus having relatively low volatility is used. Then, an epitaxial layer having a low resistivity is manufactured by vapor-phase growth of an epitaxial layer on the main surface of the prepared silicon single crystal substrate.

  However, when an epitaxial layer is grown on a low resistivity silicon single crystal substrate doped with phosphorus at a high concentration, many stacking faults (stacking faults) occur on the main surface of the epitaxial wafer after vapor phase growth. When a semiconductor element is manufactured using the epitaxial wafer in which the stacking fault has occurred, characteristics (mainly withstand voltage characteristics) of the semiconductor element (device) are deteriorated. Therefore, it is necessary to reduce the number of stacking faults to a level that does not affect the device characteristics.

  The stacking faults observed on the main surface of the epitaxial wafer are observed when dislocations originate from crystal defects generated on a low resistivity silicon single crystal substrate and propagate to the main surface of the epitaxial wafer. The Since the stacking faults observed on the main surface of the epitaxial wafer tend to increase as the resistivity of the silicon single crystal substrate decreases, it is considered that phosphorus as a dopant is involved in the formation of stacking faults.

  Therefore, Patent Document 1 discloses a method of manufacturing an epitaxial wafer in which an annealing process is performed at a temperature of 1200 ° C. or higher before an epitaxial layer is grown on a low resistivity silicon single crystal substrate, and defects generated in the silicon single crystal substrate are solutionized. It is disclosed. Further, Patent Document 2 discloses that the main surface of a low resistivity silicon single crystal substrate is polished to clean the main surface of the substrate and suppress stacking faults generated in the epitaxial wafer. Specifically, a low resistance semiconductor substrate doped with phosphorus and germanium is heat-treated at a temperature of 1110 ° C. to 1200 ° C. for 30 seconds to 300 seconds, and then the low resistance semiconductor substrate is 1 μm or more and 10 μm or less. A method of manufacturing an epitaxial wafer for performing polishing is disclosed.

JP 2014-11293 A International Publication WO2011 / 007678

However, even when an epitaxial layer is grown on a low resistivity silicon single crystal substrate that has been subjected to these treatments, a stacking fault having a concentration that adversely affects the characteristics of the semiconductor element may occur in the epitaxial wafer. In particular, when a low resistivity substrate having a dopant concentration of 8 × 10 ¹⁹ atoms / cm ³ or more is used, a great number of stacking faults are generated on the epitaxial wafer.

  The subject of this invention is providing the manufacturing method of the epitaxial wafer which can suppress a stacking fault.

Means for Solving the Problems and Effects of the Invention

The method for producing an epitaxial wafer of the present invention includes:
Preparing a low resistivity silicon single crystal substrate doped with phosphorus;
Heat treating the silicon single crystal substrate at a temperature of 1000 ° C. or higher and lower than 1200 ° C. for 30 minutes to 120 minutes in an argon atmosphere;
A step of performing a vapor phase etching of the main surface of the silicon single crystal substrate with hydrogen chloride gas by 0.025 μm or more after the heat treatment step;
A step of growing an epitaxial layer on the silicon single crystal substrate after the step of vapor phase etching;
It is characterized by providing.

  The epitaxial wafer manufacturing method of the present invention includes a heat treatment step and a vapor phase etching step after the heat treatment step. Here, in the heat treatment step, decomposition of stacking fault nuclei such as crystal defects generated in the silicon single crystal substrate occurs, and at the same time, phosphorus, which is a source (generation source) of stacking fault nuclei, diffuses outward, and the concentration of phosphorus Decreases. Therefore, after the heat treatment step, even if the stacking fault nuclei are regenerated, the phosphorus concentration is lowered, so that the stacking fault nuclei are reduced in concentration. Then, by performing a vapor phase etching step after the heat treatment step, a certain number of stacking fault nuclei remaining after being gettered to the main surface of the silicon single crystal substrate can be removed. Therefore, an epitaxial wafer in which stacking faults are suppressed can be manufactured by growing an epitaxial layer on the silicon single crystal substrate after the heat treatment step and the vapor phase etching step. Note that if the temperature range of the heat treatment step is outside the above range, the decomposition rate of the stacking fault nuclei decreases, so the stacking fault suppression effect decreases.

In this specification, the “low resistivity silicon single crystal substrate” may be, for example, a silicon single crystal substrate doped with phosphorus of 5 × 10 ¹⁹ atoms / cm ³ or more, or phosphorus of 8 × 10 ¹⁹ atoms / cm ^3. It may be a silicon single crystal substrate doped with cm ³ or more. In the case of using a silicon single crystal substrate doped with 8 × 10 ¹⁹ atoms / cm ³ or more of phosphorus, stacking faults of the epitaxial wafer can be reduced more effectively.

  In the embodiment of the present invention, in the step of vapor phase etching, the etching amount is 1.000 μm or less.

  According to this, productivity of an epitaxial wafer can be improved.

The figure explaining each process in the manufacturing method of the epitaxial wafer of an example of this invention. The graph which shows the relationship between the temperature (degreeC) of the heat processing of the heat processing process of FIG. 1, and the density (piece / cm < ² >) of the stacking fault of the epitaxial wafer produced through the heat processing process. The graph which shows the relationship between the etching amount (micrometer) of the etching process of FIG. 1, and the density (piece / cm < ² >) of the stacking fault of the epitaxial wafer produced through the etching process. The graph which shows the density (piece / cm < ² >) of the stacking fault which generate | occur | produced in the epitaxial wafer produced in the Example and Comparative Examples 1-3.

  Hereinafter, a method of manufacturing a silicon epitaxial wafer in which a silicon epitaxial layer is grown on a phosphorus-doped silicon single crystal substrate will be described. In the following, a method of manufacturing an epitaxial wafer using a known vapor phase growth apparatus for manufacturing an epitaxial wafer (hereinafter referred to as “vapor phase growth apparatus”) will be described.

In order to manufacture a silicon epitaxial wafer using a vapor phase growth apparatus, first, a silicon single crystal substrate which is a growth substrate on which an epitaxial layer is grown is manufactured. For example, polycrystalline silicon in a quartz crucible, and a seed crystal silicon rod is dipped in the molten liquid obtained by adding phosphorus in the form of red phosphorus to adjust the resistivity, and pulling it up to produce a silicon single crystal ingot To do. At the time of producing this silicon single crystal ingot, phosphorus is added as a dopant in an amount of 5 × 10 ¹⁹ atoms / cm ³ or more (for example, phosphorus is added at 1 × 10 ²⁰ atoms / cm ³ ). Then, step S1 of FIG. 1 is performed on the produced silicon single crystal ingot.

  In S1, the produced silicon single crystal ingot is cut out to a predetermined thickness, and then a CW process such as lapping, liquid phase etching, donor killer heat treatment, etc. is performed to obtain a CW wafer subjected to the CW process.

  Next, rough polishing is performed on the CW wafer obtained in the CW process of S1 (S2 in FIG. 1).

  After the rough polishing step of S2 is completed, heat treatment is performed in an argon atmosphere at a temperature of 1000 ° C. or higher and lower than 1200 ° C. for 30 minutes or longer and 120 minutes or shorter (S3 in FIG. 1).

After the heat treatment step of S3 is finished, mirror polishing is performed to obtain a PW wafer (S4 in FIG. 1). In FIG. 1, the mirror polishing process of S4 is performed after the heat treatment process of S3, but this order depends on the balance between the location of the annealing furnace where the heat treatment is performed and the progress of each process. The order may be reversed. Hereinafter, a PW wafer to which phosphorus is added as a dopant by 5 × 10 ¹⁹ atoms / cm ³ or more through steps S1 to S4 is referred to as a substrate W.

  The produced substrate W is transferred to a reaction furnace of a vapor phase growth apparatus, and steps S5 to S8 in FIG. 1 are performed. The substrate W transferred to the reaction furnace is put into a reaction furnace using hydrogen as an atmospheric gas. The substrate W put into the reaction furnace is subjected to a baking step (S5), which is heated for several tens of seconds at a temperature of 1000 ° C. or higher, for example, by a vapor phase growth apparatus, and the natural oxide film on the surface of the substrate W is removed Is done.

  Next, an etching process for performing vapor phase etching on the substrate W is performed (S6). In the etching step, hydrogen chloride gas (HCl gas) is supplied onto the main surface of the substrate W in the reaction furnace, and the main surface of the substrate W is vapor-phase etched. Specifically, the supply time and supply amount of the hydrogen chloride gas are set so that the etching amount is 0.025 μm or more and 1.000 μm or less. Since the stacking fault nucleus is localized in the region of 0.025 μm or more from the main surface of the substrate W in the depth direction (thickness direction) of the substrate W, the stacking defect is effective when the etching amount is 0.025 μm or more. Can be suppressed. On the other hand, if the etching amount exceeds 1.000 μm, the productivity for manufacturing the epitaxial wafer is lowered, and therefore the etching amount is set in the range of 0.025 μm or more and 1.000 μm or less. Note that the etching rate is set to be 0.04 μm / min or more and 0.37 μm / min or less, for example.

  When the etching process of S6 is completed, a purge process (S7) is performed for discharging the hydrogen chloride gas in the reaction furnace to the outside of the reaction furnace.

  When the purge step of S7 is completed, a vapor phase growth step (S8) for growing an epitaxial layer on the substrate W is performed. In the vapor phase growth process, for example, trichlorosilane (TCS) and hydrogen gas that is a carrier gas for diluting the trichlorosilane are supplied to the main surface of the substrate W in the reaction furnace. Epitaxial layers are vapor grown on the surface. Specifically, the temperature in the reaction furnace (substrate W) is set to 1000 ° C. or higher, for example, to grow the epitaxial layer. Thus, an epitaxial layer is grown on the substrate W, and a silicon epitaxial wafer is manufactured.

In the foregoing, a series of processes for producing an epitaxial wafer by growing an epitaxial layer on the substrate W has been described. In the substrate W that is the basis of such an epitaxial wafer, phosphorus of 5 × 10 ¹⁹ atoms / cm ³ or more (for example, 1 × 10 ²⁰ atoms / cm ³ ) is added as a dopant phosphorus when a silicon single crystal ingot is manufactured. Therefore, since there are many stacking fault nuclei such as crystal defects on the main surface of the silicon single crystal substrate cut out from the silicon single crystal ingot, when the epitaxial layer is grown on this substrate, the stacking fault nuclei are stacked on the epitaxial wafer. cause.

Accordingly, the present inventor performed etching of 0.02 μm in the etching process of S6 in FIG. 1 on the temperature at which the CW wafer is roughly polished and then heat-treated (S3 in FIG. 1) and the substrate W heat-treated at that temperature. The relationship with the density (number / cm ² ) of stacking faults formed on the epitaxial wafer on which the epitaxial layer was grown after the examination was examined. The result of the examination is shown in FIG. In FIG. 2, a silicon single crystal substrate having a resistivity of 0.74 mΩ · cm (resistivity corresponding to a phosphorus concentration of 1 × 10 ²⁰ atoms / cm ³ ) was used and selected in the range of 950 ° C. to 1200 ° C. An epitaxial wafer was fabricated based on the substrate W that was heat-treated (S3 in FIG. 1) for 90 minutes at a temperature. And the density (number / cm < ² >) of the stacking fault which generate | occur | produced in the main surface of the produced epitaxial wafer was measured using the particle counter (MAGICS made from a laser tech company). In FIG. 2, the horizontal axis indicates the heat treatment temperature (° C.) of S3 in FIG. 1, and the vertical axis indicates the density (number / cm ² ) of stacking faults generated on the main surface of the fabricated epitaxial wafer. As shown in FIG. 2, when the heat treatment temperature is less than 1000 ° C., the density of stacking faults is 1000 (pieces / cm ² ) or more. Further, when the heat treatment temperature increases from 1000 ° C., the density of stacking faults decreases. When the heat treatment temperature is 1200 ° C., the effect of improving the density of stacking faults is seen, but the effect of suppressing stacking faults is lower than when the heat treatment temperature is 1170 ° C. By performing such a heat treatment step, decomposition of stacking fault nuclei such as crystal defects generated in the silicon single crystal substrate occurs, and at the same time, phosphorus, which is a source of stacking fault nuclei, diffuses outward, and the phosphorus concentration decreases. . As a result, after the heat treatment step, even if the stacking fault nuclei are regenerated, the phosphorus concentration is lowered. Therefore, the stacking fault nuclei that are regenerated is reduced in concentration, and stacking faults of the epitaxial wafer can be suppressed. Specifically, it is produced by heat-treating a silicon single crystal substrate for 30 minutes to 120 minutes (90 minutes in FIG. 2) at a temperature of 1000 ° C. to less than 1200 ° C. in an argon atmosphere. It is possible to suppress stacking faults in the epitaxial wafer.

In addition, the present inventor has performed etching on the main surface of the substrate W that has been heat-treated at 1170 ° C. in S3 of FIG. 1 (S6 in FIG. 1), and an epitaxial layer on the substrate W on which the etching amount has been etched. The relationship of the density of stacking faults (pieces / cm ² ) formed on the epitaxial wafer grown on was examined. The result of the examination is shown in FIG. In FIG. 3, an epitaxial wafer was fabricated based on the etched substrate W by a predetermined amount (μm) in the thickness direction of the substrate W from the main surface of the substrate W. And the density (number / cm < ² >) of the stacking fault which generate | occur | produces in the main surface of the produced epitaxial wafer was measured using the particle counter (Magnec by Lasertec Corporation). In FIG. 3, it can be seen that the density of stacking faults is reduced when the etching amount of the substrate W is 0.025 μm or more. This is because the stacking fault nuclei remaining after gettering on the surface of the substrate W are locally present in a region within 0.025 μm in the depth direction from the main surface of the substrate W, and the remaining stacking fault nuclei are stacked. This is because defects are caused. Although not shown in FIG. 3, when the etching amount exceeds 1.000 μm, the etching time becomes long, so that the productivity of the epitaxial wafer is lowered. Therefore, in the etching process of S6 in FIG. 1, by setting the etching amount in the range of 0.025 μm to 1.000 μm, it becomes possible to suppress stacking faults of the epitaxial wafer to be manufactured and increase productivity. Can be improved.

  From the above, when an epitaxial wafer is produced based on the substrate W that has been subjected to the heat treatment step S3 in FIG. 1 and the etching step S6 in FIG. 1, it is possible to produce an epitaxial wafer with suppressed stacking faults. As a specific heat treatment step, when the silicon single crystal substrate is heat-treated at a temperature of 1000 ° C. or higher and lower than 1200 ° C. for 30 minutes to 120 minutes in an argon atmosphere, an epitaxial wafer with reduced stacking faults can be manufactured. Further, as a specific etching process, when the main surface of the substrate W is etched by 0.025 μm or more with hydrogen chloride gas, an epitaxial wafer with suppressed stacking faults can be produced.

  In order to confirm the effect of the present invention, the following experiment was conducted. Hereinafter, the present invention will be specifically described with reference to Examples and Comparative Examples, but these do not limit the present invention.

(Comparative example)
In Comparative Example 1, a silicon single crystal ingot having a diameter of 200 mm doped with phosphorus so as to have a resistivity of 0.71 mΩ · cm was prepared. Next, the steps S1 and S2 shown in FIG. 1 were performed on this silicon single crystal ingot. Then, the mirror polishing process of S4 was performed without performing the heat treatment process of S3 in FIG. 1, and a substrate W having a thickness of 735 μm and a resistivity of 0.71 mΩ · cm was manufactured. Then, the substrate W was carried into the reaction furnace of the vapor phase growth apparatus, and only the steps S5 and S8 in FIG. 1 were performed (the steps S6 and S7 in FIG. 1 were not performed). In the baking step of S5, the substrate W was heated to 1150 ° C. while flowing hydrogen gas into the reaction furnace. In the vapor phase growth step of S8, the temperature of the substrate W is maintained at 1150 ° C., and trichlorosilane (SiHCl ₃ ) is introduced, the growth rate is 4.0 μm / min, and the epitaxial layer is grown by 3.0 μm. Produced. And the density (number / cm < ² >) of the stacking fault which generate | occur | produced in the main surface of the produced epitaxial wafer was measured using the particle counter (MAGICS made from a laser tech company).

In Comparative Example 2, an epitaxial wafer was produced in the same manner as in Comparative Example 1 except that the heat treatment step of S3 in FIG. 1 was performed, and the density of stacking faults (pieces / cm ² ) generated on the main surface of the produced epitaxial wafer was determined. Measured. As the heat treatment condition of S3, the heat treatment was performed in an argon atmosphere at a heat treatment temperature of 1170 ° C. for 90 minutes.

In Comparative Example 3, an epitaxial wafer was produced in the same manner as in Comparative Example 1 except that the etching process of S6 and the purge process of S7 in FIG. 1 were performed, and the density (number of stacking faults generated on the main surface of the produced epitaxial wafer was measured. / Cm ² ). In the etching step of S6, the etching rate was set to 0.090 μm / min and the etching amount was set to 0.100 μm. In the purge step of S7, hydrogen gas was allowed to flow for 30 seconds while maintaining the temperature of the substrate W at 1150 ° C. for the purpose of removing hydrogen chloride gas.

(Example)
In the example, an epitaxial wafer was produced in the same manner as in Comparative Example 3 except that the heat treatment step of S3 in FIG. 1 was performed, and the density (number / cm ² ) of stacking faults generated on the main surface of the produced epitaxial wafer was measured. did. The heat treatment conditions for S3 were the same as those for the heat treatment process of Comparative Example 2.

FIG. 4 shows the density of stacking faults generated in the epitaxial wafers produced in Comparative Examples 1 to 3 and Examples. In Comparative Example 1, the density of stacking faults is 1005 (pieces / cm ² ), in Comparative Example 2, the density of stacking faults is 260 (pieces / cm ² ), and in Comparative Example 3, the density of stacking faults is 99 (pieces). / Cm ² ). In contrast, in the example, the density of stacking faults was 55 (pieces / cm ² ).

If both the heat treatment step and the etching step were not performed as in Comparative Example 1 in FIG. 4, the number of stacking faults was not sufficiently suppressed, and the density of stacking faults exceeded 1000 (pieces / cm ² ). Further, when the heat treatment step is performed without performing the etching step as in Comparative Example 2 in FIG. 4, the number of stacking faults is suppressed as compared with Comparative Example 1, but the stacking fault density is 260 (pieces / cm ² ). became. When the etching process is performed without performing the heat treatment process as in Comparative Example 3 in FIG. 4, the number of stacking faults is suppressed as compared with Comparative Example 2, but the density of stacking faults is 99 (pieces / cm ² ). became. On the other hand, by performing both the heat treatment process and the etching process as in the embodiment of FIG. 4, the number of stacking faults can be greatly reduced, and the stacking fault density is 55 (pieces / cm ² ). . Therefore, in the Example, the epitaxial wafer which suppressed the stacking fault was able to be manufactured. It should be noted that the experiment disclosed in the embodiment for carrying out the invention and the experiment disclosed in the examples differ in the addition amount of phosphorus, and therefore the absolute number of stacking faults differs between them.

  The embodiments of the present invention have been described above. However, the present invention is not limited to the specific description, and the illustrated configurations and the like can be appropriately combined within a technically consistent range. In addition, certain elements and processes may be replaced with known forms.

W substrate (silicon single crystal substrate)

Claims (4)

Preparing a low resistivity silicon single crystal substrate doped with phosphorus;
Heat-treating the silicon single crystal substrate at a temperature of 1000 ° C. or more and less than 1200 ° C. for 30 minutes to 120 minutes in an argon atmosphere;
After the heat treatment step, the main surface of the silicon single crystal substrate is vapor-phase etched by hydrogen chloride gas to 0.025 μm or more;
A step of growing an epitaxial layer on the silicon single crystal substrate after the step of vapor phase etching;
A method for producing an epitaxial wafer, comprising:   The method for manufacturing an epitaxial wafer according to claim 1, wherein the vapor phase etching step has an etching amount of 1.000 μm or less. ^{3. The} method for producing an epitaxial wafer according to claim 1, wherein in the preparing step, the silicon single crystal substrate doped with 5 × 10 ¹⁹ atoms / cm ³ or more of phosphorus is prepared. 4. The method for producing an epitaxial wafer according to claim 1, wherein in the preparing step, the silicon single crystal substrate doped with 8 × 10 ¹⁹ atoms / cm ³ or more of phosphorus is prepared. 5.

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