JP6372709B2 - Epitaxial wafer manufacturing method - Google Patents

Description

  The present invention relates to an epitaxial wafer manufacturing method.

  For example, an epitaxial wafer is used as a substrate of a semiconductor element used for a mobile terminal or the like. In such a semiconductor element, it is required to lower the on-resistance due to a demand for power saving. As a specific method for reducing the on-resistance, there are a method for reducing the thickness of the semiconductor element substrate and a method for decreasing the resistivity of the semiconductor element substrate. There are limits. Therefore, an epitaxial layer is grown on a low resistivity silicon single crystal substrate doped with a dopant at a high concentration, and a low resistivity epitaxial wafer as a semiconductor element substrate is produced. As such an epitaxial wafer, Patent Documents 1 to 3 disclose an epitaxial wafer in which an epitaxial layer is grown on a low resistivity semiconductor substrate.

  A silicon single crystal substrate that is the basis of such an epitaxial wafer is manufactured based on an ingot that is pulled up by doping with a high concentration of dopant. However, when an n-type dopant such as Sb (antimony) or As (arsenic) is used as this dopant, the doped dopant evaporates during the pulling. Therefore, if the silicon single crystal substrate on which the epitaxial layer is grown is n-type, a silicon single crystal substrate doped with phosphorus (red phosphorus) having relatively low volatility as a dopant is used. Then, an epitaxial layer having a low resistivity is manufactured by vapor-phase growth of an epitaxial layer on the main surface of the prepared silicon single crystal substrate.

  However, when an epitaxial layer is grown on a low resistivity silicon single crystal substrate doped with phosphorus at a high concentration, many stacking faults (stacking faults) occur on the main surface of the epitaxial wafer after vapor phase growth. When a semiconductor element is manufactured using the epitaxial wafer in which the stacking fault has occurred, characteristics (mainly withstand voltage characteristics) of the semiconductor element (device) are deteriorated. Therefore, it is necessary to reduce the number of stacking faults to a level that does not affect the device characteristics.

  The stacking faults observed on the main surface of the epitaxial wafer are observed by propagating to the main surface of the epitaxial wafer starting from a crystal defect or the like generated on the low resistivity silicon single crystal substrate. Since this stacking fault tends to increase as the resistivity of the silicon single crystal substrate decreases, it is considered that phosphorus as a dopant is involved in forming the stacking fault.

  Therefore, before the epitaxial layer is grown on the low resistivity silicon single crystal substrate, the main surface of the silicon single crystal substrate is vapor-phase etched with hydrogen chloride gas to clean the substrate surface and suppress the generation of stacking faults. Measures are taken.

JP 2012-156303 A JP 2014-82242 A JP 2005-79134 A

  However, even when an epitaxial layer is grown on a low resistivity silicon single crystal substrate subjected to such vapor phase etching, a stacking fault having a concentration that adversely affects the characteristics of the semiconductor element may occur in the epitaxial wafer.

  The subject of this invention is providing the manufacturing method of the epitaxial wafer which can suppress a stacking fault.

Means for Solving the Problems and Effects of the Invention

The method for producing an epitaxial wafer of the present invention includes:
Preparing a low resistivity silicon single crystal substrate doped with phosphorus;
A step of growing an epitaxial layer on a silicon single crystal substrate at a temperature of 1040 ° C. or more and 1130 ° C. or less at a growth rate of 2 μm / min or less;
It is characterized by providing.

  The epitaxial wafer manufacturing method of the present invention grows an epitaxial layer on a silicon single crystal substrate having a low resistivity by the above-described growth process, so that stacking faults occurring during the epitaxial growth can be suppressed. In the growth step, if the temperature is set to a low temperature lower than 1040 ° C., an explosive number of convex defects having a height of several tens of nm and a width of several μm are formed on the epitaxial wafer. On the other hand, when the temperature in the growth process is set to a high temperature side exceeding 1130 ° C., stacking faults generated on the epitaxial wafer increase and submicron minute pits are generated. These defects are specifically generated when an epitaxial layer is grown on a low resistivity silicon single crystal substrate doped with phosphorus (red phosphorus), and are formed by the involvement of phosphorus in the same way as stacking faults. It is thought to be caused by defects. Since such a defect also adversely affects the device characteristics of the semiconductor element, an epitaxial layer is grown on the silicon single crystal substrate in a temperature range of 1040 ° C. or higher and 1130 ° C. or lower.

In this specification, the “low resistivity silicon single crystal substrate” may be, for example, a silicon single crystal substrate doped with phosphorus (red phosphorus) at 5 × 10 ¹⁹ atoms / cm ³ or more, or phosphorus (red phosphorus). ) May be a silicon single crystal substrate doped with 8 × 10 ¹⁹ atoms / cm ³ or more. When a silicon single crystal substrate doped with 8 × 10 ¹⁹ atoms / cm ³ or more of phosphorus (red phosphorus) is used, stacking faults of the epitaxial wafer can be effectively reduced.

  In an embodiment of the present invention, the growing step is a first step, and includes a second step of growing an epitaxial layer on the epitaxial layer at a growth rate exceeding the growth rate after the first step.

  According to this, the speed at which the epitaxial layer is grown by the second step can be increased, and an epitaxial wafer in which stacking faults are suppressed can be manufactured without significantly reducing the productivity of the epitaxial wafer.

  In an embodiment of the present invention, a step of performing vapor phase etching of the main surface of the silicon single crystal substrate with hydrogen chloride gas is provided between the step of preparing and the step of growing.

  According to this, the main surface of the silicon single crystal substrate can be cleaned, and the occurrence of stacking faults can be further suppressed.

  In the embodiment of the present invention, in the step of performing vapor phase etching, the etching amount is 0.025 μm or more and 1.000 μm or less.

  The stacking fault nuclei are localized from the surface of the silicon single crystal substrate to a region of 0.025 μm or more in the depth direction of the substrate. Therefore, when the etching amount is 0.025 μm or more, the stacking fault nuclei are effectively removed. it can. Moreover, productivity can be improved by making etching amount into 1.000 micrometers or less.

The figure explaining each process (the 1) in the manufacturing method of the epitaxial wafer of an example of this invention. 6 is a graph showing the relationship between the number of stacking faults (pieces / wafer) generated on an epitaxial wafer grown with an epitaxial layer at a growth rate of 5.0 μm / min and the temperature (° C.) during epitaxial growth. The graph which shows the relationship between the number of stacking faults (piece / wafer) which generate | occur | produced in the epitaxial wafer which made the epitaxial layer grown by the growth rate of 4.0 micrometers / min, and the temperature (degreeC) at the time of epitaxial growth. 6 is a graph showing the relationship between the number of stacking faults (pieces / wafer) generated on an epitaxial wafer grown with an epitaxial layer at a growth rate of 2.0 μm / min and the temperature (° C.) during epitaxial growth. 6 is a graph showing the relationship between the number of stacking faults (pieces / wafer) generated on an epitaxial wafer grown with an epitaxial layer at a growth rate of 1.0 μm / min and the temperature during epitaxial growth (° C.). 2A to 2D are diagrams showing examples of convex defects generated in an epitaxial wafer manufactured with the temperature during epitaxial growth set to the lowest temperature side. FIG. 2A to 2D are diagrams showing examples of minute pits generated on an epitaxial wafer manufactured with the temperature during epitaxial growth set to the highest temperature side. FIG. The figure explaining each process (the 2) in the manufacturing method of the epitaxial wafer of an example of this invention. The graph which shows the number (piece / wafer) of the stacking fault which generate | occur | produced in the epitaxial wafer produced in Example 1, 2 and the comparative example.

  A method for manufacturing a silicon epitaxial wafer in which a silicon epitaxial layer is grown on a silicon single crystal substrate doped with red phosphorus will be described below. In the following, a method of manufacturing an epitaxial wafer using a known vapor phase growth apparatus for manufacturing an epitaxial wafer (hereinafter referred to as “vapor phase growth apparatus”) will be described.

  The vapor phase growth apparatus includes a reaction furnace for reacting a silicon single crystal substrate as a sample. For example, the steps S1 to S4 shown in FIG. 1 are performed in a state where the silicon single crystal substrate is housed in the reaction furnace, and an epitaxial layer is grown on the silicon single crystal substrate in the reaction furnace to produce a silicon epitaxial wafer. The

In order to manufacture a silicon epitaxial wafer using a vapor phase growth apparatus, first, a silicon single crystal substrate which is a growth substrate on which an epitaxial layer is grown is manufactured. For example, a silicon single crystal ingot is produced by immersing and pulling up a seed crystal silicon rod on the surface of a melt obtained by adding polycrystalline silicon and red phosphorus for adjusting resistivity in a quartz crucible and melting it. Next, the produced silicon single crystal ingot is cut out to a predetermined thickness, and a silicon single crystal substrate obtained by subjecting the cut wafer to rough polishing, etching, polishing and the like is produced. In this silicon single crystal substrate, 5 × 10 ¹⁹ atoms / cm ³ or more of red phosphorus is added as a dopant when a silicon single crystal ingot is manufactured (for example, 1 × 10 ²⁰ atoms / cm ^{3 of} red phosphorus is added). Hereinafter, a silicon single crystal substrate to which red phosphorus is added as a dopant at 5 × 10 ¹⁹ atoms / cm ³ or more is referred to as a substrate W.

  The produced substrate W is transferred to a reaction furnace of a vapor phase growth apparatus, and a series of steps shown in FIG. 1 is performed. The substrate W transferred to the reaction furnace is put into a reaction furnace using hydrogen as an atmospheric gas. The substrate W put into the reaction furnace is subjected to a baking process (S1) heated for several tens of seconds, for example, at a temperature of 1100 ° C. or higher by a vapor phase growth apparatus, and the natural oxide film on the surface of the substrate W is removed. Is done.

  Next, an etching process for performing vapor phase etching on the substrate W is performed (S2). In the etching step, hydrogen chloride gas (HCl gas) is supplied onto the main surface of the substrate W in the reaction furnace, and the main surface of the substrate W is vapor-phase etched. Specifically, the supply time and supply amount of the hydrogen chloride gas are set so that the etching amount is 0.025 μm or more and 1.000 μm or less. Since the stacking fault nucleus is localized in the region of 0.025 μm or more from the main surface of the substrate W in the depth direction (thickness direction) of the substrate W, the stacking defect is effective when the etching amount is 0.025 μm or more. Can be suppressed. On the other hand, if the etching amount exceeds 1.000 μm, the productivity for manufacturing the epitaxial wafer is lowered, and therefore the etching amount is set in the range of 0.025 μm or more and 1.000 μm or less. Note that the etching rate is set to be 0.04 μm / min or more and 0.37 μm / min or less, for example.

  When the etching process of S2 is completed, a purge process (S3) is performed for discharging the hydrogen chloride gas in the reaction furnace to the outside of the reaction furnace.

  When the purge process of S3 is completed, a growth process (S4) for growing an epitaxial layer on the substrate W is performed. In the growth process, a raw material gas such as trichlorosilane (TCS) and a hydrogen gas serving as a carrier gas for diluting the trichlorosilane are supplied to the main surface of the substrate W in the reaction furnace. The epitaxial layer is vapor-phase grown. Specifically, the temperature in the reaction furnace (substrate W) is maintained at a predetermined temperature of 1040 ° C. to 1130 ° C. (for example, maintained at 1100 ° C.), and the epitaxial layer is 2 μm / min or less. Grows at a growth rate. In this manner, an epitaxial layer having a predetermined thickness is grown on the substrate W to manufacture a silicon epitaxial wafer.

In the foregoing, a series of processes for producing an epitaxial wafer by growing an epitaxial layer on the substrate W has been described. The substrate W that is the basis of such an epitaxial wafer is doped with 5 × 10 ¹⁹ atoms / cm ³ or more (for example, 1 × 10 ²⁰ atoms / cm ³ ) of red phosphorus as a dopant when a silicon single crystal ingot is manufactured. Therefore, a large number of stacking fault nuclei exist on the main surface of the substrate W. Therefore, when an epitaxial layer is grown on the substrate W, stacking fault nuclei on the main surface of the substrate W cause stacking faults in the epitaxial wafer. Therefore, the main surface of the substrate W on which the stacking fault nuclei exist is removed by the etching process of S2 shown in FIG. 1 to remove the stacking fault nuclei.

  Although the stacking fault nuclei on the main surface of the substrate W are largely removed by etching the main surface of the substrate W, some stacking fault nuclei still remain in the substrate W, for example, in the form of minute pits after the etching process. To do. Therefore, even when an epitaxial layer is grown on the substrate W after etching, for example, a stacking fault nucleus such as the main surface of the substrate W may cause a stacking fault in the epitaxial wafer.

Therefore, the present inventor has scrutinized the relationship between the growth rate and temperature growth conditions for growing the epitaxial layer on the substrate W, and the number of stacking faults (pieces / wafer) formed on the epitaxial wafer grown under the growth conditions. . The scrutinized result is shown in FIGS. 2A to 2D. 2A to 2D, the growth rate during epitaxial growth varies from figure to figure, and the number of stacking faults of epitaxial wafers produced at a temperature selected during the epitaxial growth within a range of 1000 ° C. to 1160 ° C. (pieces / wafer). ) Is displayed. The epitaxial wafer produced in each figure is obtained by growing an epitaxial layer having a layer thickness of 3 μm on a substrate W having a diameter of 200 mm, a thickness of 735 μm, and a red phosphorus concentration of 1 × 10 ²⁰ atoms / cm ³ . Moreover, the horizontal axis in each figure shows the temperature (° C.) in the reactor during epitaxial growth. On the other hand, the vertical axis represents the number (pieces / wafer) obtained by measuring the number of stacking faults generated on the main surface of the manufactured epitaxial wafer using a particle counter (Surfscan SP1 manufactured by KLA-Tencor). FIG. 2A shows the number of stacking faults of an epitaxial wafer epitaxially grown at each of four temperatures selected from a range of 1120 ° C. to 1160 ° C. with the growth rate fixed at 5.0 μm / min. FIG. 2B shows the number of stacking faults of an epitaxial wafer epitaxially grown at each of five temperatures selected at a temperature ranging from 1100 ° C. to 1160 ° C. with the growth rate fixed at 4.0 μm / min. FIG. 2C shows the number of stacking faults of an epitaxial wafer epitaxially grown at each of eight temperatures selected at a temperature ranging from 1025 ° C. to 1160 ° C. with the growth rate fixed at 2.0 μm / min. FIG. 2D shows the number of stacking faults of an epitaxial wafer epitaxially grown at each of eight temperatures selected at a temperature ranging from 1025 ° C. to 1160 ° C. with the growth rate fixed at 1.0 μm / min.

  The points plotted in FIGS. 2A to 2D have a minimum point where the number of stacking faults is minimum in each figure. The number of stacking faults at this minimum point is the smallest when the growth rate is 1.0 μm / min (see the point near the temperature of 1100 ° C. in FIG. 2D). Further, when the growth rate is 1.0 μm / min, the number of stacking faults formed on the epitaxial wafer manufactured at a temperature deviating from the temperature at which the number of stacking faults becomes the minimum (around the temperature of 1100 ° C. in FIG. 2D). The numbers are almost flat over a wide range of temperatures from 1040 ° C to 1130 ° C. Furthermore, as shown in FIG. 2C, even when the growth rate is 2.0 μm / min, the number of stacking faults formed on the fabricated epitaxial wafer is almost the same over the temperature range of 1040 ° C. to 1130 ° C. It is leveling off. On the other hand, as shown in FIGS. 2A and 2B, in the epitaxial wafer manufactured at a growth rate of 4.0 μm / min or more, the number of stacking faults does not remain in a wide range, and it depends on the temperature during epitaxial growth. It changes a lot. Therefore, it is possible to suppress stacking faults by epitaxial growth at a temperature near 1100 ° C. at a low growth rate.

  In each figure of Drawing 2A-Drawing 2D, the point plotted in the field on the lowest temperature side is a point where the number of stacking faults measured overflowed. Defects at these points were mainly convex defects as shown in FIG. 3 having several tens of nm and a width of several μm. On the other hand, the defects at the points plotted in the region on the high temperature side (1160 ° C. side) in each of FIGS. 2A to 2D were stacking faults and minute pits of submicron shown in FIG. These defects are not seen except in the low resistivity substrate doped with red phosphorus, and are a phenomenon peculiar to this substrate.

  From the above, by setting the growth rate during epitaxial growth to 2 μm / min or less and the temperature during the growth to 1040 ° C. or more and 1130 ° C. or less, an epitaxial wafer that suppresses the occurrence of stacking faults can be manufactured. Preferably, the growth rate during epitaxial growth is 2 μm / min or less, and the temperature during growth is 1060 ° C. or more and 1120 ° C. or less. More preferably, the growth rate during epitaxial growth is 1 μm / min or less, and the temperature during growth is 1060 ° C. or more and 1120 ° C. or less.

  As shown in FIG. 5, after performing the baking step (S1) to the purging step (S3) on the substrate W as in FIG. 1, the first and second steps are performed instead of the growth step (S4) in FIG. The growth step (S4a, S4b) may be performed. In the first growth step (S4a), the growth rate of the epitaxial layer during epitaxial growth is set to 2.0 μm / min or less, the temperature during the growth is set to 1040 ° C. or more and 1130 ° C. or less, and the substrate W is non-doped epitaxial layer. Is epitaxially grown. Thereafter, as the second growth step (S4b), the epitaxial layer is grown at a growth rate (for example, 4.0 μm / min) exceeding the growth rate of the first growth step (S4a) until the epitaxial layer has a predetermined thickness. In the first growth step (S4a), it takes time to grow the epitaxial layer, and the productivity is greatly reduced. Therefore, by performing the second growth step (S4b) after the first growth step (S4a), it is possible to manufacture an epitaxial wafer in which stacking faults are suppressed without significantly reducing productivity.

  EXAMPLES Hereinafter, although an Example and a comparative example are given and this invention is demonstrated concretely, these do not limit this invention.

(Example)
In Example 1, two substrates W having a diameter of 200 mm and a thickness of 735 μm having a resistivity of 0.71 mΩ · cm to 0.74 mΩ · cm and a mirror-polished main surface were prepared. Next, steps S1 to S4 shown in FIG. 1 were performed on each of the prepared two substrates W using a vapor phase growth apparatus, and two silicon epitaxial wafers were produced. As manufacturing conditions, in the etching step of S2, the etching rate was set to 0.090 μm / min, and the etching amount was set to 0.045 μm. In the purge step of S3, hydrogen gas was flowed at 1130 ° C. for 30 seconds. In the growth step of S4, a silicon epitaxial layer having a thickness of 2.1 μm was grown at a growth rate of 1.0 μm / min and a temperature of 1100 ° C. The produced epitaxial wafer was measured with a particle counter (Surfscan SP1 manufactured by KLA-Tencor), and the number of stacking faults (pieces / wafer) generated on the epitaxial wafer was measured.

  In the second embodiment, the process is the same as that in the first embodiment until the purge process (S3) in FIG. 1, and then the first and second growth processes (S4a, S4b in FIG. 5) instead of the growth process (S4) in FIG. ). In the first growth step of S4a, an epitaxial layer having a thickness of 0.1 μm was grown at a growth rate of 1.0 μm / min and a temperature of 1100 ° C. Next, in the second growth step of S4b, an epitaxial layer having a thickness of 2 μm was grown at a growth rate of 4.0 μm / min and a temperature of 1150 ° C. Thus, the epitaxial wafer was produced and the number of stacking faults (pieces / wafer) generated in the epitaxial wafer produced in the same manner as in Example 1 was measured.

(Comparative example)
In the comparative example, the process up to the purge step (S3) in FIG. 1 is performed in the same manner as in Example 1, and then the growth rate is set to 4.0 μm / min and the temperature is set to 1150 ° C. instead of the growth step (S4) in FIG. An epitaxial process was performed by growing an epitaxial layer having a thickness of 2.1 μm. And the number (piece / wafer) of the stacking fault which generate | occur | produced in the epitaxial wafer produced similarly to Example 1 was measured.

  FIG. 6 shows the number of stacking faults generated in the epitaxial wafers produced in Examples 1 and 2 and the comparative example. In Example 1, the number of stacking faults is 348 (pieces / wafer) and 324 (pieces / wafer). In Example 2, the number of stacking faults is 222 (pieces / wafer) and 172 (pieces / wafer). is there. On the other hand, in the comparative example, the number of stacking faults was 4348 (pieces / wafer) and 3820 (pieces / wafer).

  As shown in FIG. 6, when the growth rate exceeds 2 μm / min as in the comparative example, the number of stacking faults is not sufficiently suppressed, whereas the growth rate is 2 μm / min or less as in Example 1, If the temperature during growth is 1100 ° C., the number of stacking faults can be sufficiently suppressed. Further, after growing an epitaxial layer under the same conditions as in Example 1 (growth rate is 2 μm / min or less and temperature is 1100 ° C.) as in Example 2, the epitaxial layer is grown at a higher growth rate than that. Even in the case of growth, the number of stacking faults was sufficiently suppressed. Therefore, it is possible to manufacture an epitaxial wafer in which the number of stacking faults is suppressed with increased production efficiency.

  The embodiments of the present invention have been described above. However, the present invention is not limited to the specific description, and the illustrated configurations and the like can be appropriately combined within a technically consistent range. In addition, certain elements and processes may be replaced with known forms.

  W substrate (silicon single crystal substrate)

Claims (5)

Preparing a silicon single crystal substrate doped with phosphorus of 5 × 10 ¹⁹ atoms / cm ³ or more;
A first step of growing an epitaxial layer on the silicon single crystal substrate at a growth rate of 2 μm / min or less at a temperature of 1040 ° C. or more and 1130 ° C. or less;
A second step of growing an epitaxial layer on the epitaxial layer at a growth rate exceeding the growth rate after the first step;
Equipped with a,
In the second step, an epitaxial layer having a thickness larger than that of the epitaxial layer grown in the first step is grown . 2. The method for producing an epitaxial wafer according to claim 1, wherein in the preparing step, the silicon single crystal substrate doped with 8 × 10 ¹⁹ atoms / cm ³ or more of phosphorus is prepared.   The manufacturing method of the epitaxial wafer of Claim 1 or 2 provided with the process of carrying out the vapor phase etching of the main surface of the said silicon single crystal substrate with hydrogen chloride gas between the said process to prepare and the said 1st process.   4. The method for producing an epitaxial wafer according to claim 3, wherein in the step of performing vapor phase etching, an etching amount is 0.025 μm or more and 1.000 μm or less. 5. The method for manufacturing an epitaxial wafer according to claim 1, wherein in the first step, the epitaxial layer is grown at a temperature of 1060 ° C. or more and 1120 ° C. or less and a growth rate of 1 μm / min or less.