KR102521336B1 - Manufacturing method of epitaxial wafer - Google Patents

Abstract

A manufacturing method of an epitaxial wafer includes a preparing step and a growing step. In the preparation process, a substrate W having low resistivity doped with red phosphorus is prepared. The substrate W is doped with 5×10 ¹⁹ atoms/cm ³ or more of phosphorus as a dopant. In the growing process, the epitaxial layer is grown on the substrate W at a temperature of 1040° C. or more and 1130° C. or less at a growth rate of 2 μm/min or less. Thus, a method for manufacturing an epitaxial wafer capable of suppressing stacking faults is provided.

Description

Manufacturing method of epitaxial wafer

The present invention relates to a method for manufacturing epitaxial wafers.

For example, epitaxial wafers are used as substrates for semiconductor devices used in mobile terminals and the like. In such a semiconductor device, it is required to reduce the on-resistance due to the demand for power saving. As a specific method of lowering the on-resistance, there are methods of thinning the semiconductor device substrate and methods of reducing the resistivity of the semiconductor device substrate, but there is a limit to thinning the semiconductor device substrate due to the characteristics of the device of the semiconductor device. Therefore, an epitaxial layer is grown on a low-resistivity silicon single crystal substrate doped with a dopant at a high concentration to produce a low-resistivity epitaxial wafer serving as a semiconductor device substrate. As such an epitaxial wafer, Patent Documents 1 to 3 disclose an epitaxial wafer in which an epitaxial layer is grown on a low-resistivity semiconductor substrate.

A silicon single crystal substrate, which is the source of such an epitaxial wafer, is manufactured from an ingot raised by doping with a high concentration of dopant. However, when an n-type dopant such as Sb (antimony) or As (arsenic) is used for this dopant, the doped dopant evaporates during pulling. Therefore, if the silicon single crystal substrate on which the epitaxial layer is grown is n-type, a silicon single crystal substrate doped with relatively low volatility phosphorus (red phosphorus) as a dopant is used. Then, an epitaxial wafer having low resistivity is manufactured by vapor phase growing an epitaxial layer on the main surface of the prepared silicon single crystal substrate.

However, when an epitaxial layer is grown on a low-resistivity silicon single crystal substrate doped with high phosphorus concentration, many stacking faults (stacking faults) occur on the main surface of the epitaxial wafer after vapor phase growth. When a semiconductor element is fabricated using the epitaxial wafer having the stacking fault, the characteristics (mainly withstand voltage characteristic) of the semiconductor element (device) are deteriorated. Therefore, it is necessary to reduce the number of occurrences of stacking faults to a level that does not affect device characteristics.

The stacking fault observed on the main surface of the epitaxial wafer is observed by propagating to the main surface of the epitaxial wafer starting from a crystal defect or the like generated in a low-resistivity silicon single crystal substrate. Since this stacking fault tends to increase as the resistivity of the silicon single crystal substrate decreases, it is thought that phosphorus, which is a dopant, is involved in the formation of the stacking fault.

Therefore, before growing an epitaxial layer on a low-resistivity silicon single crystal substrate, a major surface of the silicon single crystal substrate is vapor-phase etched with hydrogen chloride gas to clean the substrate surface, thereby suppressing the occurrence of stacking faults.

Japanese Unexamined Patent Publication No. 2012-156303 Japanese Unexamined Patent Publication No. 2014-82242 Japanese Unexamined Patent Publication No. 2005-79134

However, even when an epitaxial layer is grown on a low-resistivity silicon single crystal substrate subjected to such vapor phase etching, stacking faults at concentrations adversely affecting the characteristics of semiconductor devices may occur in the epitaxial wafer.

An object of the present invention is to provide a method for manufacturing an epitaxial wafer capable of suppressing stacking faults.

(Means for Solving Problems and Effects of Invention)

The manufacturing method of the epitaxial wafer of the present invention,

A step of preparing a low-resistivity silicon single crystal substrate doped with phosphorus;

A process of growing an epitaxial layer at a growth rate of 2 μm/min or less on a silicon single crystal substrate at a temperature of 1040 ° C. or more and 1130 ° C. or less

It is characterized by having a.

In the epitaxial wafer manufacturing method of the present invention, since an epitaxial layer is grown on a low-resistivity silicon single crystal substrate by the above growing step, stacking faults generated during epitaxial growth can be suppressed. In addition, when the temperature is set to a low temperature of less than 1040° C. in the growth step, an explosive number of convex defects with a height of several tens of nm and a width of several μm are formed on the epitaxial wafer. On the other hand, when the temperature in the growing process is set to a high temperature side exceeding 1130°C, stacking faults occurring on the epitaxial wafer increase and submicron minute pits occur. These defects occur specifically when an epitaxial layer is grown on a low-resistivity silicon single crystal substrate doped with phosphorus (red phosphorus), and are thought to be caused by crystal defects formed by phosphorus, similar to stacking faults. . Since these defects also adversely affect the device characteristics of semiconductor elements, an epitaxial layer is grown on a silicon single crystal substrate in a temperature range of 1040°C or more and 1130°C or less.

In this specification, the “low-resistivity silicon single crystal substrate” may be, for example, a silicon single crystal substrate doped with 5×10 ¹⁹ atoms/cm ³ or more of phosphorus (red phosphorus), or 8×10 ¹⁹ phosphorus (red phosphorus). It may be a silicon single crystal substrate doped with atoms/cm ³ or more. In the case of using a silicon single crystal substrate doped with 8×10 ¹⁹ atoms/cm ³ or more of phosphorus (red phosphorus), stacking faults of the epitaxial wafer can be effectively reduced.

In an embodiment of the present invention, the growing process is a first process, and a second process of growing an epitaxial layer on the epitaxial layer at a growth rate exceeding the growth rate is provided after the first process.

According to this, the speed at which the epitaxial layer is grown in the second step can be increased, and an epitaxial wafer in which stacking faults are suppressed can be manufactured without significantly reducing the productivity of the epitaxial wafer.

In an embodiment of the present invention, between the preparation step and the growing step, a step of vapor phase etching the main surface of the silicon single crystal substrate with hydrogen chloride gas is provided.

According to this, the main surface of the silicon single crystal substrate can be cleaned, and the occurrence of stacking faults can be further suppressed.

In the embodiment of the present invention, in the vapor phase etching step, the etching amount is 0.025 μm or more and 1.000 μm or less.

Since the stacking fault nuclei are localized in a region of 0.025 μm or more from the surface of the silicon single crystal substrate in the depth direction of the substrate, the stacking fault nuclei can be effectively removed by setting the etching amount to 0.025 μm or more. Moreover, productivity can be improved by making etching amount into 1.000 micrometer or less.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram explaining each step (part 1) in a method for manufacturing an epitaxial wafer according to an example of the present invention.
2A is a graph showing the relationship between the number of stacking faults (pieces/wafer) generated in an epitaxial wafer in which the epitaxial layer is grown at a growth rate of 5.0 μm/min and the temperature (° C.) during epitaxial growth.
2B is a graph showing the relationship between the number of stacking faults (piece/wafer) generated in an epitaxial wafer in which the epitaxial layer is grown at a growth rate of 4.0 μm/min and the temperature (° C.) during epitaxial growth.
2C is a graph showing the relationship between the number of stacking faults (pieces/wafer) generated in an epitaxial wafer in which the epitaxial layer is grown at a growth rate of 2.0 μm/min and the temperature (° C.) during epitaxial growth.
2D is a graph showing the relationship between the number of stacking faults (piece/wafer) generated in an epitaxial wafer in which the epitaxial layer is grown at a growth rate of 1.0 μm/min and the temperature (° C.) during epitaxial growth.
Fig. 3 is a diagram showing an example of a convex defect occurring in an epitaxial wafer fabricated by setting the temperature at the time of epitaxial growth to the lowest temperature side in Figs. 2A to 2D;
Fig. 4 is a diagram showing an example of minute pits generated in an epitaxial wafer fabricated by setting the temperature at the time of epitaxial growth to the highest temperature side in Figs. 2A to 2D;
Fig. 5 is a diagram explaining each step (part 2) in the method for manufacturing an epitaxial wafer according to an example of the present invention.
6 is a graph showing the number (piece/wafer) of stacking faults generated in epitaxial wafers fabricated in Examples 1 and 2 and Comparative Example.

(Mode for implementing the invention)

Hereinafter, a method for manufacturing a silicon epitaxial wafer in which a silicon epitaxial layer is grown on a silicon single crystal substrate doped with red phosphorus will be described. Hereinafter, a method for manufacturing an epitaxial wafer using a known vapor phase growth apparatus (hereinafter referred to as "vapor phase growth apparatus") for manufacturing an epitaxial wafer will be described.

The vapor phase growth apparatus includes a reaction furnace for reacting a silicon single crystal substrate as a sample. In a state where the silicon single crystal substrate is accommodated in the reaction furnace, steps S1 to S4 shown in FIG. 1 are performed, for example, to grow an epitaxial layer on the silicon single crystal substrate in the reaction furnace, thereby manufacturing a silicon epitaxial wafer.

In order to manufacture a silicon epitaxial wafer using a vapor phase growth apparatus, first, a silicon single crystal substrate serving as a substrate for growth on which an epitaxial layer is grown is prepared. For example, polycrystalline silicon and red phosphorus for adjusting the resistivity are placed in a quartz crucible, and a seed crystal silicon rod is immersed in the liquid surface of the molten liquid and pulled up to produce a silicon single crystal ingot. Next, the produced silicon single crystal ingot is cut out to a predetermined thickness, and a silicon single crystal substrate is produced by subjecting the cut wafer to rough polishing, etching, polishing, and the like. In this silicon single crystal substrate, 5×10 ¹⁹ atoms/cm ³ or more of red phosphorus is added as a dopant during production of a silicon single crystal ingot (for example, 1×10 ²⁰ atoms/cm ³ of red phosphorus is added). Hereinafter, a silicon single crystal substrate to which red phosphorus is added as a dopant at 5×10 ¹⁹ atoms/cm ³ or more is used as the substrate W.

The produced substrate W is conveyed to the reaction furnace of the vapor phase growth apparatus, and a series of steps shown in FIG. 1 are performed. The substrate W transported to the reaction furnace is put into a reaction furnace using hydrogen as an atmospheric gas. The substrate W put into the reaction furnace is subjected to a bake process (S1) in which the substrate W is heated for several tens of seconds at a temperature of, for example, 1100° C. or higher by a vapor phase growth device, so that the native oxide film on the surface of the substrate W is removed.

Next, an etching process of subjecting the substrate W to vapor phase etching is performed (S2). In the etching process, hydrogen chloride gas (HCl gas) is supplied onto the main surface of the substrate W in the reactor, and the main surface of the substrate W is etched in the vapor phase. Specifically, the supply time and supply amount of the hydrogen chloride gas are set so that the etching amount is 0.025 μm or more and 1.000 μm or less. Since stacking fault nuclei are localized in a region of 0.025 μm or more in the depth direction (thickness direction) of the substrate W from the main surface of the substrate W, stacking faults can be effectively suppressed by etching amount of 0.025 μm or more. On the other hand, if the etching amount exceeds 1.000 μm, the productivity of producing epitaxial wafers decreases, so the etching amount is set within a range of 0.025 μm or more and 1.000 μm or less. In addition, the etching rate is set to be, for example, 0.04 μm/min or more and 0.37 μm/min or less.

When the etching step of S2 is completed, a purge step (S3) of discharging the hydrogen chloride gas in the reactor to the outside of the reactor is performed.

When the purge process of S3 is completed, a growth process (S4) of growing an epitaxial layer on the substrate W is performed. In the growth step, trichlorosilane (TCS) as a source gas, for example, and hydrogen gas as a carrier gas for diluting the trichlorosilane are supplied to the main surface of the substrate W in the reaction furnace; An epitaxial layer is vapor grown on the main surface of the substrate W. Specifically, the temperature in the reaction furnace (substrate W) is maintained at a predetermined temperature of, for example, 1040 ° C. or higher and 1130 ° C. or lower (eg, maintained at 1100 ° C.), and the epitaxial layer grow at a growth rate of 2 µm/min or less. In this way, an epitaxial layer having a predetermined film thickness is grown on the substrate W, and a silicon epitaxial wafer is manufactured.

In the above, a series of flows of manufacturing an epitaxial wafer by growing an epitaxial layer on the substrate W have been described. In the substrate W, which is the source of such an epitaxial wafer, red phosphorus as a dopant is added at 5×10 ¹⁹ atoms/cm ³ or more (eg, 1×10 ²⁰ atoms/cm ³ ) during fabrication of a silicon single crystal ingot. For this reason, a large number of stacking fault nuclei exist on the main surface of the substrate W. Therefore, when an epitaxial layer is grown on the substrate W, stacking fault nuclei on the main surface of the substrate W cause stacking faults in the epitaxial wafer. Therefore, the main surface of the substrate W on which the stacking fault nucleus exists is removed in the etching step of S2 shown in FIG. 1 to remove the stacking fault nucleus.

Although stacking fault nuclei on the main surface of the substrate W are significantly removed by etching the main surface of the substrate W, some stacking fault nuclei are still formed in the form of minute pits, for example, on the substrate ( W) remains. Therefore, even if an epitaxial layer is grown on the substrate W after etching, for example, stacking fault nuclei on the main surface of the substrate W or the like may cause stacking faults in the epitaxial wafer.

Therefore, the present inventors have discussed the relationship between growth conditions such as growth rate and temperature for growing an epitaxial layer on a substrate W, and the number (piece/wafer) of stacking faults formed on an epitaxial wafer grown under the growth conditions. meticulously investigated. The detailed investigation results are shown in FIGS. 2A to 2D. 2A to 2D, the growth rate during epitaxial growth is different for each drawing, and the number of stacking faults in the epitaxial wafer produced by setting the temperature during epitaxial growth to a temperature selected from the range of 1000 ° C. to 1160 ° C. ( dog/wafer) is shown. In the epitaxial wafer fabricated in each drawing, an epitaxial layer having a layer thickness of 3 μm is grown on a substrate W having a diameter of 200 mm, a thickness of 735 μm, and a concentration of red phosphorus of 1×10 ²⁰ atoms/cm ³ . In addition, the horizontal axis in each figure represents the temperature (° C.) in the reaction furnace during epitaxial growth. On the other hand, the vertical axis represents the number (piece/wafer) of the number of stacking faults generated on the main surface of the produced epitaxial wafer measured by a particle counter (Surfscan SP1 manufactured by KLA-Tencor). FIG. 2A shows the number of stacking faults of an epitaxial wafer grown epitaxially at each of four temperatures selected from the range of 1120° C. to 1160° C. with the growth rate fixed at 5.0 μm/min. FIG. 2B shows the number of stacking faults of an epitaxial wafer grown epitaxially at each of five temperatures selected from the range of 1100° C. to 1160° C. with the growth rate fixed at 4.0 μm/min. FIG. 2C shows the number of stacking faults of an epitaxial wafer grown epitaxially at each of eight temperatures selected from the range of 1025° C. to 1160° C. with the growth rate fixed at 2.0 μm/min. FIG. 2D shows the number of stacking faults of an epitaxial wafer grown epitaxially at each of eight temperatures selected from the range of 1025° C. to 1160° C. with the growth rate fixed at 1.0 μm/min.

The points drawn in FIGS. 2A to 2D have a minimum point at which the number of stacking faults is minimum in each drawing. The number of stacking faults at this minimum point is the smallest when the growth rate is 1.0 μm/min (see the point near the temperature of 1100° C. in FIG. 2D). Further, when the growth rate is 1.0 μm/min, the number of stacking faults formed in the epitaxial wafer fabricated at a temperature deviating from the temperature at which the number of stacking faults is minimized (temperature around 1100° C. in FIG. 2D) is 1040° C. Over a wide range of -1130 ° C, it becomes almost unchanged form. Also, as shown in FIG. 2C, similarly when the growth rate is 2.0 µm/min, the number of stacking faults formed on the fabricated epitaxial wafer varies substantially over the temperature range of 1040°C to 1130°C. It is in the form of no. On the other hand, as shown in FIGS. 2A and 2B , in an epitaxial wafer produced at a growth rate of 4.0 μm/min or more, the number of stacking faults does not fluctuate over a wide range and varies depending on the temperature during epitaxial growth. It changes greatly. For this reason, it is possible to suppress stacking faults by performing epitaxial growth at a temperature of around 1100° C. at a low growth rate.

In each drawing of FIGS. 2A to 2D , the point drawn in the region at the lowest temperature is the point at which the number of stacking faults measured overflows. Defects at these points were mainly convex defects of several tens of nm and several μm in width as shown in FIG. 3 . Conversely, defects at the points drawn in the high-temperature side (1160°C side) region in each of FIGS. 2A to 2D were stacking faults and minute pits of submicron shown in FIG. 4 . These defects are not seen except for low-resistivity substrates doped with red phosphorus, and are unique to this substrate.

From the above, by setting the growth rate during epitaxial growth to 2 μm/min or less and the temperature during growth to 1040° C. or more and 1130° C. or less, an epitaxial wafer suppressing the occurrence of stacking faults can be manufactured. . Preferably, the growth rate during epitaxial growth is 2 µm/min or less, and the temperature during growth is 1060°C or higher and 1120°C or lower. More preferably, the growth rate during epitaxial growth is 1 µm/min or less, and the temperature during growth is 1060°C or higher and 1120°C or lower.

In addition, as shown in FIG. 5, after the substrate W is subjected to a bake step (S1) and a purge step (S3) as in FIG. 1, the first and second growth steps (S4) in FIG. You may perform the growth process (S4a, S4b). In the first growth step (S4a), the growth rate of the epitaxial layer during epitaxial growth is set to 2.0 μm/min or less, and the temperature during the growth is set to 1040° C. or more and 1130° C. or less, so that the substrate W is free from moisture. A doped epitaxial layer is epitaxially grown. Thereafter, as the second growth step S4b, at a growth rate exceeding the growth rate of the first growth step S4a (for example, 4.0 µm/min) until the epitaxial layer reaches a predetermined film thickness. grow In the first growth process (S4a), it takes time to grow the epitaxial layer, and productivity is greatly reduced. Therefore, by carrying out the second growth step S4b after the first growth step S4a, it is possible to manufacture an epitaxial wafer in which stacking faults are suppressed without significantly reducing productivity.

Example

Hereinafter, the present invention will be specifically described by way of Examples and Comparative Examples, but these are not intended to limit the present invention.

(Example)

In Example 1, two substrates W having a diameter of 200 mm and a thickness of 735 µm, the main surfaces of which have a resistivity of 0.71 mΩ·cm to 0.74 mΩ·cm, were mirror-polished. Next, steps S1 to S4 shown in FIG. 1 were performed on each of the prepared two substrates W using a vapor phase growth apparatus, thereby fabricating two silicon epitaxial wafers. As production conditions, in the etching step of S2, the etching rate was set to 0.090 µm/min and the etching amount was set to 0.045 µm. Further, in the purge step of S3, hydrogen gas was flowed at 1130°C for 30 seconds. In the growth step of S4, a silicon epitaxial layer having a thickness of 2.1 μm was grown at a growth rate of 1.0 μm/min and a temperature of 1100° C. Then, the produced epitaxial wafer was measured with a particle counter (Surfscan SP1 manufactured by KLA-Tencor), and the number of stacking faults (piece/wafer) generated in the epitaxial wafer was measured.

In Example 2, the purge process (S3) in FIG. 1 is the same as in Example 1, and then the first and second growth processes (S4a, S4b) in FIG. 5 are performed instead of the growth process (S4) in FIG. carried out. In the first growth step of S4a, an epitaxial layer having a thickness of 0.1 μm was grown at a growth rate of 1.0 μm/min and a temperature of 1100° C. Next, in the second growth step of S4b, an epitaxial layer having a thickness of 2 μm was grown at a growth rate of 4.0 μm/min and a temperature of 1150° C. In this way, an epitaxial wafer was fabricated, and the number of stacking faults (piece/wafer) generated in the epitaxial wafer fabricated in the same manner as in Example 1 was measured.

(Comparative example)

In the comparative example, up to the purge step (S3) in FIG. 1 was performed in the same manner as in Example 1, and then, instead of the growth step (S4) in FIG. 1, the growth rate was 4.0 μm/min and the temperature was 1150° C. An epitaxial wafer was fabricated by performing a growth step of growing an epitaxial layer having a thickness of 2.1 µm. Then, as in Example 1, the number of stacking faults (piece/wafer) generated in the fabricated epitaxial wafer was measured.

6 shows the number of stacking faults generated in the epitaxial wafers fabricated in Examples 1 and 2 and Comparative Example. In Example 1, the number of stacking faults is 348 (piece/wafer) and 324 (piece/wafer), and in Example 2, the number of stacking faults is 222 (piece/wafer) and 172 (piece/wafer). On the other hand, in the comparative example, the number of stacking faults was 4348 (piece/wafer) and 3820 (piece/wafer).

As shown in FIG. 6 , when the growth rate exceeds 2 μm/min as in the comparative example, the number of stacking faults is not sufficiently suppressed, whereas in Example 1 the growth rate is 2 μm/min or less and the growth rate is 2 μm/min or less. When the temperature during the test is 1100°C, the number of stacking faults can be sufficiently suppressed. In addition, as in Example 2, after growing the epitaxial layer under the same conditions as in Example 1 (growth rate of 2 μm/min or less, and temperature of 1100 ° C.), the epitaxial layer was grown at a higher growth rate than that Even in the case of growth, the number of stacking faults could be sufficiently suppressed. Therefore, it is possible to manufacture an epitaxial wafer in which the number of stacking faults is suppressed while increasing the production efficiency.

Above, the embodiments of the present invention have been described, but the present invention is not limited to the specific description, and it is also possible to implement the exemplified configurations and the like in appropriate combinations within a technically consistent range, and certain elements and processes are notified. It can also be implemented by substituting in the form of.

W substrate (silicon single crystal substrate)

Claims (6)

A step of preparing a silicon single crystal substrate doped with 5×10 ¹⁹ atoms/cm ³ or more of phosphorus;
A first step of growing an epitaxial layer on the silicon single crystal substrate at a temperature of 1040 ° C. or more and 1130 ° C. or less at a growth rate of 2 μm / min or less;
A second step of growing an epitaxial layer on the epitaxial layer at a growth rate exceeding the growth rate after the first step,
In the second step, an epitaxial layer having a thickness greater than that of the epitaxial layer grown in the first step is grown. According to claim 1,
The method of manufacturing an epitaxial wafer, characterized in that the preparing step prepares the silicon single crystal substrate doped with 8×10 ¹⁹ atoms/cm ³ or more of phosphorus. According to claim 1 or 2,
Between the preparation step and the first step, a step of vapor phase etching the main surface of the silicon single crystal substrate with hydrogen chloride gas is provided. According to claim 3,
The method for manufacturing an epitaxial wafer according to claim 1, wherein, in the vapor phase etching step, the etching amount is 0.025 μm or more and 1.000 μm or less.
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