JP6369388B2 - Evaluation method of silicon single crystal substrate - Google Patents

Description

  The present invention relates to a method for evaluating a silicon single crystal substrate.

  For example, an epitaxial wafer is used for a semiconductor device having a MOS (Metal Oxide Semiconductor) structure used for a standby power supply (mobile power supply) used by connecting to a mobile terminal. From the viewpoint of power saving in recent years, it is required to make the resistivity of a substrate used for such an epitaxial wafer extremely low.

  When growing a silicon single crystal ingot having a very low resistivity, for example, an n-type substrate (silicon single crystal substrate), phosphorus (red phosphorus) having low volatility among n-type dopant species is used as a dopant. As a high concentration. By adjusting the added red phosphorus, the resistivity of the silicon substrate obtained from the silicon single crystal ingot is adjusted. For example, when an epitaxial layer is grown on a silicon substrate having a resistivity of 0.8 mΩ · cm or less by adjusting the added red phosphorus, a stacking fault (stacking fault) is likely to occur during the growth of the epitaxial layer. When a semiconductor device is manufactured using an epitaxial wafer in which such a stacking fault has occurred, the characteristics of the semiconductor device are adversely affected. Therefore, it is necessary to control the quality of the epitaxial wafer so that the number of stacking faults generated in the epitaxial wafer used for the semiconductor device is a certain number or less.

  The generation source of the stacking faults generated in the epitaxial wafer is presumed to be a crystal defect related to red phosphorus because red phosphorus is added at a high concentration when growing the ingot. The silicon substrate used for the epitaxial wafer is mirror-polished (polished wafer state), and the following defect inspection devices are widely used as devices for detecting crystal defects from the surface of such a silicon substrate. ing. Specifically, Surfscan SP1 manufactured by KLA-Tencor and MAGICS manufactured by Lasertec are widely used as apparatuses for measuring crystal defects on a polished wafer. However, even if these apparatuses are used, crystal defects cannot be detected from a silicon substrate having a resistivity of 0.8 mΩ · cm or less by adding red phosphorus.

  Further, there is a method of detecting defects by selectively etching the surface of a silicon substrate in a polished wafer state to reveal crystal defects or the like on the surface of the silicon substrate, measuring an LPD (Light Point Defect) density. However, in the case of a silicon substrate in which red phosphorus is added and the resistivity is 0.8 mΩ · cm or less, the target crystal can be obtained even if general HF (hydrogen fluoride), nitric acid, and acetic acid-based etching is used as a selective etching solution. Defects do not appear.

  Therefore, the crystal defect of the silicon substrate that is considered to cause a stacking fault in the epitaxial wafer cannot be confirmed directly from the silicon substrate. Therefore, in order to evaluate the crystal defects (quality) of the silicon substrate, it is necessary to confirm the number of stacking faults generated in the epitaxial wafer by growing an epitaxial layer on the silicon substrate, which is very inconvenient. For example, Patent Document 1 discloses a method for detecting crystal defects in a silicon substrate by confirming crystal defects in the epitaxial layer grown on the silicon substrate.

  On the other hand, Patent Document 2 discloses a method of directly detecting a crystal defect of a silicon substrate from the silicon substrate by performing a heat treatment on the silicon substrate without growing an epitaxial layer on the silicon substrate.

International Publication No. 2001/048810 JP 2007-019226 A

  However, the method of Patent Document 2 does not evaluate defects in a silicon substrate to which red phosphorus is added so that the resistivity is 0.8 mΩ · cm or less.

  An object of the present invention is to provide a silicon single crystal substrate evaluation method capable of evaluating the quality of a silicon single crystal substrate having a resistivity of 0.8 mΩ · cm or less with the addition of red phosphorus.

Means for Solving the Problems and Effects of the Invention

The method for evaluating a silicon single crystal substrate of the present invention is as follows.
A heat treatment step in which heat treatment is performed for 30 seconds or more at a temperature of 1050 ° C. or higher in an atmosphere gas having an etching action on a silicon single crystal substrate having a resistivity of 0.8 mΩ · cm or less added with red phosphorus as a dopant;
An evaluation step for evaluating the quality of the silicon single crystal substrate based on the number of defects formed on the surface of the silicon single crystal substrate by the heat treatment step;
It is characterized by providing.

  When red phosphorus is added as a dopant to grow an epitaxial layer on a silicon single crystal substrate having a resistivity of 0.8 mΩ · cm or less, stacking faults are likely to occur in the epitaxial layer due to the added red phosphorus. This stacking fault is presumed to be caused by crystal defects related to red phosphorus in the silicon single crystal substrate because red phosphorus is added to the silicon single crystal substrate on which the epitaxial layer is grown. Further, when an epitaxial wafer in which such a stacking fault has occurred is used for a semiconductor device, the device characteristics are adversely affected. Therefore, at the time of the silicon single crystal substrate, it is desired to easily evaluate the degree of stacking fault (quality of the silicon single crystal substrate) when the silicon single crystal substrate becomes an epitaxial wafer in the future. .

  Therefore, the present inventor detects a crystal defect related to red phosphorus, which is estimated to cause a stacking fault in the future in a silicon single crystal substrate having a resistivity of 0.8 mΩ · cm or less when red phosphorus is added. Because of trial and error. As a result, it has been found that the defect that is a generation source of the stacking fault can be formed on the surface of the silicon single crystal substrate under the condition of heat-treating the silicon single crystal substrate. That is, heat treatment is performed for 30 seconds or more at a temperature of 1050 ° C. or higher with an atmospheric gas having an etching action on a silicon single crystal substrate having a resistivity of 0.8 mΩ · cm or less added with red phosphorus. By doing so, it is possible to make a defect that is a source of stacking faults manifest on the surface of the silicon single crystal substrate. Therefore, the quality of the silicon single crystal substrate can be easily evaluated based on this defect. If the heat treatment time is less than 30 seconds, the number of defects formed in the silicon single crystal substrate varies. Therefore, by performing the heat treatment for 30 seconds or more, the defects that are the source of stacking faults can be appropriately detected. It becomes possible to form.

  Furthermore, the present inventor conducted extensive studies based on heat treatment conditions that cause defects in the silicon single crystal substrate. As a result, the conclusion is that the number of defects formed in the silicon single crystal substrate by the heat treatment and the number of stacking faults formed by growing an epitaxial layer on the silicon single crystal substrate have a linear correlation. Reached.

  Therefore, it is possible to obtain the number of stacking faults that are predicted to occur when an epitaxial layer is grown on the silicon single crystal substrate based on the defects formed on the silicon single crystal substrate subjected to the heat treatment. That is, as the quality of the silicon single crystal substrate, it is possible to evaluate the number of stacking faults that are expected to occur when an epitaxial layer is grown on the silicon single crystal substrate.

  In the embodiment of the present invention, the heat treatment step is performed for 60 seconds or more. When the heat treatment is performed for 60 seconds or more, it is effective to stabilize the number of defects formed in the silicon single crystal substrate.

The number of defects formed on the surface of the silicon single crystal substrate by the heat treatment of the example and the comparative example, and the number of stacking faults formed by growing an epitaxial layer on the silicon single crystal substrate by the epitaxial growth of the example and the comparative example Graph showing. 6 is a graph showing the correlation between the number of defects formed on the surface of a silicon single crystal substrate by heat treatment and the number of stacking faults formed by growing an epitaxial layer on the silicon single crystal substrate.

  Hereinafter, an example of the evaluation method of the present invention for evaluating the quality of a silicon single crystal substrate having a resistivity of 0.8 mΩ · cm or less by adding red phosphorus as a dopant will be described. In this embodiment, a known heat treatment apparatus and defect inspection apparatus are used to evaluate the quality of the silicon single crystal substrate.

  As a known heat treatment apparatus, a heat treatment furnace for heat treating a silicon single crystal substrate is provided. At the time of heat treatment, for example, the inside of the heat treatment furnace is replaced with hydrogen gas, argon gas, or a mixed gas thereof, and the inside of the heat treatment furnace is heated to, for example, 1050 ° C. or more and 1150 ° C. or less.

  As a known defect inspection apparatus, for example, Surfscan SP1 manufactured by KLA-Tencor, MAGICS manufactured by Lasertec, or the like is used as an apparatus for detecting defects formed on the surface of a silicon single crystal substrate.

  Using the above heat treatment apparatus and defect inspection apparatus, the quality of a silicon single crystal substrate having a resistivity of 0.8 mΩ · cm or less when red phosphorus is added as a dopant is evaluated.

  First, a silicon single crystal substrate for quality evaluation is produced. For example, a silicon single crystal ingot is produced by immersing and pulling up a seed crystal silicon rod on the surface of a melt obtained by adding polycrystalline silicon and red phosphorus for adjusting resistivity in a quartz crucible and melting it. Next, the produced silicon single crystal ingot is cut to a predetermined thickness, and the cut wafer is subjected to rough polishing, etching, polishing, etc., and the surface is mirror-finished (polished wafer state). A plurality of substrates are manufactured. This silicon single crystal substrate is adjusted to have a resistivity of 0.8 mΩ · cm or less by red phosphorus added as a dopant during the production of the silicon single crystal ingot. Hereinafter, a silicon single crystal substrate to which red phosphorus is added and the resistivity is adjusted to 0.8 mΩ · cm or less is referred to as a substrate W. Note that the silicon single crystal ingot that is the base of the substrate W is not limited to the CZ method described above, and other methods such as the FZ method may be employed.

  The produced substrate W is transferred to a heat treatment apparatus and subjected to heat treatment. When the substrate W is transferred into the heat treatment furnace, the inside of the furnace is set to a hydrogen gas atmosphere at 1130 ° C., for example, and the substrate W is subjected to heat treatment for a predetermined time (for example, 60 seconds).

  When heat treatment is performed on the substrate W, hydrogen gas (atmosphere gas) selectively etches the surface of the substrate W, so that defects (pits) are manifested on the surface of the substrate W. Then, the number of defects manifested on the surface of the heat-treated substrate W is measured by a defect inspection apparatus (for example, MAGICS).

  Next, the quality of the substrate W is evaluated based on the number of defects on the surface of the substrate W thus measured. When an epitaxial layer is grown on the substrate W as in this embodiment, stacking faults are likely to occur in the epitaxial layer due to red phosphorus added to the substrate W. When an epitaxial wafer in which such a stacking fault has occurred is used in a semiconductor device, the device characteristics are adversely affected. Therefore, it is necessary to evaluate the degree of stacking fault (evaluation of the quality of the substrate W) when the substrate W becomes an epitaxial wafer in the future at the time of the substrate W before growing the epitaxial layer.

  The inventor made trial and error in order to evaluate the number of stacking faults generated when an epitaxial layer is grown on the substrate W from the number of defects formed on the surface of the substrate W that has been subjected to the heat treatment. Among them, it has been found that the number of defects formed in the substrate W by heat treatment under predetermined conditions and the number of stacking faults generated during the growth of the epitaxial layer have a proportional correlation. Specifically, the number of defects formed on the surface of the substrate W that has been heat-treated for 30 seconds or more at a temperature of 1050 ° C. or more with an atmospheric gas having an etching action, and the stacking produced by growing an epitaxial layer on the substrate W There is a proportional correlation in the number of defects. This correlation can be determined as follows, for example.

  A set of a plurality of substrates W having a resistivity of 0.8 mΩ · cm or less and a substrate W ′ cut out from an adjacent portion of each substrate W in the same ingot that is the basis of each substrate W was prepared first. A plurality of substrates W are subjected to a heat treatment for 30 seconds or more at a temperature of 1050 ° C. or higher with an atmospheric gas having an etching action (the substrates W are subjected to a heat treatment under the same conditions). Next, the number of defects manifested on the surface of each substrate W by the heat treatment is measured, and a plurality of substrates W having different numbers of measured defects are selected. For example, three substrates W with the measured number of defects around 1000 (pieces / wafer), around 2000 (pieces / wafer), and around 3000 (pieces / wafer) are selected. Next, an epitaxial layer is grown on the substrate W ′ paired with the three selected substrates W under the same growth conditions, and the stacking fault generated in the grown epitaxial layer is measured by a defect inspection apparatus such as MAGICS. Get the number of. For example, the number of stacking faults of the acquired substrate W ′ is the vertical axis, and the number of defects that are manifested on the surface of the substrate W by the heat treatment is the horizontal axis, corresponding to the selected three substrates W and the three substrates W. The correlation between the number of stacking faults and the number of defects can be acquired by plotting the data acquired from the set of the substrates W ′. As a specific correlation, for example, a correlation such as the graph of FIG. 2 described in the following embodiment can be acquired. Therefore, the quality of the substrate W (the number of stacking faults) can be evaluated based on the number of defects on the surface of the substrate W that has been heat-treated at a temperature of 1050 ° C. or higher for 30 seconds or more with an atmospheric gas having an etching action.

  EXAMPLES Hereinafter, although an Example and a comparative example are given and this invention is demonstrated concretely, these do not limit this invention.

(Comparative example)
A plurality of sets of substrates W in a polished wafer state in which red phosphorus is added as a dopant and having a resistivity of 0.8 mΩ · cm or less and substrates W ′ cut from adjacent portions of the same ingot were prepared. First, each prepared substrate W was heat-treated with a heat treatment apparatus. Specifically, each substrate W was subjected to heat treatment at 1130 ° C. for 20 seconds in a hydrogen gas atmosphere. The number of defects on the surface of each substrate W after the heat treatment (hereinafter referred to as “number of defects”) was measured with a defect measuring apparatus (MAGICS). For the substrate W ′ corresponding to each substrate W, an epitaxial layer was separately grown under the same conditions, and the number of stacking faults generated by growing the epitaxial layer was measured with a defect measuring apparatus (MAGICS).

(Example)
Each substrate W was subjected to heat treatment under the same conditions except that the heat treatment time was changed from 20 seconds to 60 seconds. Then, the number of defects on the surface of each substrate W is measured in the same manner as in the comparative example, and separately, the epitaxial layer is grown on the substrate W ′ corresponding to each substrate W in the same manner as in the comparative example to determine the number of stacking faults. It was measured.

  Furthermore, in the examples, a plurality of sets of substrates W ′ having a resistivity of 0.8 mΩ · cm or less and substrates W ′ cut from adjacent portions of the same ingot were prepared. As the prepared substrate W, the number of defects that appear on the surface of the substrate W under the heat treatment conditions of the example is about 1000 (pieces / wafer), about 2000 (pieces / wafer), and about 3000 (pieces / wafer). W was prepared. Thereafter, the number of defects on the surface of the substrate W and the number of stacking faults generated by growing an epitaxial layer on the substrate W ′ corresponding to each substrate W where the defects were measured were measured in the same manner as in the above-described example. . Then, a correlation was obtained between the number of defects manifested on the surface of the substrate W and the number of stacking faults generated by growing an epitaxial layer on the substrate W ′ corresponding to each substrate W separately.

  FIG. 1 shows the number of defects (comparative examples and examples on the horizontal axis) formed on the surface of the substrate W by the heat treatment of the comparative examples and examples, and the epitaxial layers grown on the substrate W ′ in the comparative examples and examples. The number of stacking faults (the number of stacking faults on the horizontal axis) is indicated. In the comparative example, the number of defects on the surface of the substrate W was significantly smaller than the number of stacking faults in the epitaxial layer grown on the substrate W ′. Further, in the comparative example, the number of defects on the surface of the substrate W varied widely between the measured samples, and the value was not stable. On the other hand, in the example, the number of defects on the surface of the substrate W was close to the number of stacking faults in the epitaxial layer grown on the substrate W ′. Further, in the example, the number of defects on the surface of the substrate W was small among the measured samples, and the values were about the same and stabilized.

  If the heat treatment time is 20 seconds (less than 30 seconds) as in the comparative example of FIG. 1, the number of defects varies and a stable number of defects cannot be formed on the substrate W. Therefore, when the heat treatment time is 30 seconds or longer, preferably 60 seconds or longer as in the embodiment of FIG. 1, a stable number of defects can be formed on the substrate W.

  In FIG. 2, in the example, the number of defects on the surface of each substrate W obtained separately and the stacking faults generated by growing an epitaxial layer on the substrate W ′ corresponding to each substrate W are shown. The correlation (graph) obtained by the number is shown. As shown in FIG. 2, there is a proportional correlation between the number of defects on the surface of the substrate W after the heat treatment and the number of stacking faults in the epitaxial layer grown on the substrate W ′. Therefore, from this correlation, the quality of the substrate W (number of stacking faults) can be evaluated from the number of defects on the surface of the substrate W in the heat treatment.

  The embodiments of the present invention have been described above. However, the present invention is not limited to the specific description, and the illustrated configurations and the like can be appropriately combined within a technically consistent range. In addition, certain elements and processes may be replaced with known forms.

  W substrate (silicon single crystal substrate)

Claims (2)

A heat treatment step of applying heat treatment at a temperature of 1050 ° C. or more and 1150 ° C. or less for 60 seconds or more in a hydrogen gas atmosphere to a silicon single crystal substrate to which red phosphorus is added as a dopant and having a resistivity of 0.8 mΩ · cm or less;
A measuring step of measuring the number of defects formed on the surface of the silicon single crystal substrate by the heat treatment step ;
An acquisition step of obtaining a proportional correlation between the number of defects obtained by the measurement step and the number of stacking faults generated by actually growing an epitaxial layer on the silicon single crystal substrate;
Based on the number of defects obtained by performing the heat treatment step and the measurement step on the silicon single crystal substrate to be evaluated and the correlation obtained in the obtaining step, the silicon single crystal substrate is epitaxially formed. An evaluation process for evaluating the number of stacking faults expected to occur when the layer is grown ;
A method for evaluating a silicon single crystal substrate, comprising:   In the obtaining step, the plurality of silicon single crystal substrates having different numbers of the defects obtained in the measurement step are selected, and the ingot that is the basis of the first substrate that is the selected silicon single crystal substrate, An epitaxial layer is grown on a second substrate that is a silicon single crystal substrate cut out from an adjacent portion of the first substrate, and the number of stacking faults generated in the grown epitaxial layer is obtained, thereby obtaining a plurality of the first substrates. 2. The method for evaluating a silicon single crystal substrate according to claim 1, wherein a correlation between the number of defects obtained from one substrate and the number of stacking faults obtained from a plurality of the second substrates is acquired.

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