WO2011125305A1

WO2011125305A1 - Silicon epitaxial wafer, method for manufacturing silicon epitaxial wafer, and method for manufacturing semiconductor element or integrated circuit

Info

Publication number: WO2011125305A1
Application number: PCT/JP2011/001824
Authority: WO
Inventors: 彰一高見澤; 孝俊名古屋; 隆司佐山; 裕之丸山
Original assignee: 信越半導体株式会社
Priority date: 2010-04-08
Filing date: 2011-03-28
Publication date: 2011-10-13
Also published as: JPWO2011125305A1; JP5440693B2; TW201218250A

Abstract

Disclosed is a silicon epitaxial wafer having an epitaxial layer formed on a silicon substrate, wherein the silicon substrate is doped with phosphorus or boron at a concentration of 2.0×10¹⁹ atoms/cm³ or more, a CVD oxide film is formed at least on the rear surface, a carbon ion-implanted layer is formed by implanting carbon ions from the front surface, and the epitaxial layer is formed on the front surface where the carbon ion-implanted layer is formed. The silicon epitaxial wafer is composed of the epitaxial layer having a desired resistivity necessary to obtain predetermined electrical characteristics of an element, and a substrate having a lower resistivity compared with conventional substrates, and is capable of improving the electrical characteristics of a low breakdown strength power MOS, a middle breakdown strength power MOS, an image pick-up element and the like, and the silicon epitaxial wafer has auto-doping and out diffusion more strongly suppressed when performing epitaxial growing and heat treatment in an element manufacture step, compared with the conventional silicon epitaxial wafers.

Description

Silicon epitaxial wafer, silicon epitaxial wafer manufacturing method, and semiconductor device or integrated circuit manufacturing method

The present invention relates to a silicon epitaxial wafer and a method for manufacturing a silicon epitaxial wafer. Specifically, it is possible to grow a high resistance epitaxial layer with a narrow transition width on a silicon substrate having a very low resistivity with high reproducibility. For example, the present invention relates to a silicon epitaxial wafer and a method for manufacturing the same, which can realize low on-resistance while reducing variations in reverse breakdown voltage of vertical elements.

For switching transistors such as power MOS transistors and IGBTs (insulated gate bipolar transistors) that allow current to flow from the front to the back, and devices that require stabilization of device characteristics by minimizing substrate potential fluctuations, use epitaxial wafers. Most of them are used.

This is because the resistivity of the epitaxial layer having a relatively high resistivity necessary for ensuring the breakdown voltage of the element and the resistivity of the silicon substrate that becomes a parasitic resistance in the conductive state can be controlled independently.
For this reason, in particular, in a power MOS in which the resistivity of the silicon substrate strongly affects the on-resistance, the resistance of the silicon substrate has been actively reduced.

Here, in an N-type silicon substrate, red phosphorus, which can easily introduce a high concentration dopant during crystal growth, has been used as a dopant.
As a result, the resistivity of the silicon substrate of the low-voltage power MOS epitaxial wafer, which previously had a lower limit of about 5 mΩcm, has recently been lowered to 1 mΩcm or less.

However, since the diffusion coefficient of phosphorus is larger than that of arsenic and antimony, out diffusion (hereinafter also referred to as outward diffusion) occurs in the heat treatment performed during epitaxial growth or when forming a semiconductor element, and the thickness of the epitaxial layer is reduced. Since it becomes thinner, there is a problem that it is necessary to grow the epitaxial layer thicker than necessary in order to ensure a predetermined reverse breakdown voltage.

Therefore, when an N-type silicon substrate is used, arsenic and antimony with less auto-doping and out-diffusion have been used as the dopant.
However, there is a problem that the dopant which becomes electrically inactive increases when doping arsenic at a high concentration. In addition, antimony has a low solid solubility, and there is a limit to the production of crystals that are highly doped. Another problem is that crystal defects are likely to occur during crystal growth or epitaxial growth.

From such a background, since the productivity of crystals becomes extremely poor, it has not been practical or used to use these dopants in an extremely low resistance epitaxial substrate.
That is, when an N-type silicon substrate having an extremely low resistivity is used, a part of the dopant enters the interstitial position and becomes electrically inactive or cannot be dissolved in the crystal. Since it is not possible to use arsenic or antimony, which easily causes defects, it is necessary to use red phosphorus as a dopant.

In recent medium and low withstand voltage power MOSs, the element manufacturing process temperature has been lowered, and the influence of phosphorus out-diffusion is decreasing. From such a background, an epitaxial substrate of about 1 mΩcm using red phosphorus as a dopant has been used.

However, as described above, since heat treatment during device fabrication facilitates diffusion of phosphorus from the substrate side into the epitaxial layer, the region with a constant resistivity decreases. Accordingly, it is necessary to increase the thickness of the initial epitaxial layer. This has the opposite result to the reduction of the on-resistance of the element, which is the original purpose. Further, the thicker epitaxial growth causes a problem that productivity is lowered and cost is increased. Furthermore, when the thickness of the high-resistance epitaxial layer is increased and the region (transition width) in which the dopant concentration changes at the boundary between the epitaxial layer and the silicon substrate increases, there also arises a problem that the leakage current increases.

On the other hand, in a P-type silicon substrate, since there are various problems in using dopants other than boron, it is general to use boron as a dopant regardless of the doping amount.
Since boron can be doped at a high concentration relatively easily, the resistance has been further reduced from about 5 mΩcm as the temperature of the heat treatment in the device manufacturing process is lowered. In the range where there is no influence of auto-doping or out-diffusion, the resistance of the P-type silicon substrate has been lowered mainly in the low voltage power MOS and the like.

However, boron is an element having a large diffusion coefficient, and out-diffusion and auto-doping are problems.
On the other hand, a technique for controlling autodoping by sealing the back surface of a silicon substrate with an oxide film has been used for a long time (see, for example, Patent Document 1).

JP 58-95819 A

Thus, when boron or phosphorus is used as a dopant for a low-resistance epitaxial substrate, the dopant diffused from the substrate into the growth atmosphere during epitaxial growth is re-doped into the epitaxial layer, so-called auto-doping, or heat treatment during device manufacturing. The problem is that the out-diffusion of solid diffusion from the substrate to the epitaxial layer becomes large.
In order to stabilize the resistivity of the epitaxial layer, it is necessary to increase the thickness of the epitaxial layer, but there is a contradiction that this causes deterioration of the on-resistance of the element.

In epitaxial growth using these low-resistance substrates, technologies such as sealing the backside of the substrate with a non-doped oxide film, high-speed growth technology for single-wafer epitaxial devices, and gas flow control technology (holed susceptor) under the susceptor are used. Outdiffusion and autodoping during epitaxial growth are reduced.
However, since out-diffusion from the substrate surface side cannot be prevented, there remains a problem in controlling the region (transition region) in which the dopant concentration changes at the boundary between the substrate and the epitaxial layer during epitaxial growth and device fabrication. ing.

The present invention has been made in view of the above problems, and includes an epitaxial layer having a desired resistivity necessary for obtaining predetermined electrical characteristics of an element and a substrate having a lower resistance than conventional ones. Silicon epitaxial wafer that can improve the electrical characteristics of medium-voltage power MOSs, imaging devices, etc., and can suppress auto-doping and out-diffusion during epitaxial growth and heat treatment in the device manufacturing process more strongly than before. And its manufacturing method.

In order to solve the above problems, the present invention provides a silicon epitaxial wafer in which an epitaxial layer is formed on a silicon substrate, wherein the silicon substrate has a phosphorus or boron concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more. The silicon in which the carbon ion implantation layer is formed by being doped and having a CVD oxide film formed at least on the back surface side and carbon ions being implanted from the surface. A silicon epitaxial wafer characterized in that the epitaxial layer is formed on a surface of a substrate.

Thus, in a silicon epitaxial wafer in which a silicon wafer doped with phosphorus or boron at a high concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more is used as a substrate, a CVD oxide film is formed on at least the back surface side of the silicon substrate. Since it is formed, the out-diffusion of phosphorus or boron from the back surface of the silicon substrate, that is, the atmosphere of epitaxial growth is suppressed from being contaminated by the dopant during the formation of the epitaxial layer, and the occurrence of auto-doping is suppressed. Thus, the resistivity of the epitaxial layer is suppressed from deviating from a desired value.
In addition, since the carbon ion implanted layer is formed on the surface on which the epitaxial layer is formed, the carbon ion implanted layer of the silicon substrate takes in a high concentration of carbon into the silicon crystal lattice, thereby Increase and decrease of interstitial silicon occur. The decrease in interstitial silicon reduces the chances of phosphorus and boron being pushed out between the lattices, and the diffusion of atoms with a smaller bond radius than silicon, such as boron and phosphorus (kickout type), is significantly suppressed. As a result, the out diffusion from the silicon substrate to the epitaxial layer during the heat treatment during the formation of the epitaxial layer and the heat treatment during the device manufacture is suppressed.
By these effects, a silicon epitaxial wafer can be obtained which can obtain predetermined electrical characteristics such as a low breakdown voltage power MOS and an image pickup element, which are composed of an epitaxial layer having a desired resistivity and a silicon substrate having a lower resistivity than before.

Here, the carbon ion implanted layer is preferably one in which carbon ions are implanted at a dose of 3.0 × 10 ¹⁴ atoms / cm ² or more in order to reduce the interstitial silicon concentration.
Thus, when the dose amount of carbon ions is 3.0 × 10 ¹⁴ atoms / cm ² or more, the outward diffusion of phosphorus or boron on the silicon substrate surface side is more strongly suppressed. Thus, a silicon epitaxial wafer having a more desirable resistivity distribution can be obtained.

The CVD oxide film preferably covers the side surface of the silicon substrate from the position where the carbon ion implantation layer is formed to the surface side.
In this way, the silicon substrate doped with boron or phosphorus at a high concentration is formed by the CVD oxide film and the carbon ion implantation by being covered with the CVD oxide film from the position where the carbon ion implantation layer is formed to the surface side. Thus, a silicon epitaxial wafer having an epitaxial layer with a desired design value can be obtained. Further, boron or phosphorus out-diffusion or auto-doping is further suppressed.

When the impurity concentration of the epitaxial layer is 1/1000 or less of the impurity concentration of the silicon substrate, the effectiveness increases, and the effect of suppressing the impurity diffusion in the carbon implanted layer becomes remarkable, which is preferable.
As described above, the silicon epitaxial wafer of the present invention uses a silicon substrate doped with phosphorus or boron at a high concentration, and suppresses out-diffusion or autodoping of phosphorus or boron. Even if the resistivity of the substrate, that is, the impurity concentration differs from that of the substrate by 3 digits or more, a distribution close to a staircase type can be maintained.

Further, the silicon substrate is doped with phosphorus at a concentration of 0.5 × 10 ²⁰ atoms / cm ³ or more,
The carbon ion implantation layer is formed by implanting carbon ions at a dose amount of 4 A × 10 ¹⁵ atoms / cm ² or more when the concentration of phosphorus doped in the silicon substrate is A × 10 ²⁰ atoms / cm ^3. It has been
The epitaxial layer is preferably one in which phosphorus is doped at a concentration of 5.0 × 10 ¹⁷ atoms / cm ³ or less.

With such a phosphorus concentration and a dose amount of carbon ions, the movement of the phosphorus dopant at the boundary of the epitaxial layer can be controlled during the growth of the epitaxial layer and during the device fabrication process. Doping and out diffusion can be prevented. As a result, a silicon epitaxial wafer that can improve the electrical characteristics of the final device such as reduction of on-resistance and leakage current is obtained.

The silicon substrate is doped with boron at a concentration of 0.2 × 10 ²⁰ atoms / cm ³ or more,
The carbon ion implantation layer is formed by implanting carbon ions at a dose amount of 4B × 10 ¹⁵ atoms / cm ² or more when the concentration of boron doped in the silicon substrate is B × 10 ²⁰ atoms / cm ^3. It has been
In the epitaxial layer, boron is preferably doped with a concentration of 2.0 × 10 ¹⁷ atoms / cm ³ or less.

With such boron concentration and carbon ion dose, the movement of boron dopant at the boundary of the epitaxial layer can be controlled during the growth of the epitaxial layer and during the device fabrication process. Doping and out diffusion can be prevented. As a result, a silicon epitaxial wafer that can improve the electrical characteristics of the final device such as reduction of on-resistance and leakage current is obtained.

Furthermore, the thickness of the CVD oxide film is preferably 1500 mm or more.

With such a film thickness, out diffusion and autodoping of boron or phosphorus dopant can be further suppressed.

Further, the present invention provides a method for producing a silicon epitaxial wafer, comprising preparing a silicon substrate doped with phosphorus or boron at a concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more. After the process of forming the CVD oxide film on the back side and the process of forming the carbon ion implanted layer by implanting carbon ions on the front side are performed in random order, an epitaxial layer is formed on the surface subjected to the carbon ion implantation A method for producing a silicon epitaxial wafer is provided.

When a silicon epitaxial wafer is manufactured using a silicon substrate doped with phosphorus or boron at a high concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more, an auto process during epitaxial growth or heat treatment during device manufacturing is performed. It is important to suppress doping and out-diffusion.
Here, for auto-doping, it is effective to prevent outward diffusion from the substrate during the epitaxial process into the epitaxial growth atmosphere, so it is very effective to seal at least the back surface of the silicon substrate with a CVD oxide film. It is.
However, since the surface side cannot be sealed with a CVD oxide film for the convenience of epitaxial growth, this portion causes autodoping, and it is necessary to suppress this. Therefore, carbon is ion-implanted to form a carbon ion-implanted layer in order to form a thin layer having a small diffusion coefficient of phosphorus or boron immediately below the surface on which the epitaxial layer is formed. This makes it possible to suppress outward diffusion on the surface side, and suppresses not only auto-doping during epitaxial growth but also outdiffusion of dopant from the silicon substrate to the epitaxial layer side in the subsequent device manufacturing stage. It is possible to provide a method for manufacturing a silicon epitaxial wafer that can be used.

Here, the dose amount of the carbon ions is preferably set to 3.0 × 10 ¹⁴ atoms / cm ² or more.
As described above, by setting the dose amount of carbon ions to 3.0 × 10 ¹⁴ atoms / cm ² or more, phosphorus and boron can be more strongly suppressed from diffusing outward from the surface side of the silicon substrate. In addition, it is possible to manufacture a silicon epitaxial wafer having an epitaxial layer having a more desirable resistivity.

In addition, after performing the CVD oxide film forming step and the carbon ion implantation layer forming step, heating is performed at a temperature rising rate of 30 ° C./sec or more using an RTA apparatus, and recovery is performed at a temperature of 900 ° C. or more for 10 seconds or more. Annealing (hereinafter also referred to as recovery heat treatment) can be performed, and then the epitaxial layer can be formed.
Thus, by performing the recovery heat treatment with the RTA apparatus, the crystallinity of the silicon substrate disturbed by the carbon ion implantation can be recovered, the crystallinity of the epitaxial layer can be improved, and the crystal defects Therefore, it is possible to manufacture a silicon epitaxial wafer having a low resistivity and a desired resistivity.

Then, after performing the CVD oxide film forming step and the carbon ion implantation layer forming step, the wafer is introduced into a single-wafer epitaxial apparatus, and then heated from a temperature region of 600 ° C. or higher at a temperature rising temperature of 15 ° C./sec or higher. The epitaxial layer can be formed after holding for 30 seconds or more at a temperature of 1,050 ° C. or higher in a hydrogen atmosphere.
Thus, the single-wafer epitaxial apparatus can perform the crystallinity recovery heat treatment at a rate similar to RTA, and can recover the carbon ion implantation damage without separately performing the recovery heat treatment. Crystal defects can be reduced without increasing. Therefore, while suppressing the diffusion amount of phosphorus and boron, it is possible to recover the crystallinity without increasing the number of processes, and even higher quality silicon crystal (having few crystal defects and having a desired resistivity). Wafers can be manufactured.

Furthermore, it is preferable that the CVD oxide film is formed so as to cover a side surface closer to the silicon substrate surface than the position of the carbon ion implantation layer of the silicon substrate.
Thus, by forming the CVD oxide film so as to cover the side surface closer to the silicon substrate surface than the position of the carbon ion implantation layer of the silicon substrate, the silicon substrate is sealed with the CVD oxide film and the carbon ion implantation layer. Can do. As a result, out-diffusion and autodoping of boron and phosphorus can be suppressed more reliably and strongly, and a silicon epitaxial wafer having an epitaxial layer with a desired resistivity can be manufactured.

Further, as the silicon substrate, a silicon substrate doped with phosphorus at a concentration of 0.5 × 10 ²⁰ atoms / cm ³ or more is prepared,
In the step of forming the carbon ion implantation layer, when the concentration of phosphorus doped in the silicon substrate is set to A × 10 ²⁰ atoms / cm ³ , the dose is 4A × 10 ¹⁵ atoms / cm ² or more on the surface side. Injecting carbon ions to form the carbon ion implanted layer,
It is preferable to form the epitaxial layer doped with phosphorus at a concentration of 5.0 × 10 ¹⁷ atoms / cm ³ or less on the surface of the silicon substrate on which the carbon ions have been implanted.

If a silicon substrate is prepared with such a phosphorus concentration and a dose amount of carbon ions, a carbon ion implanted layer is formed, and an epitaxial layer is formed, the epitaxial layer is grown at the boundary of the epitaxial layer and during the device fabrication process. The movement of the phosphorus dopant can be controlled, and the silicon epitaxial wafer manufacturing method can prevent autodoping and outdiffusion from the silicon substrate surface side. This makes it possible to manufacture a silicon epitaxial wafer that can improve the final device electrical characteristics such as reduction of on-resistance and leakage current.

Furthermore, a silicon substrate doped with boron at a concentration of 0.2 × 10 ²⁰ atoms / cm ³ or more is prepared as the silicon substrate,
In the step of forming the carbon ion implantation layer, when the concentration of boron doped in the silicon substrate is B × 10 ²⁰ atoms / cm ³ , the dose is 4B × 10 ¹⁵ atoms / cm ² or more on the surface side. Injecting carbon ions to form the carbon ion implanted layer,
It is also preferable to form the epitaxial layer doped with boron at a concentration of 2.0 × 10 ¹⁷ atoms / cm ³ or less on the surface of the silicon substrate subjected to the carbon ion implantation.

If a silicon substrate is prepared with such a boron concentration and a dose amount of carbon ions, a carbon ion implantation layer is formed, and an epitaxial layer is formed, the epitaxial layer is grown at the boundary of the epitaxial layer and during the device manufacturing process. It becomes a method for manufacturing a silicon epitaxial wafer that can control the movement of boron dopant and prevent autodoping and outdiffusion from the surface side of the silicon substrate. This makes it possible to manufacture a silicon epitaxial wafer that can improve the final device electrical characteristics such as reduction of on-resistance and leakage current.

In the step of forming the carbon ion implantation layer, the carbon ion implantation energy is preferably 100 keV or less.

With such an implantation energy, a carbon ion implantation layer having a high carbon concentration can be formed in the vicinity of the silicon substrate surface, so that the silicon epitaxial wafer manufacturing method can further prevent autodoping and outdiffusion.

Further, in the step of forming the CVD oxide film, it is preferable to form a non-doped CVD oxide film having a thickness of 1500 mm or more.

A CVD oxide film having such a thickness is a method for producing a silicon epitaxial wafer that can further prevent auto-doping and out-diffusion.

In addition, after the implantation of the carbon ions and before the formation of the epitaxial layer, the temperature is increased from 600 ° C. to 1000 ° C. at a temperature increase rate of 20 ° C./sec or more, and 30 at a temperature of 1,050 ° C. or more in a hydrogen atmosphere. It is preferable to carry out the recovery annealing step by holding for at least 2 seconds.

By performing such a recovery annealing step, the crystallinity of the silicon substrate disturbed by the implantation of carbon ions can be recovered, and an epitaxial layer having a good crystallinity can be formed by vapor-phase growth of the epitaxial layer thereon. This is a method for producing a silicon epitaxial wafer that can be obtained. Thereby, a silicon epitaxial wafer with few crystal defects can be produced in the epitaxial layer.

Furthermore, in the present invention, a method of manufacturing a semiconductor element or an integrated circuit using a silicon epitaxial wafer manufactured by the method of manufacturing a silicon epitaxial wafer,
The method for manufacturing a semiconductor element or an integrated circuit is characterized in that the heat treatment held for longer than 1 minute is such that the maximum temperature of the heat treatment is 950 ° C. or lower.

When manufacturing a semiconductor element or an integrated circuit, the heat treatment is performed in this way, so that the movement of the dopant at the boundary of the epitaxial layer can be controlled, and autodoping and out diffusion from the silicon substrate surface side can be prevented. This is a method for manufacturing a semiconductor device or an integrated circuit.

As described above, according to the present invention, an epitaxial layer having a desired resistivity necessary for obtaining predetermined electrical characteristics of an element and a silicon substrate having a lower resistivity than the conventional one, a low breakdown voltage power MOS and an imaging device are provided. Silicon epitaxial wafer capable of improving the electrical characteristics of devices, etc., and capable of suppressing autodoping during epitaxial growth and dopant out-diffusion during heat treatment in the device manufacturing process, and its manufacture A method is provided.

In addition, as described above, by using boron and phosphorus having a predetermined concentration as dopants and implanting carbon ions having a predetermined dose, at the epitaxial layer boundary during the growth of the epitaxial layer and during the device fabrication process. It is possible to provide a silicon epitaxial wafer which can control the movement of the phosphorus dopant and can effectively prevent autodoping and outdiffusion from the surface side of the silicon substrate, and a method for manufacturing the same. Thereby, it is possible to obtain a silicon epitaxial wafer capable of improving the final device electrical characteristics such as reduction of on-resistance and leakage current. Furthermore, the present invention can provide a method for manufacturing a semiconductor element or an integrated circuit using the silicon epitaxial wafer.

It is the figure which showed an example of the outline of the silicon epitaxial wafer of this invention. It is the process flow figure showing an example of the manufacturing method of the silicon epitaxial wafer of the present invention. It is the figure which showed the density | concentration distribution of the depth direction of the phosphorus from the wafer surface of the epitaxial wafer of an Example and Comparative Examples 1 and 2. FIG. It is explanatory drawing which showed the outline | summary of the motion of the dopant impurity in the middle of epitaxially growing an epitaxial layer on the surface of a silicon substrate. It is the figure which showed the relationship between the diffusion coefficient of various elements, and temperature. It is a general | schematic process flowchart of power MOS manufacture by the manufacturing method of the semiconductor element or integrated circuit of this invention. It is a figure which shows the carbon ion implantation energy and the carbon concentration distribution (dose amount: 1 × 10 ¹⁵ atoms / cm ² ) in the depth direction. It is a figure which shows the change of the boron density | concentration distribution (SIMS) of the epitaxial layer-silicon substrate interface vicinity before and behind the heat processing of this invention and the conventional epitaxial wafer. It is a figure which shows the change of the density | concentration distribution (SIMS) of the phosphorus of the vicinity of an epitaxial layer-silicon substrate interface before and after heat processing of this invention and the conventional epitaxial wafer. It is a figure which shows the change of carbon concentration distribution (SIMS) near the epitaxial layer-silicon substrate interface of the epitaxial wafer of this invention before heat processing and after heat processing at 1100 degreeC for 1 hour.

Hereinafter, the present invention will be described more specifically.
FIG. 4 shows an outline of the movement of the dopant impurity during the epitaxial growth of the epitaxial layer on the surface of the silicon substrate.

As shown in FIG. 4A, when the epitaxial layer is formed, pre-baking is performed as shown in FIG. 4B in order to remove the natural oxide film 11 on the surface of the silicon substrate 10 before the epitaxial growth. However, at this time, the dopant in the wafer diffuses outward in the atmospheric gas and stays in the vicinity of the susceptor 20.

Then, as shown in FIG. 4C, when the epitaxial layer 12 starts to be formed, the growth rate of the epitaxial layer 12 is faster than the diffusion rate of the dopant, so that the outward diffusion from the substrate disappears. However, in the initial growth stage of the epitaxial layer 12, the dopant that has diffused out and stays in the atmospheric gas is taken into the epitaxial layer 12.

Here, as shown in FIG. 4D, when no countermeasure against auto-doping is applied to the silicon substrate 10, an epitaxial layer does not grow on the back surface side of the silicon substrate 10, so that the dopant is removed from the back surface side. The diffusion will continue. For this reason, the dopant which stays in the epitaxial layer which continues to grow is continuously taken in, and the resistivity of the epitaxial layer 12 remains deviated from a desired value.

Here, as shown in FIG. 4 (e), the atmospheric gas is allowed to flow also to the back side of the susceptor, or the back side of the silicon substrate is sealed with a non-doped oxide film 13 as shown in FIG. 4 (f). However, this is not a measure for outward diffusion from the surface of the silicon substrate 10 to the epitaxial layer 12, and the resistivity shift of the epitaxial layer 12 cannot be completely suppressed.

Therefore, in order to reduce outward diffusion on the silicon substrate surface side, natural oxide film removal annealing is performed at a low temperature, and a thin epitaxial layer is immediately grown to suppress outward diffusion. In some cases, the surface side auto-doping may be suppressed by a cap deposition method in which the substrate is once purged and then epitaxially grown.
However, although the process becomes complicated, there is a problem that it is not so effective in suppressing autodoping. This is because the purging is not so effective because the dopant diffuses out into the starch layer of the atmospheric gas during the pre-bake for removing the natural oxide film on the surface of the silicon substrate and is adsorbed on the susceptor. .

Here, the out diffusion of the dopant from the silicon substrate to the epitaxial layer is determined by the diffusion coefficient of the dopant species and the epitaxial growth conditions (mainly the ambient temperature and the time required for the epitaxial growth).
As shown in FIG. 5, since phosphorus and boron are elements having a relatively large diffusion coefficient, this out-diffusion becomes large, but a single-wafer type epitaxial device has been widely used, and high-speed temperature rising and cooling and high-speed growth are achieved. As a result, the out diffusion toward the epitaxial layer side during epitaxial growth has been reduced.

However, for auto-doping, a single wafer epitaxial apparatus is not always effective.
In addition, since the growth rate is high in the single wafer epitaxial apparatus, the epitaxial growth is started in a state where the purge is not sufficiently performed. This is one of the reasons why the above-described auto-doping countermeasure is not effective.

Therefore, it is necessary to suppress the diffusion itself on the silicon substrate surface side.
That is, it is possible to suppress out-diffusion by forming a film of a material having a small dopant diffusion coefficient. However, as described above, the back side may be sealed with a non-doped CVD oxide film, but this method cannot be applied to the front side.
In addition, the phenomenon of out diffusion becomes stronger for elements having a large diffusion coefficient in silicon. That is, the most effective countermeasure for this is to reduce the diffusion coefficient.

Therefore, as a result of intensive studies on a method for reducing the diffusion coefficient of dopant in silicon, the number of silicon atoms between lattices decreases in silicon containing carbon at a high concentration, and boron and phosphorus are interstitial. Opportunities are reduced, and diffusion of atoms with a smaller bond radius than silicon such as boron and phosphorus (kickout phenomenon) is significantly suppressed, and atoms with a larger bond radius than silicon such as arsenic and antimony (hole type) We focused on the phenomenon that diffusion is accelerated. That is, in the crystal region doped with carbon at a high concentration, attention was focused on suppressing auto-doping and out-diffusion during epitaxial growth and device fabrication by utilizing the phenomenon that the diffusion of phosphorus and boron is slowed down.

Note that the behavior related to the change in the diffusion coefficient of dopant impurities in silicon containing a high concentration of carbon has been put to practical use in boron profile control in SiGeC type heterobipolar transistors, and many reports have been made on the principle. (Non-patent document 1, Non-patent document 2).

In order to improve the actual device characteristics, it is necessary to suppress the diffusion of dopants (auto-doping and out-diffusion) not only in the epitaxial growth process but also in the subsequent heat treatment during the device manufacturing process. It is. In recent years, the power MOS has been miniaturized, and as a result, the heat treatment in the element manufacturing process has also been lowered in temperature. On the other hand, the dopant for the silicon substrate is also easily diffused instead of arsenic instead of red phosphorus. Further, since the silicon substrate is required to have a low resistivity, the dopant concentration of the silicon substrate is increasing, and diffusion to the epitaxial layer is likely to occur. It is necessary to realize effective diffusion suppression of the dopant comprehensively including not only the epitaxial growth process but also the heat treatment of the element manufacturing process after the epitaxial growth process.

In the process of epitaxial growth after carbon ion implantation into a silicon substrate, how the carbon concentration distribution on the surface of the silicon substrate changes can be roughly known from basic data on ion implantation. That is, by obtaining a profile in the depth direction at the ion implantation end stage with the dose amount and the acceleration energy, and using the Gaussian distribution formula, the change in the carbon concentration distribution after the heat treatment of the silicon substrate can be roughly obtained.

On the other hand, the diffusion of the dopant from the silicon substrate to the epitaxial layer is roughly determined by an error function. The diffusion of the dopant is from a certain concentration, and the change in the carbon concentration distribution is the diffusion of a certain amount of material. The steep peak of the carbon concentration distribution formed by carbon ion implantation has the property of being lowered by heat treatment.

Here, when the carbon ion implantation energy is increased, the peak position of the carbon concentration distribution is deepened, and the carbon concentration on the wafer surface is lowered. Since carbon is a relatively light element, when it is implanted with high acceleration energy, the concentration on the wafer surface tends to be low. For example, the carbon concentration at the surface when ion implantation of a dose amount of 10 × 10 ¹⁵ atoms / cm ² is performed at 100 keV is about 1 × 10 ¹⁸ atoms / cm ³ , and when this is 50 keV, the carbon concentration is 6 × 10 6. It is known to be about ¹⁸ atoms / cm ³ (Non-patent Document 3).

As described above, if a high-concentration carbon ion implantation layer is present in the vicinity of the silicon substrate surface, dopant diffusion into the epitaxial layer can be better suppressed, so that the carbon ion implantation dose is large and the carbon ion implantation energy is high. Is preferably low.

Actually, since the carbon concentration on the surface is increased and the dopant concentration on the surface is decreased by the heat treatment before epitaxial growth, the carbon ion implanted layer has a concentration of phosphorus doped in the silicon substrate of A × 10 ²⁰ atoms / cm ^3. 4A × 10 ¹⁵ atoms / cm ² or more, and when the concentration of boron doped in the silicon substrate is B × 10 ²⁰ atoms / cm ³ , ions with a dose amount of 4B × 10 ¹⁵ atoms / cm ² or more are used. By implantation, the carbon concentration becomes equal to or higher than the dopant concentration before epitaxial growth, and diffusion into the epitaxial layer can be suppressed.

When the phosphorus concentration of the silicon substrate is relatively high and the dose amount of carbon implantation is less than 4 A × 10 ¹⁵ atoms / cm ² , a moderation effect on phosphorus diffusion is observed in the epitaxial growth stage, but the effect is remarkable in the subsequent heat treatment. Is not. Under the heat treatment after epitaxial growth, in the vicinity of the epitaxial layer-silicon substrate interface, carbon diffuses in a Gaussian distribution, and phosphorus and boron diffuse in an error function, so that the relative concentrations change in a complicated manner. In this region, in order to stably suppress dopant diffusion by carbon ion implantation, the dose is preferably set to a predetermined amount or more.

As described above, in a silicon substrate containing a high concentration of carbon, the concentration of interstitial silicon decreases, and as a result, the opportunity for boron and phosphorus to be pushed out between the lattices decreases, resulting in a smaller bond radius than silicon. Atomic (interstitial) diffusion slows down, and (vacancy) diffusion of atoms with larger bond radii than silicon increases. In particular, at high temperatures, both the interstitial silicon and the concentration of vacancies increase due to the generation of Frankel pairs, so that the diffusion suppressing effect due to the reduction of interstitial silicon due to carbon in the silicon substrate decreases. Therefore, when it is intended to suppress diffusion of phosphorus dopant, boron dopant, etc. in the carbon ion implanted layer, heat treatment is performed at a low temperature so that √Dt becomes equal not only in the epitaxial growth process but also in the element fabrication process. Is preferred. In boron profile control in a SiGeC type heterobipolar transistor, device heat treatment is performed at a low temperature and put into practical use. Here, Dt indicates a diffusion coefficient at temperature t, and √Dt is an index indicating a measure of the amount of diffusion by heat treatment.

FIG. 10 shows changes in the carbon concentration profile before and after carbon ions are implanted into the silicon substrate and subjected to heat treatment. It can be seen that the carbon concentration profile after the heat treatment shown in FIG. 10 is not a simple Gaussian diffusion profile. Thus, it is considered that carbon ions are diffused by both vacancy-type diffusion and interstitial diffusion. Therefore, by implanting carbon ions at a high concentration into the silicon substrate, it is possible to suppress the phenomenon of dopant (phosphorus, boron) floating from the silicon substrate to the epitaxial layer in the epitaxial growth process and the element manufacturing process. As a result, the on-resistance of the vertical transistor can be reduced and the leakage current can be reduced.

On the other hand, it is known that when a carbon ion is ion-implanted at a dose of about 1 × 10 ¹⁵ atoms / cm ² , the region becomes a strong gettering site. Therefore, the carbon ion-implanted epitaxial layer-silicon substrate region also serves as a stable and powerful gettering site, and contributes to the improvement of device yield and electrical characteristics using this method. Naturally, an effect is also expected.

Then, as a result of intensive studies based on this knowledge, the present inventors conducted carbon ion implantation on a silicon substrate directly under the epitaxial layer to form a carbon ion implanted layer, thereby forming a silicon substrate surface side (epitaxial It is found that an epitaxial layer having a desired resistivity can be obtained by suppressing outdiffusion on the side on which the layer is formed), further suppressing autodoping by forming a CVD oxide film on the back side together, The present invention has been completed.

Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto. FIG. 1 is a view showing an example of the outline of the silicon epitaxial wafer of the present invention.
As shown in FIG. 1A, a silicon epitaxial wafer 1 according to the present invention is obtained by forming an epitaxial layer 5 on a silicon substrate 2.
At least the silicon substrate 2 is doped with phosphorus or boron at a concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more, and the CVD oxide film 4 is formed on at least the back surface 2b side, and on the front surface 2a side. Is a carbon ion implanted layer 3 formed by carbon ions implanted from the surface. The epitaxial layer 5 is formed on the surface 2a on the side where the carbon ion implantation layer 3 is formed.

Thus, in a silicon epitaxial wafer comprising a silicon substrate doped with phosphorus or boron at a concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more and an epitaxial layer, a CVD oxide film is formed on at least the back surface side of the silicon substrate. In the case where the carbon ion implanted layer is formed on the surface side on which the epitaxial layer is formed, out-diffusion on the back surface side is suppressed by the CVD oxide film on the back surface during the heat treatment when the epitaxial layer is formed, On the surface side, diffusion of boron and phosphorus is suppressed by the carbon ion implantation layer, and outward diffusion is suppressed. As a result, autodoping of the dopant into the epitaxial layer is suppressed. In addition, even during device manufacture, out diffusion to the epitaxial layer is suppressed by the presence of the carbon ion implantation layer. Note that phosphorus or boron doped in the silicon substrate is preferably doped at a concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more and a solid solution limit or less.
Therefore, it is suitable for obtaining predetermined electrical characteristics such as a low withstand voltage power MOS, a medium withstand voltage power MOS, an image sensor, etc. It is a silicon epitaxial wafer composed of an efficient silicon substrate.

Further, as shown in FIG. 1B, the silicon epitaxial wafer 1 ′ has a CVD oxide film 4 ′ extending from the position where the carbon ion implantation layer 3 of the silicon substrate 2 is formed to the side surface closer to the silicon substrate surface. It can be covered.
In such an epitaxial wafer, the silicon substrate is completely sealed by the CVD oxide film and the carbon ion implantation layer. For this reason, boron or phosphorus doped at a high concentration in the silicon substrate suppresses the out-diffusion during the heat treatment and the auto-doping during the formation of the epitaxial layer more strongly than in the past. Accordingly, a silicon epitaxial wafer having an epitaxial layer with a desired resistivity is obtained.

Here, the carbon ion implanted layer 3 can be one in which carbon ions are implanted at a dose of 3.0 × 10 ¹⁴ atoms / cm ² or more.
In the case of a silicon epitaxial wafer having a carbon ion implantation layer with a carbon ion dose of 3.0 × 10 ¹⁴ atoms / cm ² or more, it is promised that the peak concentration of carbon in the ion implantation region is equal to or higher than the dopant concentration of the substrate. As a result, the outward diffusion of phosphorus or boron on the silicon substrate surface side can be more strongly suppressed. Therefore, a silicon epitaxial wafer having an epitaxial layer with a more desirable resistivity is obtained. Note that carbon ions are preferably implanted at a dose of 3.0 × 10 ¹⁴ atoms / cm ² or more and 3.0 × 10 ¹⁵ atoms / cm ² or less.

In this case, as in the case of the SiGeC heterobipolar transistor, the same effect can be obtained by forming a thin epitaxial layer doped with carbon at a high concentration on the epitaxial layer side in order to suppress diffusion into the epitaxial layer. However, unlike in SiGe, the solid solubility of carbon in silicon is not so high, and crystal defects are generated when it is forcibly doped, so it is not practically used.
In addition, a carbon-induced donor is generated in a high concentration (10 ¹⁹ atoms / cm ³ or more) doping region. Since a donor having a carbon concentration of 1/100 to 1/1000 is generated, there is a problem that an n-type layer is formed. When carbon ions are implanted into a substrate doped with boron of 10 ¹⁹ atoms / cm ³ or more, an n-type inversion layer is not formed by a carbon donor, and the change in resistivity is 10% or less.

The impurity concentration of the epitaxial layer 5 can be set to 1/1000 or less of the impurity concentration of the silicon substrate 2.
Even if a high-concentration silicon substrate is used, if the impurity concentration of the epitaxial layer is relatively high, the influence of auto-doping is relatively small. In the current epitaxial apparatus, when the concentration ratio between the epitaxial layer and the substrate is 1/1000 or less, it is greatly affected by auto-doping. When this method is applied to an epitaxial wafer whose impurity concentration in the epitaxial layer is 1/1000 or less of the impurity concentration in the substrate, the effect becomes extremely remarkable. The impurity concentration of the epitaxial layer is preferably as low as possible to 1/1000 or less of the impurity concentration of the silicon substrate.

In particular, the silicon substrate is one in which phosphorus is doped at a concentration of 0.5 × 10 ²⁰ atoms / cm ³ or more, and the carbon ion implantation layer has a concentration of phosphorus doped in the silicon substrate of A × 10 ²⁰ atoms. / Cm ³ , carbon ions are implanted at a dose of 4 A × 10 ¹⁵ atoms / cm ² or more, and the epitaxial layer has a phosphorus content of 5.0 × 10 ¹⁷ atoms / cm ³ or less. A silicon epitaxial wafer that is doped at a concentration of 1 to 5 is preferred. In addition, the silicon substrate is doped with boron at a concentration of 0.2 × 10 ²⁰ atoms / cm ³ or more, and the carbon ion implanted layer has a boron concentration of B × 10 ²⁰ atoms doped into the silicon substrate. / Cm ³ , carbon ions are implanted at a dose amount of 4B × 10 ¹⁵ atoms / cm ² or more, and the epitaxial layer has boron of 2.0 × 10 ¹⁷ atoms / cm ³ or less. Also preferred is a silicon epitaxial wafer doped at a concentration of

In this case, phosphorus or boron doped in the silicon substrate is doped at a concentration of 0.5 × 10 ²⁰ atoms / cm ³ or more and a solid solution limit or less and 0.2 × 10 ²⁰ atoms / cm ³ or more and a solution solution limit or less. It is preferred that Carbon ions are implanted at a dose of 4 A × 10 ¹⁵ atoms / cm ² or more and 6 A × 10 ¹⁵ atoms / cm ² or less, 4B × 10 ¹⁵ atoms / cm ² or more and 10 B × 10 ¹⁵ atoms / cm ² or less. It is preferable. Increasing the dose of carbon ion implantation has a greater effect of slowing down the diffusion of phosphorus and boron. On the other hand, in order to avoid a decrease in ion implantation productivity and generation of crystal defects in the epitaxial layer, 4A × 10 Dose amounts close to ¹⁵ atoms / cm ² and 4B × 10 ¹⁵ atoms / cm ² are preferred. Furthermore, phosphorus or boron doped in the epitaxial layer is 0.5 × 10 ¹⁷ atoms / cm ² or more and 5.0 × 10 ¹⁷ atoms / cm ³ or less, 0.2 × 10 ¹⁷ atoms / cm ² or more, respectively. It is preferable to dope at a concentration of 0 × 10 ¹⁷ atoms / cm ³ or less.

With such a phosphorus or boron concentration and a carbon ion dose, the movement of phosphorus or boron dopant at the boundary of the epitaxial layer can be controlled during the growth of the epitaxial layer and during the device fabrication process, and the silicon substrate Auto-doping and out-diffusion from the surface side can be prevented. As a result, a silicon epitaxial wafer that can improve the electrical characteristics of the final device such as reduction of on-resistance and leakage current is obtained.

Furthermore, the thickness of the CVD oxide film is preferably 1500 mm or more. With such a film thickness, out diffusion and autodoping of boron or phosphorus dopant can be further suppressed. As a result, a silicon epitaxial wafer that can improve the electrical characteristics of the final device such as reduction of on-resistance and leakage current is obtained.

Next, an example of a method for producing a silicon epitaxial wafer according to the present invention will be described below with reference to the drawings. However, the present invention is not limited to these examples. FIG. 2 is a process flow diagram showing an example of a method for producing a silicon epitaxial wafer of the present invention.

As shown in FIG. 2A, a silicon substrate doped with phosphorus or boron at a concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more is first prepared.
The silicon substrate prepared here is not particularly limited except that phosphorus or boron is doped with phosphorus or boron at a concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more. For example, the silicon substrate is grown by the CZ method. What was manufactured by slicing from a silicon single crystal rod may be used. Further, the crystal orientation, crystal diameter, other conditions, and the like may be set as desired according to the standard, and are not particularly limited. Note that phosphorus or boron doped in the silicon substrate is preferably doped at a concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more and a solid solution limit or less.

Next, as shown in FIGS. 2B and 2C, a step of forming a CVD oxide film on the back surface side is performed on the prepared silicon substrate, and then carbon ions are implanted on the front surface side to form a carbon ion implanted layer. The process of forming is performed.
Alternatively, as shown in FIGS. 2B 'and 2C', a step of forming a carbon ion implanted layer by implanting carbon ions using pad oxide on the surface side of the prepared silicon substrate is performed, and then the back surface is formed. A step of forming a CVD oxide film on the side is performed.

At this time, it is desirable that pad oxide having a thickness of about 200 to 300 mm is formed. This is effective in preventing channeling and not making the range (Rp) during ion implantation too deep. The same effect can be obtained by performing tilting at the time of carbon ion implantation or by setting the acceleration energy low.

The carbon ion implantation process and the CVD oxide film forming process are not in any particular order, and either process may be performed first, and is not particularly limited.
However, when the CVD oxide film forming process is performed after the carbon ion implantation process, the oxide film that has come to the surface side after the CVD oxide film forming process, that is, before the epitaxial layer forming process, must be removed by polishing. Production efficiency is not very good. On the other hand, when the carbon ion implantation process is performed after the CVD oxide film formation process, it is not affected by auto-doping from the back surface during the carbon ion implantation process, so it is necessary to polish the back surface side after the carbon ion implantation process. Absent. Therefore, FIGS. 2B and 2C in which the CVD oxide film forming step is performed first and then the carbon ion implantation step is more convenient in terms of manufacturing efficiency.

Further, the CVD oxide film formation step (b) or (c ′) may be a thermal decomposition method or a plasma growth method, and the formation method is not particularly limited. The oxide film is preferably non-doped with no dopant.

In the carbon ion implantation step (b ′) or (c), the dose of carbon ions can be set to 3.0 × 10 ¹⁴ atoms / cm ² or more.
By setting the dose amount of carbon ions as described above, diffusion of phosphorus and boron from the surface side of the silicon substrate can be more reliably suppressed, and the epitaxial layer has a resistivity with a desired value. A silicon epitaxial wafer can be obtained. Note that carbon ions are preferably implanted at a dose of 3.0 × 10 ¹⁴ atoms / cm ² or more and 3.0 × 10 ¹⁵ atoms / cm ² or less.

Note that the acceleration energy of carbon ions is preferably 20 keV or more. As a result, the depth of the carbon ion implantation layer does not become too shallow, and it can contribute to reliably stopping the diffusion of boron and phosphorus.

Further, in the step of forming the carbon ion implantation layer, the carbon ion implantation energy is preferably 100 keV or less. With such implantation energy, a carbon ion implantation layer having a high carbon concentration can be formed in the vicinity of the surface of the silicon substrate, so that the silicon epitaxial wafer manufacturing method can further prevent autodoping and outdiffusion. This makes it possible to manufacture a silicon epitaxial wafer that can improve the final device electrical characteristics such as reduction of on-resistance and leakage current.

Here, FIG. 7 shows the relationship between the implantation energy and carbon concentration distribution formed when carbon ions are implanted into the silicon substrate surface. Thus, the carbon ion implantation layer can be formed near the silicon substrate surface as the implantation energy is lower.

Further, the amount of carbon ions implanted can be adjusted according to the dopant concentration of the silicon substrate. For example, when the dopant concentration of the silicon substrate is about 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ^3. It is preferably about 1 × 10 ¹⁵ atoms / cm ² . For such ion implantation, a large current ion implanter can be used, and standard productivity can be secured. Further, as an inexpensive and less side-effect method for forming this high-concentration carbon ion-implanted layer, ion implantation is performed in a range where the boron dopant or phosphorus dopant concentration of the silicon substrate does not exceed 1.0 × 10 ²⁰ atoms / cm ^3. It is preferable to do.

The silicon substrate implanted with carbon ions as described above can be removed by etching only the surface side with a hydrofluoric acid solution if there is a pad oxide film. If there is no pad oxide film, RCA cleaning can be performed as it is, and the subsequent process can be performed. In the RCA cleaning in this case, it is preferable to properly manage the etching amount in the SC1 cleaning.

Further, the CVD oxide film is formed so as to cover the side surface closer to the silicon substrate surface than the position of the carbon ion implantation layer of the silicon substrate, that is, so as to completely overlap the carbon ion implantation region. And a CVD oxide film can be continuously formed.
By continuously forming the carbon ion implantation region and the CVD oxide film so as to completely overlap the carbon ion implantation region of the silicon substrate, the silicon substrate can be sealed with the CVD oxide film and the carbon ion implantation layer. . As a result, the occurrence of out-diffusion or auto-doping of boron or phosphorus can be more strongly suppressed, and therefore a silicon epitaxial wafer having an epitaxial layer with a desired resistivity can be obtained.

Furthermore, in the step of forming the CVD oxide film, it is preferable to form a non-doped CVD oxide film having a thickness of 1500 mm or more. With a CVD oxide film having such a thickness, a silicon epitaxial wafer manufacturing method that can further prevent auto-doping and out-diffusion is obtained. This makes it possible to manufacture a silicon epitaxial wafer that can improve the final device electrical characteristics such as reduction of on-resistance and leakage current. The thickness of the CVD oxide film is preferably 1500 mm or more and 5000 mm or less.

Further, as shown in FIG. 2 (d), using an RTA apparatus, heating is performed at a temperature rising rate of 30 ° C./sec or more, recovery annealing is performed at a temperature of 900 ° C. or more for 10 seconds or more, and then the step (e) The epitaxial layer can be formed.
Thus, the crystallinity of the silicon substrate disturbed in the previous carbon ion implantation process is obtained by heating at a temperature rising rate of 30 ° C./sec or more and performing recovery annealing for 10 seconds or more at a temperature of 900 ° C. or more by the RTA apparatus. Can be recovered, and an epitaxial layer with good crystallinity can be obtained by vapor phase growth thereon. That is, a silicon epitaxial wafer with few crystal defects can be obtained in the epitaxial layer. The rate of temperature increase during the recovery annealing is preferably 30 ° C./sec or more and below the limit of the device performance, for example, 60 ° C./sec or less. The recovery annealing is performed at a temperature of 900 ° C. or more and 1100 ° C. or less. It is preferable that the reaction is performed for a time of 10 seconds to 60 seconds.

Then, as shown in FIG. 2 (d), after performing the CVD oxide film forming step and the carbon ion implantation layer forming step, it is introduced into a single wafer type epitaxial apparatus and from a temperature region of 600 ° C. or higher, 15 ° C./sec or higher. The temperature is raised at a temperature rise rate of 1 and maintained at a temperature of 1,050 ° C. or higher for 30 seconds or more in a hydrogen atmosphere.
Thus, the crystallinity recovery heat treatment can also be performed by a single wafer epitaxial apparatus. In this case, since the recovery heat treatment is not performed separately using another apparatus, a silicon epitaxial wafer with good crystallinity can be obtained without increasing the heat treatment that is a diffusion factor of phosphorus and boron and without increasing the number of steps. It is done. Therefore, according to such a method, an inexpensive silicon epitaxial wafer having good crystallinity and suppressed dopant diffusion can be manufactured. The recovery heat treatment is performed at a temperature rising rate of 15 ° C./sec to 30 ° C./sec from a temperature range of 600 ° C. to 750 ° C., and is performed at 1,050 ° C. to 1150 ° C. in a hydrogen atmosphere. It is preferable to maintain the temperature at 30 seconds or more and 60 seconds or less.

Note that this recovery of crystallinity can stably prevent the occurrence of crystal defects by using the RTA apparatus as described above, but is not limited to this, and a diffusion furnace can also be used.

Such a recovery annealing step is particularly useful when epitaxial growth is not performed by a radiant heating type apparatus, and it is easy to stably avoid the occurrence of stacking faults in the subsequent epitaxial growth.

Further, when a radiation heating type epitaxial apparatus is used, rapid heating close to that of the RTA apparatus becomes possible, so that the recovery annealing step after carbon ion implantation can be performed in parallel with the pre-bake before epitaxial growth. In this case, it is preferable to perform heating in the temperature range from 700 ° C. to 1000 ° C. at a rate of 15 ° C./sec or higher, preferably 20 ° C./sec or higher. Thereafter, pre-baking is performed for 30 seconds or more at a temperature of 1,050 ° C. or more to remove the natural oxide film and perform a recovery heat treatment, and then epitaxial growth can be started.

Thereafter, as shown in FIG. 2 (e), an epitaxial layer is formed on the surface where carbon ion implantation has been performed. Thus, the epitaxial wafer is completed (FIG. 2 (f)).

The source gas for epitaxial growth may be monosilane, dichlorosilane, or trichlorosilane, but it is preferable to perform the growth under high-speed growth conditions to shorten the holding time at high temperatures. In particular, when carbon ion implantation of about 10 ¹⁵ atoms / cm ² is performed, it is important to perform the epitaxial growth process under conditions such that crystal defects generated by the ion implantation do not propagate to the epitaxial layer.

In this way, by forming a CVD oxide film on at least the back surface side of the silicon substrate (FIG. 2B or FIG. 2C), phosphorus or boron enters the epitaxial growth atmosphere from the back surface side of the silicon substrate during the epitaxial process. Diffusion can be prevented and generation of autodope can be strongly suppressed.
Further, by forming a carbon ion implantation layer by ion implantation of carbon (FIG. 2 (b ′) or (c)), the diffusion coefficient of phosphorus or boron on the surface of the silicon substrate can be reduced. It becomes possible to suppress outward diffusion of the dopant on the surface side, and to suppress autodoping during epitaxial growth and out-diffusion in the element manufacturing process.
Due to these effects, even when a silicon epitaxial wafer is manufactured using a silicon substrate doped with phosphorus or boron at a high concentration of 2.0 × 10 ¹⁹ atoms / cm ³ or more, during epitaxial growth or when a device is manufactured. Auto-dope and out-diffusion during heat treatment of silicon can be suppressed more strongly than before, and a silicon epitaxial wafer consisting of a high resistivity epitaxial layer and a silicon substrate with a low resistivity and a narrow resistivity transition width can be manufactured. Can do.

When a silicon substrate doped with phosphorus at a high concentration is used, the diffusion coefficient of phosphorus is large. For this reason, phosphorus diffuses from the silicon substrate side to the epitaxial layer side during the heat treatment during device fabrication, the thickness of the epitaxial layer is substantially reduced, and sagging occurs in the dopant profile at the interface between the silicon substrate and the epitaxial layer. There is.
However, in the present invention, by introducing a carbon ion implanted layer, the floating of the dopant can be suppressed. Accordingly, since the transition width of the dopant profile of the epitaxial layer can be kept small even at the end of the device process, the thickness of the epitaxial layer can be made thinner with respect to a predetermined breakdown voltage. .

In particular, a silicon substrate doped with phosphorus at a concentration of 0.5 × 10 ²⁰ atoms / cm ³ or more is prepared as a silicon substrate, and the concentration of phosphorus doped into the silicon substrate in the step of forming the carbon ion implantation layer Is A × 10 ²⁰ atoms / cm ³ , carbon ions are implanted into the surface side with a dose amount of 4 A × 10 ¹⁵ atoms / cm ² or more to form a carbon ion implanted layer, and silicon subjected to carbon ion implantation A method for producing a silicon epitaxial wafer is preferred in which an epitaxial layer doped with phosphorus at a concentration of 5.0 × 10 ¹⁷ atoms / cm ³ or less is formed on the surface of the substrate. In addition, a silicon substrate doped with boron at a concentration of 0.2 × 10 ²⁰ atoms / cm ³ or more is prepared as a silicon substrate, and the concentration of boron doped in the silicon substrate in the step of forming the carbon ion implantation layer Is B × 10 ²⁰ atoms / cm ³ , carbon ions are implanted into the surface side with a dose amount of 4B × 10 ¹⁵ atoms / cm ² or more to form a carbon ion implanted layer, and silicon subjected to carbon ion implantation A silicon epitaxial wafer manufacturing method in which an epitaxial layer doped with boron at a concentration of 2.0 × 10 ¹⁷ atoms / cm ³ or less is formed on the surface of the substrate is also preferable.

If a silicon substrate is prepared with such a phosphorus or boron concentration and a carbon ion dose, a carbon ion implantation layer is formed, and an epitaxial layer is formed, the epitaxial layer is grown during the growth of the epitaxial layer and during the device fabrication process. Therefore, it is possible to control the movement of phosphorus or boron dopant at the boundary of the silicon substrate, and to produce a silicon epitaxial wafer that can prevent autodoping and outdiffusion from the silicon substrate surface side. This makes it possible to manufacture a silicon epitaxial wafer that can improve the final device electrical characteristics such as reduction of on-resistance and leakage current.

As described above, by using boron and phosphorus at a predetermined concentration as a dopant and implanting a predetermined dose of carbon ions, the dopant at the boundary of the epitaxial layer is grown during the growth of the epitaxial layer and during the device fabrication process. It is possible to provide a silicon epitaxial wafer that can control the movement and can effectively prevent autodoping and outdiffusion from the surface side of the silicon substrate, and a method for manufacturing the same.

Furthermore, in the present invention, a semiconductor device or an integrated circuit is manufactured using a silicon epitaxial wafer manufactured by a method for manufacturing a silicon epitaxial wafer, and the heat treatment held for longer than 1 minute is performed at a maximum temperature of the heat treatment. Provided is a method for manufacturing a semiconductor element or an integrated circuit, wherein the temperature is 950 ° C. or lower. FIG. 6 shows a schematic flow of a manufacturing process related to epitaxial growth from a silicon substrate according to the present invention and further to a device manufacturing process.

For example, when a vertical MOS transistor is formed on the silicon epitaxial wafer of the present invention, it is preferable that the formation temperature of the double diffusion structure of field oxidation, source, and channel region is 950 ° C. or lower. In the case of a SiGeC heterobipolar transistor, since a boron-doped base layer is formed after field oxidation, the subsequent steps of forming an emitter and the like are performed at 900 ° C. or lower. Although the low-voltage power MOS is also miniaturized and the temperature of the process is decreasing, it is preferable to set the field oxidation formation temperature to 950 ° C. or lower. Phosphorus and boron are used in the formation of the channel and source regions, but since there is no influence of carbon in this region, the process can proceed under the same conditions as when carbon ion implantation is not performed. In addition, it is preferable to change the process conditions to a low temperature and a long time as much as possible for a process that has been processed at a temperature higher than 950 ° C. in manufacturing an imaging device. As such process conditions, it is preferable to set the maximum temperature of the heat treatment to 950 ° C. or less with respect to the heat treatment held for longer than 1 minute as described above.

When manufacturing a semiconductor element or an integrated circuit, the heat treatment is performed in this way, so that the movement of the dopant at the boundary of the epitaxial layer can be controlled, and autodoping and out diffusion from the silicon substrate surface side can be prevented. This is a method for manufacturing a semiconductor device or an integrated circuit. As a result, it is possible to manufacture a semiconductor element or an integrated circuit with excellent final device electrical characteristics such as on-resistance and reduction of leakage current.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.

Example 1
An epitaxial silicon substrate was fabricated from a CZ single crystal having a diameter of 200 mm, a red phosphorus dope, and a resistivity of 1.2 mΩcm.
Then, a CVD oxide film having a thickness of 300 nm was formed on the back side.

Thereafter, carbon ions were implanted into the silicon substrate using a large current ion implantation apparatus. Specifically, channeling countermeasures were taken by 5 ° tilting without forming a pad oxide film on the surface of the silicon substrate where ions were implanted. The acceleration voltage was 60 keV, and the dose was 1.0 × 10 ¹⁵ atoms / cm ² .
Then, after ion implantation, recovery heat treatment was performed using an RTA apparatus. The heat treatment conditions were a temperature increase rate of 30 ° C./sec, a nitrogen atmosphere of 1200 ° C., and 30 seconds.

Thereafter, substrate cleaning was performed and epitaxial growth was performed. In this epitaxial growth, a single wafer reactor was used, and an epitaxial layer having a thickness of 5 μm was formed at 1150 ° C. using trichlorosilane as a silicon source.
As a result of investigating the thickness of the formed epitaxial layer by the infrared interference method, it was in the range of 5.0 to 5.2 μm. The resistivity of the epitaxial layer was measured by the CV method using a Schottky diode and found to be 10.0 Ωcm at the wafer center.

The manufactured epitaxial wafer was evaluated as shown below.
Defects in the epitaxial layer of the produced epitaxial wafer were evaluated by preferential etching.
Further, with respect to the wafer subjected to the pre-etching, the chip was cut out from the position of 10 to 20 mm in the outer periphery, which was relatively strongly influenced by autodoping, and each was subjected to angle polishing, and the dopant profile was measured by spraying resistance. Here, the spreading resistance is corrected data and converted from the resistance value to the impurity concentration. The results are shown in FIG. Note that the thickness of the epitaxial layer is reduced by about 1.0 μm by the amount etched by the preferential etching.

(Comparative Examples 1 and 2)
For comparison, one silicon substrate having the same manufacturing method (same lot) as the silicon substrate used in Example 1 was prepared, one of which was formed with a CVD oxide film on the back side, and carbon ion implantation was performed. An epitaxial wafer was manufactured without performing the above process (Comparative Example 1), and the other one was subjected to carbon ion implantation without forming a CVD oxide film on the back side to produce an epitaxial wafer (Comparative Example 2).
The CVD oxide film formation conditions, carbon ion implantation conditions, and epitaxial layer formation conditions were the same as in the examples.

The thickness of the epitaxial layer at the wafer center of the epitaxial wafer of Comparative Example 1 was in the range of 5.1 to 5.3 μm. The resistivity was in the range of 9.9 Ωcm to 9.2 Ωcm.
The thickness of the epitaxial layer at the wafer center of the epitaxial wafer of Comparative Example 2 was in the range of 5.1 to 5.3 μm. The resistivity was 9.9 Ωcm.
The same evaluations as in the examples were performed on the silicon epitaxial wafers of Comparative Examples 1 and 2. The result is shown in FIG.

As a result of investigating the defects in the epitaxial layer by the preferential etching, the density of stacking faults in the epitaxial wafers of Examples and Comparative Examples 1 and 2 was within an average level.

As shown in FIG. 3, the phosphorus concentration of the epitaxial layer is the result of decreasing in the order of Example, Comparative Example 1, and Comparative Example 2. From the measurement result of the spraying resistance, there is a significant difference in autodoping. It was.
Regarding the out diffusion from the substrate to the epitaxial layer at the time of epitaxial growth, the interface between the silicon substrate and the epitaxial layer is not clear, and thus the difference cannot be clearly confirmed. However, there are few in the order of Comparative Example 2, Comparative Example 1, and Example.
In FIG. 3, since the accuracy of angle polishing is not necessarily good, the interface between the epitaxial layer and the substrate is shown so that the profiles match.

From the above results, it was found that out-diffusion and auto-doping can be significantly suppressed by using a high-concentration phosphorus-doped silicon substrate whose back surface is sealed with a non-doped CVD oxide film and performing carbon ion implantation on the front surface side.
In addition, when ion implantation is performed on a low resistivity silicon substrate, diffusion of dopant from the substrate side to the epitaxial layer side during the element manufacturing process can be suppressed, and more than necessary to ensure the breakdown voltage of the element. It has also been found that it is not necessary to increase the thickness of the epitaxial layer.

(Example 2)
A silicon substrate was fabricated from a CZ single crystal having a diameter of 200 mm, boron doping, and a resistivity of 3.2 mΩcm (boron doping concentration: 0.25 × 10 ²⁰ atoms / cm ³ ). A CVD oxide film having a thickness of 500 nm was formed on the back side during the silicon substrate manufacturing process.

Thereafter, carbon ions were implanted into the substrate using a large current ion implantation apparatus. A pad oxide film was not formed, and channeling countermeasures were taken by tilting at 5 ° C. The acceleration voltage was 60 keV, and the dose was 1.0 × 10 ¹⁵ atoms / cm ² . Recovery heat treatment using an RTA apparatus or a diffusion furnace was not performed after ion implantation. Thereafter, after substrate cleaning, epitaxial growth was performed. Epitaxial growth is performed using a single-wafer reactor of a radiation heating method, using trichlorosilane as a silicon source, heating up to 1000 ° C. at a heating rate of 20 ° C./sec, prebaking at 1150 ° C., and the same temperature. Then, an epitaxial layer doped with boron at 1.5 × 10 ¹⁵ atoms / cm ³ was formed to manufacture a silicon epitaxial wafer. As a result of investigating the thickness of this epitaxial layer by an infrared interference method, it was in the range of 5.5 to 5.8 μm. As a result of measuring the resistivity of the epitaxial layer by the CV method using a Schottky diode, it was 10.0 Ωcm at the wafer center.

(Comparative Example 3)
For comparison, a silicon epitaxial wafer was manufactured in the same manner as in Example 2 except that the carbon ions were not implanted. At this time, the thickness of the epitaxial layer at the center of the wafer was in the range of 5.2 to 5.6 μm. The resistivity was 9.9 Ωcm at the center.

The defects in the epitaxial layer of the silicon epitaxial wafer manufactured according to Example 2 and Comparative Example 3 were investigated by preferential etching. As a result, in Example 2, it was confirmed that damage caused by carbon ion implantation did not induce stacking faults in the epitaxial layer. In Example 2 and Comparative Example 3, the defect density of the epitaxial layer was within an average level.

The silicon epitaxial wafers of Example 2 and Comparative Example 3 were not heat-treated, and were vertically processed under a heat treatment condition in a nitrogen gas atmosphere containing 3% oxygen at 950 ° C., 20 hours and 1100 ° C. for 1 hour. What was heat-processed using the diffusion furnace was prepared. About these, each chip is cut out from a position of 10 to 20 mm in the outer periphery which is relatively strongly influenced by autodoping, and boron of about 8 μm from the surface of the epitaxial layer to the silicon substrate direction by quadrupole SIMS (Secondary Ion Mass Spectroscopy). The depth profile of was measured. The result is shown in FIG. FIG. 8 shows that in Comparative Example 3, diffusion of phosphorus dopant is not suppressed. On the other hand, in the case where heat treatment is not performed, it can be seen that the diffusion of boron dopant into the epitaxial layer is suppressed, and from this, the diffusion suppression of boron dopant in the epitaxial growth process is presumed. It can also be seen that boron dopant is suppressed from being diffused even when heat treatment is performed at 950 ° C. for 20 hours as the pseudo element manufacturing step. However, when heat treatment was performed at 1100 ° C. for 1 hour, the boron dopant diffusion was only slightly slowed down.

From the above results, a silicon substrate doped with boron at a high concentration with the back surface sealed with a non-doped oxide film is used, carbon ion implantation is performed on the surface side, and a heat treatment after epitaxial growth is performed at a temperature near 950 ° C. for a long time. As a result, it was found that diffusion of boron from the silicon substrate into the epitaxial layer (outward diffusion) can be suppressed.

(Example 3)
A silicon substrate was fabricated from a CZ single crystal having a diameter of 200 mm, a red phosphorus doping, and a resistivity of 1.2 mΩcm (phosphorus doping concentration: 0.6 × 10 ²⁰ atoms / cm ³ ). A CVD oxide film having a thickness of 300 nm was formed on the back side during the silicon substrate manufacturing process.

Thereafter, carbon ions were implanted into the substrate using a large current ion implantation apparatus. A pad oxide film was formed. Ion implantation was performed with an acceleration voltage of 60 keV and a dose of 2.0 × 10 ¹⁵ atoms / cm ² . Recovery heat treatment using an RTA apparatus or a diffusion furnace was not performed after ion implantation. Thereafter, after substrate cleaning, epitaxial growth was performed. Epitaxial growth is performed using a single-wafer reactor of a radiation heating method, using trichlorosilane as a silicon source, heating up to 1000 ° C. at a heating rate of 20 ° C./sec, prebaking at 1150 ° C., and the same temperature. A silicon epitaxial wafer was manufactured by forming an epitaxial layer doped with phosphorus at 0.5 × 10 ¹⁶ atoms / cm ³ . As a result of investigating the thickness of this epitaxial layer by infrared interferometry, the thickness of the center was in the range of 5.2 to 5.4 μm. The resistivity of the epitaxial layer was measured by the CV method using a Schottky diode and found to be 1.0 Ωcm near the center of the wafer.

(Comparative Example 4)
For comparison, a silicon epitaxial wafer was manufactured in the same manner as in Example 3 except that the carbon ions were not implanted. At this time, the thickness of the epitaxial layer at the center of the wafer was in the range of 5.2 to 5.5 μm. The resistivity was 0.99 Ωcm at the center.

Defects in the epitaxial layer of the silicon epitaxial wafer manufactured according to Example 3 and Comparative Example 4 were investigated by preferential etching. As a result, in Example 3, it was confirmed that damage caused by carbon ion implantation did not induce stacking faults in the epitaxial layer. In Example 3 and Comparative Example 4, the defect density of the epitaxial layer was within an average level.

The silicon epitaxial wafers of Example 3 and Comparative Example 4 were not heat-treated, and were vertically processed under a heat treatment condition in a nitrogen gas atmosphere containing 3% oxygen at 950 ° C., 20 hours and 1100 ° C. for 1 hour. What was heat-processed using the diffusion furnace was prepared. About these, each chip was cut out from the position of the outer periphery of 10 to 20 mm which is relatively strongly influenced by autodoping, and the depth profile of about 8 μm boron from the epitaxial layer surface toward the silicon substrate was measured by quadrupole SIMS. . The result is shown in FIG. From FIG. 9, it was shown that the diffusion of phosphorus dopant was not suppressed in Comparative Example 4. On the other hand, when heat treatment is not performed, it can be seen that the diffusion of the phosphorus dopant into the epitaxial layer is suppressed, and it is assumed from this that the diffusion of the phosphorus dopant in the epitaxial growth process is suppressed. It can also be seen that the diffusion of the phosphorus dopant is suppressed even when heat treatment is performed at 950 ° C. for 20 hours as the pseudo element manufacturing step. However, when heat treatment was performed at 1100 ° C. for 1 hour, the phosphorus dopant diffusion was only slightly slowed down.

From FIG. 9, the fact that no slow diffusion of phosphorus was observed away from the above-mentioned silicon substrate interface corresponds to a portion having a low carbon concentration. That is, when the carbon ion implantation conditions are the same, the phosphorus dopant concentration of the silicon epitaxial wafer of Example 3 is higher than that of the boron silicon substrate (Example 2). At a distant site, the carbon concentration is low, and the diffusion suppressing effect of the phosphorus dopant is weakened.

As described above, in order to suppress the out-diffusion of the dopant from the silicon substrate to the epitaxial layer by carbon ion implantation, the ion implantation conditions (dose amount) such that the carbon concentration on the surface of the silicon substrate becomes a predetermined concentration or higher at the start of epitaxial growth. , Acceleration energy) is preferably set appropriately.

The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

Claims

A silicon epitaxial wafer in which an epitaxial layer is formed on a silicon substrate,
The silicon substrate is doped with phosphorus or boron at a concentration of 2.0 × 10 19 atoms / cm 3 or more, and a CVD oxide film is formed at least on the back side, and carbon ions are implanted from the surface. A carbon ion implanted layer is formed,
A silicon epitaxial wafer, wherein the epitaxial layer is formed on a surface of the silicon substrate on which the carbon ion implantation layer is formed.
2. The silicon epitaxial wafer according to claim 1, wherein the carbon ion implanted layer is formed by implanting carbon ions at a dose amount of 3.0 × 10 14 atoms / cm 2 or more.
3. The silicon epitaxial wafer according to claim 1, wherein the CVD oxide film covers a side surface of the silicon substrate from a position where the carbon ion implantation layer is formed to a surface side. 4.
4. The silicon epitaxial wafer according to claim 1, wherein an impurity concentration of the epitaxial layer is 1/1000 or less of an impurity concentration of the silicon substrate. 5.
The silicon substrate is doped with phosphorus at a concentration of 0.5 × 10 20 atoms / cm 3 or more,
The carbon ion implantation layer is formed by implanting carbon ions at a dose amount of 4 A × 10 15 atoms / cm 2 or more when the concentration of phosphorus doped in the silicon substrate is A × 10 20 atoms / cm 3. It has been
5. The silicon epitaxial wafer according to claim 1, wherein the epitaxial layer is doped with phosphorus at a concentration of 5.0 × 10 17 atoms / cm 3 or less. .
The silicon substrate is doped with boron at a concentration of 0.2 × 10 20 atoms / cm 3 or more,
The carbon ion implantation layer is formed by implanting carbon ions at a dose amount of 4B × 10 15 atoms / cm 2 or more when the concentration of boron doped in the silicon substrate is B × 10 20 atoms / cm 3. It has been
5. The silicon epitaxial wafer according to claim 1, wherein the epitaxial layer is doped with boron at a concentration of 2.0 × 10 17 atoms / cm 3 or less. .
The silicon epitaxial wafer according to any one of claims 1 to 6, wherein a film thickness of the CVD oxide film is 1500 mm or more.
A method for producing a silicon epitaxial wafer, comprising:
Preparing a silicon substrate doped with phosphorus or boron at a concentration of 2.0 × 10 19 atoms / cm 3 or more;
After the step of forming a CVD oxide film on the back side and the step of forming a carbon ion implantation layer by implanting carbon ions on the front side are performed in random order on the prepared silicon substrate,
A method for producing a silicon epitaxial wafer, wherein an epitaxial layer is formed on a surface subjected to carbon ion implantation.
9. The method for producing a silicon epitaxial wafer according to claim 8, wherein a dose amount of the carbon ions is set to 3.0 × 10 14 atoms / cm 2 or more.
After performing the CVD oxide film forming step and the carbon ion implantation layer forming step, using an RTA apparatus, heating is performed at a temperature rising rate of 30 ° C./sec or higher, and recovery annealing is performed at a temperature of 900 ° C. or higher for 10 seconds or longer. The method for producing a silicon epitaxial wafer according to claim 8 or 9, wherein the epitaxial layer is formed after the step.
After performing the CVD oxide film forming step and the carbon ion implantation layer forming step, after being introduced into a single wafer epitaxial apparatus, the temperature is raised from a temperature region of 600 ° C. or more at a temperature rising rate of 15 ° C./sec or more, 10. The method for producing a silicon epitaxial wafer according to claim 8, wherein the epitaxial layer is formed after being held at a temperature of 1,050 ° C. or higher for 30 seconds or more in a hydrogen atmosphere.
12. The CVD oxide film according to claim 8, wherein the CVD oxide film is formed so as to cover a side surface of the silicon substrate closer to the surface of the silicon substrate than the position of the carbon ion implantation layer. A method for producing a silicon epitaxial wafer as described in 1).
Preparing a silicon substrate doped with phosphorus at a concentration of 0.5 × 10 20 atoms / cm 3 or more as the silicon substrate;
In the step of forming the carbon ion implantation layer, when the concentration of phosphorus doped in the silicon substrate is set to A × 10 20 atoms / cm 3 , the dose is 4A × 10 15 atoms / cm 2 or more on the surface side. Injecting carbon ions to form the carbon ion implanted layer,
13. The epitaxial layer doped with phosphorus at a concentration of 5.0 × 10 17 atoms / cm 3 or less is formed on the surface of the silicon substrate subjected to the carbon ion implantation. The method for producing a silicon epitaxial wafer according to any one of the above.
Preparing a silicon substrate doped with boron at a concentration of 0.2 × 10 20 atoms / cm 3 or more as the silicon substrate;
In the step of forming the carbon ion implantation layer, when the concentration of boron doped in the silicon substrate is B × 10 20 atoms / cm 3 , the dose is 4B × 10 15 atoms / cm 2 or more on the surface side. Injecting carbon ions to form the carbon ion implanted layer,
13. The epitaxial layer doped with boron at a concentration of 2.0 × 10 17 atoms / cm 3 or less is formed on the surface of the silicon substrate subjected to the carbon ion implantation. The method for producing a silicon epitaxial wafer according to any one of the above.
15. The method for producing a silicon epitaxial wafer according to claim 8, wherein in the step of forming the carbon ion implantation layer, carbon ion implantation energy is set to 100 keV or less.
16. The method for producing a silicon epitaxial wafer according to claim 8, wherein in the step of forming the CVD oxide film, a non-doped CVD oxide film having a thickness of 1500 mm or more is formed. .
After the carbon ion implantation and before the formation of the epitaxial layer, the temperature is increased from 600 ° C. to 1000 ° C. at a temperature increase rate of 20 ° C./sec or more, and at a temperature of 1,050 ° C. or more in a hydrogen atmosphere for 30 seconds or more. The method for producing a silicon epitaxial wafer according to any one of claims 8 to 16, wherein a recovery annealing step is performed while being held.
A method of manufacturing a semiconductor element or an integrated circuit using a silicon epitaxial wafer manufactured by the method of manufacturing a silicon epitaxial wafer according to any one of claims 8 to 17,
The method for manufacturing a semiconductor element or an integrated circuit, wherein the heat treatment for longer than 1 minute is performed such that the maximum temperature of the heat treatment is 950 ° C. or lower.