JP2010153631A - Epitaxial silicon wafer, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress both misfit dislocation and a stacking fault (SF) of an epitaxial silicon wafer based on a silicon crystal substrate with low electric resistivity doped with an electric-resistivity decreasing dopant, such as phosphorus, and germanium together during growth of silicon crystal. <P>SOLUTION: The process temperature of a process of growing a silicon epitaxial layer by a CVD method on the silicon crystal substrate doped with, for example, phosphorus and germanium together during the growth of silicon crystal is set within a range of 1,000 to 1,090°C (preferably, 1,050 to 1,080°C). Consequently, the number of LPDs (due to SF) caused on a surface of the epitaxial silicon wafer owing to an SF greatly decreases. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an epitaxial silicon wafer for use in a semiconductor circuit and a method for manufacturing the same, and more particularly, a silicon crystal substrate doped with germanium together with a dopant for lowering an electrical resistivity, such as phosphorus, when growing a silicon crystal. The present invention relates to an epitaxial silicon wafer having a silicon epitaxial layer formed on its surface and a method for manufacturing the same.

  For example, an epitaxial silicon wafer for a power MOS transistor is required to have a very low electrical resistivity of the silicon crystal substrate. In order to sufficiently reduce the electrical resistivity of the silicon crystal substrate, arsenic (As) is used as a dopant for decreasing the resistivity in molten silicon in the process of pulling up the silicon crystal ingot that is the material of the wafer (that is, when growing the silicon crystal). A technique for doping is known. However, since arsenic tends to evaporate, it is difficult to sufficiently increase the arsenic concentration in the silicon crystal, and it is difficult to manufacture an arsenic-doped silicon crystal substrate having a resistivity as low as required.

  Therefore, instead of arsenic, by doping an N-type or P-type resistivity lowering dopant having a lower volatility property, for example, phosphorus (P), which is one of N-type dopants that are difficult to volatilize, A technique for manufacturing a silicon crystal substrate having a very high phosphorus concentration and a very low electrical resistivity is known.

  However, when a silicon epitaxial layer is formed on a silicon crystal substrate doped with phosphorus at a high concentration, dislocation defects (misfit dislocations) are caused by a difference in phosphorus concentration at the interface between the silicon crystal substrate and the silicon epitaxial layer. There is a problem that occurs. Misfit dislocations propagate from the interface portion of the silicon crystal substrate to the surface of the silicon epitaxial layer, and are visually observed as densely packed thin and thin lines, causing a reduction in the electrical performance of the semiconductor element. The cause of the misfit dislocation is that the atomic radius of silicon is 1.17 Å (angstrom), whereas the atomic radius of phosphorus is 1.10 か な り, which is considerably smaller than that of silicon. The difference is that it causes unwanted strain in the crystal (by the way, the atomic radius of arsenic is 1.18 Å, which is quite close to silicon, so there are very few misfit dislocations). In view of this cause, the same problem occurs not only when phosphorus is used as a dopant for lowering electrical resistance, but also when other dopant substances are used.

In order to solve this problem, germanium (Ge) having an atomic radius of 1.22 mm larger than that of silicon is doped simultaneously with phosphorus in the ingot pulling process, thereby relaxing the strain of the silicon crystal lattice caused by phosphorus with germanium. And the technique which suppresses generation | occurrence | production of a misfit dislocation is known (refer patent document 1).
JP-A-9-7961

  However, when a silicon epitaxial layer is grown by CVD on a silicon crystal substrate doped with high concentrations of phosphorus and germanium at the time of silicon crystal growth, the misfit dislocation is prevented, but another side effect is new. To occur. The side effect is that a stacking fault (stacking fault, hereinafter referred to as SF) occurs in the silicon epitaxial layer, and that SF appears as a step on the wafer surface, and the LPD (Light Point Defect) level on the wafer surface It gets worse. For example, in an epitaxial wafer having a diameter of 200 mm, the total number of LPDs due to SF is as large as about 100 to several thousand, and such a wafer cannot be put to practical use. The cause of this SF has not been clarified so far, but is an inherent problem in the case of a dopant for lowering electrical resistivity, such as phosphorus, and a high concentration of germanium.

  Accordingly, an object of the present invention is to provide a misfit in an epitaxial silicon wafer based on a silicon crystal substrate doped with germanium (Ge) and a predetermined dopant for lowering electrical resistivity, such as phosphorus (P), when growing silicon crystals. It is to suppress both dislocations and stacking faults (SF).

  According to a first aspect of the present invention, in an epitaxial silicon wafer manufacturing method, a silicon crystal substrate in which an N-type or P-type resistivity reducing dopant and germanium are doped together during silicon crystal growth is prepared. One step, a second step of annealing out oxygen from the surface layer of the silicon crystal substrate, and a pre-bake treatment of the silicon crystal substrate for the purpose of surface modification, and a CVD method after the second step. And a third step of forming a silicon epitaxial layer on the silicon crystal substrate at a temperature in the range of 1000 ° C. to 1090 ° C. As a dopant for decreasing the electrical resistivity, a material that can be doped at a concentration high enough to sufficiently reduce the electrical resistivity of the silicon crystal substrate, such as phosphorus (P) or P, which is one of N-type dopants. Boron (B), which is one of the type dopants, can be employed.

  According to this manufacturing method, in the first step, a silicon crystal substrate having a low electrical resistivity in which a dopant for lowering electrical resistivity and germanium as described above are doped together at a high concentration during silicon crystal growth is prepared. Such co-doping of the resistivity lowering dopant and germanium suppresses the occurrence of misfit dislocations when a silicon epitaxial layer is formed on the silicon crystal substrate.

Further, by forming the silicon epitaxial layer on the silicon crystal substrate at 1000 to 1090 ° C. in the third step, the occurrence of stacking fault (SF) is effectively suppressed, and the light on the surface of the epitaxial layer (that is, the wafer surface) is reduced. -The number of point defaults (LPD) is very small. Typically, the number of LPDs per 100 cm ² of surface area of the wafer is 10 or less (that is, the total number of LPDs of 200 mm diameter wafers is 30 or less), and the wafer can be put to practical use. Can be manufactured.

Such an advantage of the present invention is that the germanium concentration of the silicon crystal substrate is high enough to cause the SF problem, for example, in the range of 7.0 × 10 ^{19 to} 1.0 × 10 ²⁰ atoms / cm ³ . In particular, the practical value will be high.

In one preferred embodiment, the concentration of the dopant for lowering electrical resistivity of the silicon crystal substrate prepared in the first step is in the range of 4.7 × 10 ^{19 to} 9.47 × 10 ¹⁹ atoms / cm ^3. . Moreover, the electrical resistivity of the silicon crystal substrate is in the range of 0.8 × 10 ^{−3 to} 1.5 × 10 ⁻³ Ω / cm. The temperature when forming the silicon epitaxial layer on the silicon crystal substrate in the third step is in the range of 1050 to 1080 ° C. As a result, the number of LPDs per 100 cm ² of the surface area of the wafer can be extremely reduced to about 0 to 3 (that is, the total number of LPDs of a wafer having a diameter of 200 mm is 10 or less).

  In one preferred embodiment, in the second step, a pre-bake treatment is performed in a hydrogen gas or inert gas atmosphere at a temperature in the range of 1150 to 1200 ° C. for a period of 35 seconds or more.

According to another aspect of the present invention, a silicon crystal substrate doped with N-type or P-type resistivity reducing dopant and germanium at the time of silicon crystal growth, and silicon formed on the surface of the silicon crystal substrate There is provided an epitaxial silicon wafer characterized in that the number of light point defects on the surface of the silicon epitaxial layer due to stacking faults is 10 or less per 100 cm ^{2 of} surface area.

According to a preferred embodiment, the germanium concentration of the silicon crystal substrate is in the range of 7.0 × 10 ^{19 to} 1.0 × 10 ²⁰ atoms / cm ³ . The concentration of the dopant for lowering the electrical resistivity, such as phosphorus, in the silicon crystal substrate is in the range of 4.7 × 10 ^{19 to} 9.47 × 10 ¹⁹ atoms / cm ³ . And the electrical resistivity of the silicon crystal substrate is in the range of 0.8 × 10 ^{−3 to} 1.5 × 10 ⁻³ Ω / cm.

  Such an epitaxial silicon wafer according to the present invention cannot be manufactured by the manufacturing method according to the prior art, but can be manufactured for the first time by the manufacturing method according to the present invention. That is, conventionally, a product of a silicon crystal substrate having a very low electrical resistivity as described above has not been developed commercially. Recently, the demand for such products has arisen, so that the electrical resistivity is sufficiently low, on a silicon crystal substrate that is highly doped with a dopant for reducing electrical resistivity and germanium together when growing the silicon crystal. The need to develop an epitaxial silicon wafer having a silicon epitaxial layer has arisen, and for the first time, the need to eliminate stacking faults, a problem inherent to heavily doped germanium, has arisen. Conventionally, no technology for solving the problem of stacking faults in such an epitaxial silicon wafer has been developed. Therefore, the above-described epitaxial silicon wafer according to the present invention is a novel one that has not been heretofore used, and in order to manufacture this, the above-described manufacturing method of the present invention must be used.

  According to the present invention, in an epitaxial silicon wafer based on a silicon crystal substrate doped with germanium (Ge) together with a dopant for lowering electrical resistivity such as phosphorus and growing silicon crystal, misfit dislocations and stacking faults ( An epitaxial silicon wafer in which both of (SF) are suppressed is provided.

  Hereinafter, the manufacturing method of the epitaxial silicon wafer according to the present invention will be described in detail.

  In the prior art, as described above, phosphorus (P) and germanium (Ge) are doped together at the time of silicon crystal growth (particularly, a very low electrical resistivity required for a power MOS transistor can be realized) When a silicon epitaxial layer is grown on a silicon crystal substrate (which is doped with phosphorus and germanium at a high concentration), a large number of SFs (stacking faults) are generated in the silicon epitaxial layer. The cause of this phenomenon is presumed to be related to germanium and a dopant for lowering electrical resistivity, such as phosphorus, which is highly doped in the silicon crystal substrate, but it is not clear yet.

  Accordingly, the present inventors have developed a silicon crystal substrate in which a dopant for lowering electrical resistivity, such as phosphorus, and germanium are doped together at a high concentration when growing a silicon crystal as described above (for example, when generating a silicon ingot). As a result of stacking experiments while variously changing the conditions of the epitaxial growth process when growing the silicon epitaxial layer using GaN, it is possible to suppress the occurrence of SF while suppressing misfit dislocations. It has been found that conditions for the epitaxial growth process exist.

  Hereinafter, the case where phosphorus is employed as the material for the electric resistivity lowering dopant will be described as an example. However, the present invention can be similarly applied not only to phosphorus but also to other dopant materials capable of high-concentration doping, such as boron, when adopting a dopant for lowering electrical resistivity.

  The optimum epitaxial growth process conditions found from the above experiments are that a predetermined electric resistivity lowering dopant such as phosphorus and germanium are doped together during the growth of the silicon crystal (in particular, as described above). When a silicon epitaxial layer is grown by CVD on a silicon crystal substrate that is highly doped, the process temperature during epitaxial growth is 1000 ° C. to 1090 ° C., and preferably the optimum process temperature during epitaxial growth is 1050 ° C. That is, 1080 ° C. Incidentally, in the prior art, the process temperature is about 1100 ° C. By adopting a process temperature in the above range, which is slightly lower than the conventional process temperature, the amount of SF generated is greatly reduced. Note that the process temperature range of 1000 ° C. or lower is not practical. This is because at such a process temperature, the growth rate of the silicon epitaxial layer becomes slow and the quality deteriorates.

The concentration of phosphorus in the silicon crystal substrate serving as the base of the epitaxial layer is in the range of 4.7 × 10 ^{19 to} 9.47 × 10 ¹⁹ atoms / cm ³ , and the concentration of germanium is 7.0 × 10 ¹⁹ to 1. It is preferably in the range of 0 × 10 ²⁰ atoms / cm ³ . In the pulling process of the silicon ingot that is the material of the silicon crystal substrate, by adjusting the respective concentrations when simultaneously doping phosphorus and germanium into the original molten silicon from which the ingot is pulled, the high concentration within the above range A silicon crystal substrate containing phosphorus and germanium can be obtained. The electrical resistivity of the silicon crystal substrate doped with high-concentration phosphorus and germanium in the above range is in the range of 0.8 × 10 ^{−3 to} 1.5 × 10 ⁻³ Ω / cm, This electrical resistivity satisfies the resistivity requirement required for a wafer for a power MOS transistor. FIG. 1 shows the result of an experiment examining the relationship between the process temperature during epitaxial growth and the number of LPDs that appear on the wafer surface due to SF. The horizontal axis indicates the process temperature (EP growth actual temperature) during epitaxial growth, and the vertical axis indicates the number of LPDs per wafer.

  Here, the number of LPDs per wafer shown on the vertical axis indicates the number of results obtained by detecting and counting LPDs having a side dimension of 0.13 μm or more. Incidentally, since the size of one side of the LPD caused by SF is often in the range of about 10 to 15 μm, the number of LPDs shown in FIG. It can be said that all numbers are included.

In this experiment, a silicon crystal substrate having a diameter of 200 mm (single surface area of 314 cm ² ) doped with phosphorus and germanium in the concentration range described above at the time of silicon crystal growth was used. A silicon epitaxial layer was formed on 25 silicon crystal substrates for each process temperature. The number of LPDs at each process temperature shown in FIG. 1 is an average value of the number of LPDs of those 25 wafers.

As can be seen from FIG. 1, the process temperature range can be broadly divided into a range of 1100 ° C. or higher, a range of 1100 to 1090 ° C., and a range of 1090 ° C. or lower (however, 1000 ° C. or higher). In the range of 1100 ° C. or higher, the number of LPDs is as large as 10,000 or more. As the process temperature is lowered, the number of LPDs rapidly decreases in the range of 1100 to 1090 ° C. In the range of 1090 ° C. or less (however, 1000 ° C. or more), even if the number of LPDs is large, it is 30 or less (10 or less per 100 cm ² of the surface area of the wafer). Therefore, the process temperature during epitaxial growth is preferably in the range of 1000 ° C. to 1090 ° C. In particular, in the range of 1050 ° C. to 1080 ° C., the number of LPDs is very small (several ^{2 to} 0 per 100 cm ² of the surface area of the wafer), and the above-mentioned problems are low when the process temperature is 1000 ° C. or less. So it can be said to be the optimum process temperature range.

  The reason why the number of LPDs is very small in the above temperature range has not been clarified so far.

  FIG. 2 shows a flow of manufacturing an epitaxial silicon wafer according to an embodiment of the present invention.

  As shown in FIG. 2, first, a silicon crystal substrate is prepared in which phosphorus and germanium are doped together at a high concentration when growing a silicon crystal (step S1). One of the typical methods is to use a Czochralski method to pull a silicon ingot that is highly doped with phosphorus and germanium together from molten silicon that is highly doped with phosphorus and germanium. Then, a silicon crystal substrate is cut out from the silicon ingot.

Here, desirably, as described above, the concentration of phosphorus in the silicon crystal substrate is in the range of 4.7 × 10 ^{19 to} 9.47 × 10 ¹⁹ atoms / cm ³ , and the concentration of germanium is 7.0 ×. It is in the range of 10 ^{19 to} 1.0 × 10 ²⁰ atoms / cm ³ , and the electric resistivity is in the range of 0.8 × 10 ^{−3 to} 1.5 × 10 ⁻³ Ω / cm.

  Generation of misfit dislocations when the silicon epitaxial layer is grown is suppressed by the action of germanium doped with phosphorus.

  Next, in order to anneal out oxygen from the surface layer of the silicon crystal substrate, the silicon crystal substrate is pre-baked (step S2). Here, desirably, the pre-bake treatment is performed in an atmosphere of hydrogen gas at 1150 to 1200 ° C. or an inert gas such as argon, and the pre-bake time is 35 seconds or longer (for example, the shortest 35 seconds).

  After the pre-baking process, a silicon epitaxial layer is formed on the silicon crystal substrate by the CVD method (step S4). Here, the process temperature of epitaxial growth is in the range of 1000 to 1090 ° C., and preferably in the range of 1050 to 1080 ° C. By adopting this temperature condition, the generation of SF is suppressed.

With the above manufacturing process, the electrical resistivity of the silicon crystal substrate is very low within the range of 0.8 × 10 ^{−3 to} 1.5 × 10 ⁻³ Ω / cm, and misfit dislocations in the silicon epitaxial layer are reduced. It is extremely practical and sufficiently practical for power MOS transistors that the number of LPDs due to SF (stacking fault) is 10 or less per 100 cm ² of wafer surface area, preferably about ^{2 to} 0 per 100 cm ² of wafer surface area. A silicon epitaxial wafer is manufactured.

  As described above, a high-quality silicon epitaxial wafer having a very low electrical resistivity of the silicon crystal substrate and a very low LPD due to SF (stacking fault) cannot be manufactured by the conventional manufacturing method. It can be produced only by the production method according to the present invention.

  As mentioned above, although preferred embodiment of this invention was described, this is an illustration for description of this invention, and is not the meaning which limits the scope of the present invention only to this embodiment. The present invention can be implemented in various modes different from the above-described embodiments without departing from the gist thereof. For example, phosphorus is adopted as the material for the electrical resistivity lowering dopant in the above embodiment. However, the manufacturing method of the present invention is also effective in the case where not only phosphorus but also other dopant materials capable of high concentration doping, such as boron, are employed as dopants for lowering electrical resistivity.

The characteristic view which shows the result of having investigated experimentally the relationship between the process temperature of epitaxial growth on the silicon crystal substrate with which phosphorus and germanium were doped at high concentration at the time of silicon crystal growth, and the number of LPD. The flowchart which shows the flow of manufacture of the epitaxial silicon wafer which concerns on one Embodiment of this invention.

Claims (11)

In the method of manufacturing an epitaxial silicon wafer,
A first step of preparing a silicon crystal substrate doped with N-type or P-type resistivity lowering dopant and germanium during silicon crystal growth;
A second step in which oxygen is annealed out from the surface layer of the silicon crystal substrate, and a pre-bake treatment of the silicon crystal substrate is performed for the purpose of surface modification;
And a third step of forming a silicon epitaxial layer on the silicon crystal substrate by a CVD method at a temperature within a range of 1000 to 1090 ° C. after the second step. In the manufacturing method of the epitaxial silicon wafer according to claim 1,
Manufacturing of an epitaxial silicon wafer, wherein the concentration of germanium of the silicon crystal substrate prepared in the first step is in a range of 7.0 × 10 ^{19 to} 1.0 × 10 ²⁰ atoms / cm ^3. Method. In the manufacturing method of the epitaxial silicon wafer of any one of Claim 1 or 2,
The method for producing an epitaxial silicon wafer, wherein the temperature in the third step is in a range of 1050 to 1080 ° C. In the manufacturing method of the epitaxial silicon wafer according to any one of claims 1 to 3,
The concentration of the electric resistivity decreasing dopant in the silicon crystal substrate prepared in the first step is in a range of 4.7 × 10 ^{19 to} 9.47 × 10 ¹⁹ atoms / cm ^3. A method for manufacturing an epitaxial silicon wafer. In the manufacturing method of the epitaxial silicon wafer according to any one of claims 1 to 4,
Manufacturing of an epitaxial silicon wafer, wherein the electrical resistivity of the silicon crystal substrate prepared in the first step is in a range of 0.8 × 10 ^{−3 to} 1.5 × 10 ⁻³ Ω / cm. Method. In the manufacturing method of the epitaxial silicon wafer according to any one of claims 1 to 5,
In the second step, the pre-baking process is performed in a hydrogen gas or inert gas atmosphere in a temperature range of 1150 to 1200 ° C. for a period of 35 seconds or more. In the manufacturing method of the epitaxial silicon wafer according to any one of claims 1 to 6,
A method for producing an epitaxial silicon wafer, wherein phosphorus is used as the dopant for lowering electrical resistivity. In the manufacturing method of the epitaxial silicon wafer according to any one of claims 1 to 6,
A method for producing an epitaxial silicon wafer, wherein boron is used as the dopant for lowering electrical resistivity. A silicon crystal substrate doped with N-type or P-type resistivity lowering dopant and germanium when growing silicon crystal;
A silicon epitaxial layer formed on the surface of the silicon crystal substrate,
An epitaxial silicon wafer, wherein the number of light point defects on the surface of the silicon epitaxial layer due to stacking faults is 10 or less per 100 cm ^{2 of} surface area. The epitaxial silicon wafer according to claim 9, wherein
An epitaxial silicon wafer, wherein the concentration of germanium in the silicon crystal substrate is in a range of 7.0 × 10 ^{19 to} 1.0 × 10 ²⁰ atoms / cm ³ . The epitaxial silicon wafer according to claim 8,
The concentration of the dopant for lowering electrical resistivity of the silicon crystal substrate is in the range of 4.7 × 10 ^{19 to} 9.47 × 10 ¹⁹ atoms / cm ³ , and the concentration of germanium is 7.0 × 10 ¹⁹ to 1. An epitaxial silicon wafer characterized by being in a range of 0.0 × 10 ²⁰ atoms / cm ³ .

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