JP2011228330A - Silicon epitaxial wafer manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon epitaxial wafer which comprises an epitaxial layer with a desired resistance rate and a silicon wafer with a still lower resistance rate than a conventional one, which improves electrical characteristics of elements, and which suppresses autodoping during epitaxial growth more easily than before.SOLUTION: A silicon etched wafer with boron doped at a concentration of 1.0×10atoms/cmor more is prepared, and a step to form a CVD oxide film on a reverse side of the prepared silicon etched wafer is executed. Then a step to remove the CVD oxide film which wraps around a surface side is executed by mirror polishing the surface of the silicon etched wafer. After that, a step to form an oxide film is executed by wet oxidation at a temperature of 1100°C or less, and then, a step to remove the oxide film on the surface side is executed by etching. An epitaxial layer is formed on the surface of the side where the oxide film is removed in the etching step.

Description

  The present invention uses a P-type low resistivity silicon wafer whose dopant is substantially limited to boron, and can form a silicon epitaxial layer capable of forming a high resistance epitaxial layer having a steep dopant distribution. The present invention relates to a method for manufacturing a wafer.

  Most switching transistors such as power MOS transistors and IGBTs (Insulated Gate Bipolar Transistors) that pass current from the front surface to the back surface use an epitaxial wafer.

The reason is that the resistivity of the relatively high resistance epitaxial layer required to ensure the breakdown voltage of the element and the silicon wafer, which becomes a parasitic resistance in the conductive state, can be controlled independently.
For this reason, particularly in a low-voltage power MOS or the like in which the resistivity of the silicon wafer strongly influences the on-resistance, the reduction of the resistance of the silicon wafer has been actively promoted.

Here, in a P-type silicon wafer, boron is generally used as a dopant. This is because boron has a high solid solubility in silicon, a solid solubility of about 1 × 10 ²⁰ atoms / cm ³ at 800 ° C., and can be relatively easily doped at a high concentration, that is, low resistance. is there.

  In recent years, the development of low-voltage power MOS technology has progressed, and the ratio of the resistance component of the silicon wafer part in the power loss (on-resistance) has increased. At present, when the resistivity of the epitaxial layer is 1 Ωcm or less, silicon wafers having a resistivity of 5 mΩcm or less are also widely used.

  However, when boron is used as the dopant, so-called auto-doping in which the dopant diffused from the silicon wafer into the growth atmosphere is re-doped to the epitaxial layer during the formation of the epitaxial layer, or from the silicon wafer to the epitaxial layer during heat treatment during device manufacturing. However, there is a problem that the amount of the dopant diffused into the solid becomes large.

For this reason, it is necessary to increase the thickness of the epitaxial layer, which causes deterioration of on-resistance and breakdown voltage controllability of the element.
However, in the P-type, a practical dopant is limited to boron that is likely to cause auto-doping or out-diffusion (hereinafter also referred to as outward diffusion).

In addition, autodoping is a phenomenon in which the dopant diffused outwardly from the silicon wafer into the epitaxial growth atmosphere is specifically taken into the epitaxial layer (see FIG. 4-a)), in order to suppress this autodoping. It is most effective to prevent the dopant from diffusing out.
For this reason, the back surface is widely sealed with a non-doped oxide film or the like (see FIG. 4B), for example. Among these, as for the low resistance boron-doped wafer, a wafer having a seal film formed on the back surface has been widely used.
In addition, a means is also used in which a through-hole is provided in the susceptor of the single-wafer epitaxial apparatus, and carrier gas is allowed to flow to the back side of the susceptor to suppress dopant reuptake (see FIG. 4-c).

JP 58-95819 A

The out-diffusion can be suppressed to some extent by the measures described above and the lowering of the device process. Therefore, a silicon wafer of 5 mΩcm or less is used as a substrate particularly for a low breakdown voltage MOS application using a low-resistance epitaxial layer. It has come to be used as.
However, on the surface side where epitaxial growth is carried out, preventive measures against out-diffusion using a seal film cannot be applied. Therefore, when using a low-resistance silicon wafer as a substrate and attempting to grow a high-resistance epitaxial layer, autodoping is still a problem. It was.

  In addition, when the resistivity of the epitaxial layer is high, so-called auto-doping or out-diffusion occurs during epitaxial growth, making it difficult to secure an epitaxial layer with a predetermined flat resistivity, and it is necessary to grow a thick epitaxial layer to some extent. However, this not only makes it difficult to manage the resistivity of the epitaxial layer, but also has the problem that it has the opposite effect on reducing the on-resistance of the element, which is the original purpose.

As described above, in recent years, the process temperature has been lowered with the miniaturization of devices, and the use of single-wafer epitaxial devices has been promoted due to the larger diameter of the wafer. Can be shortened.
For this reason, out diffusion has been suppressed. However, the resistance of silicon wafers has been reduced accordingly. In addition, since the single wafer epitaxial apparatus starts high-speed growth immediately after pre-baking, the outwardly diffused dopant is difficult to be purged, and the auto-doping problem still remains.

  In an image pickup device, a high frequency device, and the like, a relatively high resistance epitaxial layer is used, but even in that case, it may be desirable to use a P-type silicon wafer having a low resistivity as much as possible. However, an epitaxial technique with a small amount of boron autodoping has not been realized and has become a problem.

  The present invention has been made in view of the above problems, and comprises an epitaxial layer having a desired resistivity necessary for obtaining predetermined electrical characteristics of an element and a silicon wafer having a lower resistivity than the conventional one, and has a low withstand voltage power. An object of the present invention is to provide a method for producing a silicon epitaxial wafer, which can realize improvement in electrical characteristics of a MOS, an imaging device, etc., and can easily suppress autodoping during epitaxial growth as compared with the conventional one.

In order to solve the above-mentioned problems, the present invention provides a method for producing a silicon epitaxial wafer, wherein at least boron is doped at a concentration of 1.0 × 10 ¹⁹ atoms / cm ³ or more and is not subjected to mirror polishing. An etched wafer is prepared, a step of forming a CVD oxide film on the back side of the prepared silicon etched wafer is performed, and then the surface of the silicon etched wafer is mirror-polished to obtain a flat surface. And the step of removing the CVD oxide film that wraps around the surface side is performed, followed by the step of forming the oxide film by wet oxidation at a temperature of 1100 ° C. or lower, and the oxide film on the surface side is formed An etching process is performed, and an epitaxial layer is formed on the surface where the oxide film is removed in the etching process. To provide a method of manufacturing a silicon epitaxial wafer characterized by Rukoto.

When producing an epitaxial wafer using a silicon wafer doped with boron at a high concentration of 1.0 × 10 ¹⁹ atoms / cm ³ or more, autodoping during vapor phase growth of the epitaxial layer, Suppression of diffusion is very important. Therefore, by forming a CVD oxide film on the back side of the silicon wafer, it is possible to reliably prevent outward diffusion from the back side. However, an unnecessary CVD oxide film is also formed on the front side. However, by performing mirror polishing after forming a CVD oxide film on the etched wafer, the wafer surface can be improved and the unnecessary CVD oxide film can be removed simultaneously, and the mirror polishing is performed only once. Since the process is not performed, the process is not wasted, and the process can be easily performed without being complicated.

  Furthermore, by forming an oxide film by wet oxidation, boron on the surface portion of the silicon wafer can be segregated at a high concentration in the oxide film. By removing this oxide film before forming the epitaxial layer, only the surface of the silicon wafer is boron. The concentration can be lowered. Therefore, boron out-diffusion on the surface during epitaxial growth can be strongly suppressed, and a silicon epitaxial wafer comprising a desired resistivity, for example, a high resistivity epitaxial layer and a low resistivity silicon wafer can be easily manufactured. Can do.

  When the wet oxidation temperature is higher than 1100 ° C., the tendency of segregation of boron in silicon into the oxide film is weakened, and boron in the vicinity of the substrate surface layer diffuses more than necessary into the oxide film, resulting in an epitaxial layer. As a result, the dopant concentration distribution (resistivity distribution) at the substrate interface becomes gradual, the deviation from the resistivity distribution close to the desired step shape increases, and the electrical characteristics of the device and the like cannot be improved as expected. . For this reason, the temperature of wet oxidation shall be 1100 degrees C or less.

  Here, in the etching removal step of the oxide film, it is preferable that the surface-side oxide film is removed by chemical etching, and then the surface is finished and cleaned with an etching amount of 6 nm or less.

  This etching removal process of the oxide film is generally performed with hydrofluoric acid. In this case, specific particles adhere to the surface. These particles can be removed by SC1 and SC2 cleaning, so there is no problem, but etching is performed at nearly 2 nm by one SC1 cleaning. Therefore, the boron concentration of the surface layer does not increase due to many washings, that is, the region with a low boron concentration is etched more than necessary, and the region with a high boron concentration is reliably suppressed from coming out to the surface layer part. The etching amount in the finish cleaning should be limited to 6 nm. This ensures that an interface between the epitaxial layer and the silicon wafer having a sharp dopant profile is obtained.

Further, the in the epitaxial layer forming step, time t _e from completion heated to epitaxial growth _starting, temperature T _e during epitaxial layer _formation, the T a diffusion coefficient of boron in _e D (T _e), the surface _{t O} the heat treatment time in the oxidation film formation process, the heat treatment temperature _{T O,} the diffusion coefficient of boron in said _{T O} when the _{D (T O), 0.2 ×} (D (T e) × t e ) ^1/2 ≦ (D (T _O ) × t _O ) ^1/2 ≦ 5.0 × (D (T _e ) × t _e ) The T _e and the t _e so as to satisfy the relationship of ^1/2. , T _O and t _O are preferably set.

When wet oxidation is performed at a very high temperature for a long time, a region having a boron concentration gradient spreads on the surface side of the silicon wafer, but an epitaxial layer is required for forming a low-voltage power MOS, an image sensor, etc. It is better to narrow the region (transition layer) having a dopant concentration gradient in the vicinity of the interface between the silicon wafer and the silicon wafer so as not to disturb the stepped dopant distribution.
Therefore, the thermal budget ((D (T _O ) × t _O ) ^1/2 ) in the wet oxidation treatment is a thermal budget (outgoing diffusion from the temperature rise in the epitaxial growth step to the start of epitaxial growth ( It is good that it is 5 times or less of (D (T _e ) × t _e ) ^1/2 ).
In addition, if the thermal budget in the wet oxidation process is less than one fifth of the thermal budget in the epitaxial growth process, it becomes difficult to reliably and sufficiently suppress out-diffusion during pre-baking in the formation of the epitaxial layer. .
Therefore, 0.2 × (D (T _e ) × t _e ) ^1/2 ≦ (D (T _O ) × t _O ) ^1/2 ≦ 5.0 × (D (T _e ) × t _e ) ^{1 /} By setting T _e , t _e , T _O and t _O so as to satisfy the relationship of ² , the dopant concentration gradient near the interface between the epitaxial layer and the silicon wafer is steep, that is, the width of the transition layer is narrowed Therefore, a silicon epitaxial wafer having a stepped dopant distribution (resistivity distribution) can be manufactured more reliably.

  In the step of etching the oxide film on the front surface side, it is preferable that the CVD oxide film on the back surface side is etched so that a thickness of 200 nm or more remains.

  Thus, the thickness of the CVD oxide film for suppressing the outward diffusion of boron is ensured by etching so that the CVD oxide film on the back surface side remains by 200 nm or more by etching the oxide film on the front surface side, Boron out-diffusion from the back side in the epitaxial layer forming step can be strongly suppressed, and a silicon epitaxial wafer having an epitaxial layer having a desired resistivity can be obtained more reliably.

  When an epitaxial layer with a low dopant concentration is grown on a high-concentration boron-doped silicon wafer, autodoping from the gas phase and solid diffusion into the epitaxial layer become problems, but the present invention as described above Therefore, the outward diffusion of boron during the formation of the epitaxial layer and the autodoping caused thereby can be strongly suppressed, and the autodoping during the epitaxial growth can be significantly reduced. That is, there is provided a method for producing a silicon epitaxial wafer comprising an epitaxial layer having a desired resistivity necessary for obtaining predetermined electrical characteristics of the device and a silicon wafer having a lower resistivity than conventional ones.

It is the process flow figure showing an example of the manufacturing method of the silicon epitaxial wafer of the present invention. It is the figure which compared the measurement result of the dopant concentration distribution from the wafer surface of the epitaxial wafer of an Example and a comparative example. It is the figure which showed the SIMS (B11) depth profile of the silicon wafer after the wet oxidation which is the manufacturing process of the epitaxial wafer of an Example. It is explanatory drawing which showed the outline | summary of the motion of the dopant impurity in the middle of epitaxially growing an epitaxial layer on the surface of a silicon wafer. It is the figure which showed the magnitude | size of the outward diffusion of the dopant from a silicon wafer, the relationship between surface concentration, and time. It is the figure which showed the relationship between the diffusion coefficient of various elements, and temperature.

Hereinafter, the present invention will be described more specifically.
As described above, in order to manufacture an epitaxial wafer using a silicon wafer having a low resistivity, it is important to suppress outward diffusion and autodoping during the formation of the epitaxial layer.
For autodoping, it is most effective to prevent outward diffusion from the silicon wafer into the epitaxial growth atmosphere. Therefore, sealing the back surface with a non-doped oxide film or the like is widely performed.
However, on the surface side where epitaxial growth is performed, a measure for preventing outward diffusion by the seal oxide film cannot be applied. This outward diffusion from the surface is a problem that remains as a cause of autodoping.

Therefore, in order to reduce the outward diffusion on the silicon wafer surface side, natural oxide film removal annealing is performed at a low temperature, and a thin epitaxial layer is immediately grown to suppress the outward diffusion. A method of suppressing auto-doping on the surface side may be performed by a cap deposition method (two-stage epitaxial growth) in which the epitaxial growth is performed once after purging the substrate.
However, this method has a problem that it is not very effective in suppressing autodoping, although the process is complicated. This is because once the dopant is diffused out of the silicon wafer, the dopant impurity remains in the vicinity of the silicon wafer in various forms such as surface adsorption and infiltration into the poly layer, so that it is difficult to reduce autodoping.

The likelihood of the out-diffusion of the dopant into the atmospheric gas during epitaxial growth is related to the diffusion coefficient of the dopant species, but as shown in FIG. 6, this out-diffusion becomes large with boron having a large diffusion coefficient.
This outdiffusion also depends on the temperature. For this reason, it is only necessary to evaporate the natural oxide film by low-temperature and short-time annealing so that a silicon surface capable of epitaxial growth can be generated. However, in reality, SiGe heteroepitaxial hydrogen termination is practically used. However, the epitaxial layer formed on the surface of the hydrogen-terminated silicon wafer has a problem that defects are likely to occur.

Here, for boron, dichlorosilane or monosilane may be used to form an epitaxial layer because the low-temperature process is effective for both solid diffusion and autodoping.
However, the pre-baking temperature and time for removing the natural oxide film before the growth of the epitaxial layer are the same as in the case of trichlorosilane, so these are not so effective.

By the way, the out-diffusion of the dopant is very large at the initial stage of heating (see t = 0 in FIG. 5) because the surface dopant concentration is large, and eventually the out-diffusion itself is reduced because the surface dopant concentration is reduced. (See t = 1, 2 in FIG. 5).
In consideration of this point, the present inventors considered outdiffusion of the dopant on the substrate surface before epitaxial growth.

Here, when a silicon wafer doped with boron is oxidized, particularly in a wet atmosphere, the silicon side concentration at the interface between silicon and the oxide film (SiO ₂ ) becomes a fraction of the bulk concentration. There is.
Therefore, the boron concentration of the surface layer can be reduced to one fifth or less by wet-oxidizing a silicon wafer doped with boron at a high concentration and etching away the oxide film with hydrofluoric acid or the like. The idea was to be able to suppress the outward diffusion on the front side of the silicon wafer and to seal the back side with a CVD oxide film.

  When a single wafer epitaxial apparatus is used, since the time from when the wafer is heated to an epitaxial growth temperature of about 1100 ° C. until the epitaxial growth starts is about 1 minute, the wafer is heat-treated without an oxide film on the surface. However, the dopant concentration on the surface hardly increases again, and the amount of solid diffusion can be sufficiently reduced.

  Furthermore, the wafer for CVD oxidation for back surface sealing is not a mirror surface wafer but an etched wafer, and the surface side mirror polishing is performed after the CVD oxidation, thereby eliminating the waste of the process and preventing the manufacturing cost from increasing. The present invention was completed with the idea that a silicon epitaxial wafer comprising a high resistivity epitaxial layer and a low resistivity silicon wafer can be produced at low cost.

Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.
First, as shown in FIG. 1A, a silicon etched wafer 11 is prepared that is not subjected to mirror polishing, in which boron is doped at a concentration of 1.0 × 10 ¹⁹ atoms / cm ³ or more. The silicon etched wafer 11 has one main surface as the front surface 11a side and the other main surface as the back surface 11b side.
The silicon etched wafer prepared here is one in which boron is doped at a concentration of 1.0 × 10 ¹⁹ atoms / cm ³ or more, and a wafer (semiconductor single crystal) after an etching process in a general wafer manufacturing process. Other physical properties other than ingot manufacturing, cylindrical grinding process, slicing process, beveling process, lapping process, etching process, and not mirror polishing are not particularly limited, For example, what is produced by slicing a silicon single crystal rod grown by the CZ method may be used. Further, the crystal orientation, crystal diameter, other conditions, and the like may be set as desired according to the standard, and are not particularly limited.

Next, as shown in FIG. 1B, a step of forming a CVD oxide film 12 on the back surface 11b side of the prepared silicon etched wafer 11 is performed.
Although this CVD oxide film formation method may be thermal decomposition or plasma growth, the thermal decomposition CVD method capable of batch processing is most preferable in consideration of productivity.

Then, as shown in FIG. 1C, the surface 11a side of the silicon etched wafer 11 was then mirror-polished to improve the flatness of the surface 11a and wrap around the surface 11a side. A step of removing the CVD oxide film 12 is performed.
The conditions for this mirror polishing are not particularly limited, and can be performed under general conditions.

  Thereafter, as shown in FIG. 1D, a step of forming the oxide film 13 by wet oxidation at a temperature of 1100 ° C. or lower is performed.

When a silicon wafer containing boron is oxidized, the boron concentration on the silicon side becomes a fraction of the bulk concentration at the interface between the silicon and the oxide film (SiO ₂ ). That is, a large amount of boron is segregated in the oxide film, and the boron concentration on the surface of the silicon wafer can be reduced.
Further, in the formation of the oxide film on the surface side, wet oxidation, for example, oxidation in an atmosphere containing water vapor such as pyro-oxidation is effective. This is because the concentration of boron on the silicon surface after removal of the oxide film is about one-half in the case of wet oxidation compared to dry oxidation.

  Further, the amount of dopant that diffuses out is proportional to the dopant concentration on the surface of the silicon wafer as shown in FIG. 5, so that boron is segregated in the oxide film by wet oxidation and removed to remove the silicon wafer after removal. Can reduce the surface dopant concentration. In addition, since a thicker oxide film grows in wet oxidation, there is an advantage that a large amount of boron can be taken in at lower temperature oxidation.

  In this way, by selecting appropriate oxidation conditions (forming an oxide film by wet oxidation at a temperature of 1100 ° C. or lower), the boron concentration on the silicon surface is reduced by utilizing the segregation characteristics of the silicon phase / oxidized phase of boron. be able to. Therefore, reduction of outdiffusion before the start of epitaxial growth and reduction of autodoping are achieved, and it is possible to significantly reduce autodoping that occurs on the epitaxial layer side without deteriorating the dopant distribution at the epitaxial layer-silicon wafer interface. it can.

  In this wet oxidation, when the temperature is higher than 1100 ° C., boron in the region serving as the interface with the epitaxial layer diffuses more than necessary to the oxide film side, and the boron concentration on the silicon wafer surface becomes lower than necessary. The resistivity distribution becomes gradual. Even if an epitaxial layer is formed on such a surface, the dopant concentration distribution (resistivity distribution) at the interface between the epitaxial layer and the silicon wafer will not be stepped, but a gentle distribution. Deviation from distribution increases. For this reason, a silicon epitaxial wafer having a narrow resistivity transition region is not obtained, and it is difficult to improve the electrical characteristics of elements and the like. Accordingly, the wet oxidation temperature is set to 1100 ° C. or lower.

Then, as shown in FIG. 1E, a step of removing the oxide film 13 on the surface 11a side by etching is performed.
The details of this etching step are not particularly limited, and a generally performed method for etching an oxide film can be used. For example, hydrofluoric acid can be used.

Here, in this oxide film etching removal step, after the surface side oxide film is removed by chemical etching, the surface can be finished and cleaned with an etching amount of 6 nm or less.
Etching removal of the oxide film is generally performed using hydrofluoric acid, but it is well known that specific particles adhere to the etched surface when hydrofluoric acid is used. However, since these particles can be removed by SC1 and SC2 cleaning, there is no problem in the formation of an epitaxial layer or the like, but the surface of the silicon wafer is etched by nearly 2 nm in one SC1 cleaning.
Therefore, when this SC1 and SC2 cleaning is performed a plurality of times, regions with a low boron concentration are removed by etching, and regions with a high boron concentration appear on the surface, but this reduces the boron concentration by the previous wet oxidation. The meaning will fade. Therefore, it is important to limit the etching amount in the finish cleaning to 6 nm or less, and this makes it possible to reliably manufacture a silicon epitaxial wafer having a sharp dopant profile.

In addition, the thickness of the region having a low boron concentration can be kept to some extent, and the risk that the resistivity of the epitaxial layer increases due to the diffusion of boron from the silicon wafer to the epitaxial layer in the heat treatment during the device manufacturing process can be reduced. Therefore, the thickness of the epitaxial layer can also be reduced by a corresponding amount with respect to a predetermined breakdown voltage as compared with the conventional case.
Therefore, in the method for manufacturing a silicon epitaxial wafer according to the present invention, it is desirable that a device is manufactured using a sample with a varying thickness, and the characteristics are confirmed and optimized. By doing so, the on-resistance can be more easily reduced at the same time as the reduction of the resistance of the silicon wafer.

In the etching process of the oxide film 13 on the front surface 11a side, the CVD oxide film 12 on the back surface 11b side can be etched so that a thickness of 200 nm or more remains. This can be realized, for example, by making the thickness of the CVD oxide film 12 for sealing about 300 nm thicker than the thickness of the oxide film 13 formed on the surface 11a side.
Thus, the thickness of the CVD oxide film that suppresses the outward diffusion of boron on the back surface can be sufficiently secured by etching the front surface side oxide film so that the CVD oxide film on the back surface side remains 200 nm or more. it can. Therefore, it is possible to reliably suppress the outward diffusion of boron from the back surface side during epitaxial growth, and it is possible to grow an epitaxial layer having a desired resistivity more reliably.

And as shown in FIG.1 (f), the silicon epitaxial wafer 10 is obtained by forming the epitaxial layer 14 in the surface of the side by which the oxide film was removed by the etching process.
As a method of forming this epitaxial layer, for example, a vapor phase growth method may be used. When forming a vapor phase growth method, for example, arranged side silicon is exposed silicon wafer having a CVD oxide film on the back surface side of the oxide film has been removed in the previous step on the susceptor by etching as the upper surface, and H ₂ A source gas such as SiHCl ₃ can be introduced into the chamber as a carrier gas, and epitaxial growth can be performed on the surface of the silicon wafer by a CVD method at about 1050 to 1250 ° C.
At this time, the conductivity type, resistivity, thickness, and the like of the epitaxial layer to be formed are not particularly limited, and desired physical properties suitable for the element to be manufactured can be obtained.

Here, in the epitaxial layer forming step, time t _e from completion heated to epitaxial growth _starting, temperature T _e during epitaxial layer _formation, the diffusion coefficient of boron at T _e D (T _e), the surface side the heat treatment time in the oxidation film formation step _{t O,} a heat treatment temperature _T O, the diffusion coefficient of boron at _{T O} when the _{D (T O), 0.2 ×} (D (T e) × t e) 1 ^{/ 2} ≦ (D (T _O ) × t _O ) ^1/2 ≦ 5.0 × (D (T _e ) × t _e ) ^1/2 so as to satisfy the relationship of T _e , t _e , T _O , t _O can be set.

The thermal budget ((D (T _O ) × t _O ) ^1/2 ) in the above wet oxidation treatment is 5 of the thermal budget ((D (T _e ) × t _e ) ^1/2 ) in this epitaxial growth step. If it is at least one-fifth, it becomes easy to suppress the out-diffusion from the silicon wafer surface during the pre-bake during the epitaxial layer growth as much as necessary and sufficient. Therefore, the thermal budget in the wet oxidation treatment is preferably set to 1/5 or more of the thermal budget from the temperature rise in the epitaxial growth process until the epitaxial growth is started.
Further, if the wet oxidation treatment is performed for a long time or at a high temperature, boron is diffused more than necessary in the oxide film, and a region having a boron concentration gradient spreads on the surface side of the silicon wafer. In order to form low-voltage power MOSs, imaging devices, etc., it is better to narrow the region (transition layer) with a dopant concentration gradient near the interface between the epitaxial layer and silicon wafer so as not to disturb the step-type dopant distribution. Is convenient. Therefore, the thermal budget ((D (T _O ) × t _O ) ^1/2 ) in the wet oxidation treatment is the thermal budget ((D (T _e ) ×) from the temperature rise in the epitaxial growth step to the start of epitaxial growth. t _e ) ^1/2 ) is preferably 5 times or less.

Therefore, 0.2 × (D (T _e ) × t _e ) ^1/2 ≦ (D (T _O ) × t _O ) ^1/2 ≦ 5.0 × (D (T _e ) × t _e ) ^{1 /} By setting T _e , t _e , T _O , and t _O so as to satisfy the relationship of ² , and performing wet oxidation or formation of an epitaxial layer, a dopant concentration gradient near the interface between the epitaxial layer and the silicon wafer can be ensured. Therefore, it is possible to manufacture a silicon epitaxial wafer having a stepped dopant distribution (resistivity distribution) more reliably.

In this way, by forming a CVD oxide film on the back side of the silicon etched wafer, outward diffusion from the back side is reliably prevented.
Then, by performing mirror polishing after forming a CVD oxide film on a silicon etched wafer, it is possible to simultaneously remove the unnecessary CVD oxide film while improving the flatness of the wafer surface. It is also very easy to implement.
Furthermore, by forming an oxide film by wet oxidation, boron on the surface portion of the silicon wafer can be aggregated at a high concentration in this oxide film, and the boron concentration can be lowered only on the surface of the silicon wafer. Therefore, the out-diffusion of boron on the surface during epitaxial growth, that is, the occurrence of auto-doping can be strongly suppressed, and a silicon epitaxial wafer having a desired resistivity can be manufactured easily and reliably.

As described above, if the silicon epitaxial wafer manufacturing method of the present invention is used, there is no safety problem, simple equipment is required, and boron is agglomerated in the oxide film, so that the diffusion furnace is contaminated. There is no problem in mass production.
Further, in recent years, a slight increase in the cost of the substrate has been accepted, such as a high-concentration boron-doped crystal co-doped with Ge has come to be used as a starting substrate for an epitaxial wafer. If there is, it is only necessary to add a short wet oxidation step, there is no quality problem, and there is no need to use expensive Ge, so that the cost is excellent.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Examples and comparative examples)
Three silicon etched wafers for epitaxial use were prepared from a CZ single crystal having a diameter of 200 mm, boron dope, conductivity type P, resistivity 10.0 mΩcm, and crystal plane (100).
Then, an undoped, 500 nm thick oxide film was formed by atmospheric pressure CVD on the back side of the three prepared silicon etched wafers.
Then, the mirror polishing of the surface side opposite to the back surface side in which the CVD oxide film was formed was performed.

Thereafter, an oxide film having a thickness of 200 nm was formed on the mirror surface side by pyrooxidation at 1000 ° C. for 60 minutes using a diffusion furnace on two of the three silicon etched wafers (Example).
Thereafter, the silicon wafer after the formation of the oxide film was dipped in a hydrofluoric acid aqueous solution and etched to confirm the water repellency on the mirror surface side and remove the oxide film. At this time, it was confirmed that the CVD oxide film on the wafer back side remained about 200 nm or more from the interference color. In addition, since particles are likely to be generated when immersed in a hydrofluoric acid aqueous solution, the SC1 and SC2 cleaning is performed after cleaning to remove 3 nm of allowance, and the wafer surface is reduced to the same level as a normal mirror polished wafer. It was.
Further, the wet oxide film formation and the oxide film etching removal were not performed on the remaining one sheet (comparative example).

One of the wafers (Examples) subjected to wet oxidation was removed from the process here, and the remaining one and one wafer (Comparative Example) not subjected to wet oxidation were used using a single wafer epitaxial reactor. Epitaxial growth was performed.
Epitaxial growth used trichlorosilane as a silicon source to form an epitaxial layer of 5 μm at 1150 ° C. In the epitaxial growth, pre-baking was performed at 1150 ° C. for 60 seconds.
This condition is that, in the wafer subjected to wet oxidation, the thermal budget of boron (D (t) · t) ^1/2 is (D (1150 ° C.) · (1/60)) ^{1 for the} epitaxial growth process. ^{/ 2 ≒ 0.5 × (0.017)} 1/2 = 0.065μm, with respect to wet oxide growth ^{(D (1,000 ℃) · 1.0} ) 1/2 ≒ 0.08 × (1. 0) ^1/2 = 0.08 μm, 0.2 × 0.065≈0.013 ≦ 0.08 ≦ 5.0 × 0.065≈0.325, 0.2 × (D (T _e ) Xt _e ) ^1/2 ≦ (D (T _O ) × t _O ) ^1/2 ≦ 5.0 × (D (T _e ) × t _e ) ^1/2 is satisfied.

And the thickness of the epitaxial layer of the epitaxial wafer of the produced Example and a comparative example was investigated by the infrared interference method.
As a result, the thickness of the epitaxial layer was in the range of 5.0 to 5.2 μm. Further, the resistivity of the epitaxial layer was found to be 10.5 Ωcm at the wafer center from the measurement by the CV method.

The epitaxial wafer was then subjected to angle polishing and spreading resistance measurement, and the dopant profile was measured. The results are shown in FIG.
As shown in FIG. 2, a clear difference was observed in autodoping from the measurement results of the spreading resistance.

In addition, the boron depth profile from the surface to 1 μm was measured with a quadrupole SIMS on the silicon wafer removed from the process when the wet oxide film was removed with hydrofluoric acid. The results are shown in FIG.
As shown in FIG. 3, the boron concentration on the surface of the substrate is reduced to about 1/7 of the bulk concentration at the stage of removing the oxide film, and the concentration distribution is about 0.2 μm deep from the surface. Then, it was found that the concentration was almost bulky, and the boron concentration distribution had a steep slope.

  As described above, according to the method for manufacturing a silicon epitaxial wafer of the present invention, boron out-diffusion is reduced in the initial temperature rise and pre-bake stages of the epitaxial growth process, which can largely suppress the auto-doping phenomenon and achieve a desired resistance. It was found that a silicon epitaxial wafer having a rate distribution can be manufactured.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

10 ... silicon epitaxial wafer,
DESCRIPTION OF SYMBOLS 11 ... Silicon etched wafer, 11a ... Front surface, 11b ... Back surface, 12 ... CVD oxide film, 13 ... Oxide film, 14 ... Epitaxial layer

Claims (4)

A method for producing a silicon epitaxial wafer, comprising at least:
Preparing a silicon etched wafer in which boron is doped at a concentration of 1.0 × 10 ¹⁹ atoms / cm ³ or more and not subjected to mirror polishing;
Performing a step of forming a CVD oxide film on the back side of the prepared silicon etched wafer;
Thereafter, the surface of the silicon etched wafer is mirror-polished to improve the flatness of the surface and remove the CVD oxide film that has come around to the surface side.
Thereafter, a step of forming an oxide film by wet oxidation at a temperature of 1100 ° C. or lower is performed.
And the step of removing the oxide film on the surface side by etching,
A method for producing a silicon epitaxial wafer, comprising forming an epitaxial layer on a surface on the side from which the oxide film has been removed in the etching step.   2. The silicon according to claim 1, wherein, in the step of removing the oxide film, the surface-side oxide film is removed by chemical etching, and then the surface is finished and cleaned with an etching amount of 6 nm or less. Epitaxial wafer manufacturing method. Wherein the epitaxial layer forming step, time t _e from completion heated to epitaxial growth _starting, temperature T _e during epitaxial layer _formation, the diffusion coefficient of boron in said T _e D (T _e),
The heat treatment time in the oxidation film formation step of the surface t _O, a heat treatment temperature T _O, the diffusion coefficient of boron in said T _O when the D (T _O),
0.2 × (D (T _e ) × t _e ) ^1/2 ≦ (D (T _O ) × t _O ) ^1/2 ≦ 5.0 × (D (T _e ) × t _e ) ^1/2
The method for manufacturing a silicon epitaxial wafer according to claim 1, wherein the T _e , the t _e , the T _O , and the t _O are set so as to satisfy the relationship.   The etching process of the front surface side oxide film is performed so that the thickness of the CVD oxide film on the back side remains at 200 nm or more. A method for manufacturing a silicon epitaxial wafer.

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