CN116525416B - Pretreatment method of silicon epitaxial wafer - Google Patents

Pretreatment method of silicon epitaxial wafer Download PDF

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CN116525416B
CN116525416B CN202310686308.5A CN202310686308A CN116525416B CN 116525416 B CN116525416 B CN 116525416B CN 202310686308 A CN202310686308 A CN 202310686308A CN 116525416 B CN116525416 B CN 116525416B
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epitaxial wafer
silicon epitaxial
preset
temperature
range
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CN116525416A (en
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郭艳敏
王楠
赵堃
莫宇
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China Electronics Technology Advanced Materials Technology Innovation Co ltd
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China Electronics Technology Advanced Materials Technology Innovation Co ltd
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    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02054—Cleaning before device manufacture, i.e. Begin-Of-Line process combining dry and wet cleaning steps
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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Abstract

The application provides a pretreatment method of a silicon epitaxial wafer. The method comprises the following steps: cleaning, rinsing and spin-drying the silicon epitaxial wafer to remove natural oxide layers and impurity residues on the surface of the silicon epitaxial wafer, so as to obtain a dried first silicon epitaxial wafer; placing the first silicon epitaxial wafer in an annealing furnace chamber for annealing treatment, and oxidizing the first silicon epitaxial wafer in a temperature stabilization stage of the annealing treatment to obtain a second silicon epitaxial wafer after the annealing treatment; and cooling the second silicon epitaxial wafer to obtain a target silicon epitaxial wafer so as to perform resistivity test based on the target silicon epitaxial wafer. The application can effectively improve the processing efficiency and the processing process precision of the silicon epitaxial wafer, thereby providing high-quality silicon epitaxial wafer elements for the subsequent resistivity test of the silicon epitaxial wafer and further effectively improving the efficiency and the precision of the resistivity test of the silicon epitaxial wafer.

Description

Pretreatment method of silicon epitaxial wafer
Technical Field
The application relates to the technical field of pretreatment of silicon epitaxial wafers, in particular to a pretreatment method of a silicon epitaxial wafer.
Background
The ultra-high resistance silicon epitaxial wafer with the resistivity of 1000-3000 Ω & cm has excellent noise immunity, so that the ultra-high resistance silicon epitaxial wafer has wide application prospect in the fields of high-performance charge coupled devices and the like. In general, the resistivity requirements of ultra-high-resistance silicon epitaxial wafers are different for different types of elements. Therefore, resistivity testing of ultra-high resistance silicon epitaxial wafers prior to device fabrication is necessary.
At present, the resistivity test method of the silicon epitaxial wafer comprises the following steps: mercury probe method and four probe test method. However, for mercury probe methods, the resistivity test values of the silicon epitaxial wafer are often not accurately represented due to span limitations. For the four-probe test method, the resistivity test is usually carried out on the ultra-high-resistance silicon epitaxial wafer, in order to improve the accuracy of the test, hydrofluoric acid is generally adopted to pretreat the ultra-high-resistance silicon epitaxial wafer so as to remove an oxide layer on the surface of the ultra-high-resistance silicon epitaxial wafer, an H-termination (hydrogen end) state on the surface of the ultra-high-resistance silicon epitaxial wafer is formed, the charge accumulation formed on the ultra-high-resistance silicon epitaxial wafer due to the oxide layer is reduced, and the accuracy of the resistivity test is improved. However, the surface state of the ultra-high resistance silicon epitaxial wafer treated with hydrofluoric acid is unstable. In the process of exposing in the air, the surface of the ultra-high resistance silicon epitaxial wafer can slowly form an oxide layer again. Therefore, the resistivity test value of the ultra-high resistance silicon epitaxial wafer also slowly changes along with the slow oxidization of the ultra-high resistance silicon epitaxial wafer in the air exposure process, and the resistivity test value of the ultra-high resistance silicon epitaxial wafer does not tend to be stable until the ultra-high resistance silicon epitaxial wafer is exposed in the air for more than 48 hours. However, the pretreatment method needs to wait too long, which very affects the efficiency of actually carrying out resistivity test on the ultra-high-resistance silicon epitaxial wafer.
Based on the above, a pretreatment method capable of accurately and efficiently testing the resistivity of the ultra-high-resistance silicon epitaxial wafer is provided, which is a technical problem to be solved by the technicians in the field.
Disclosure of Invention
The embodiment of the application provides a pretreatment method of a silicon epitaxial wafer, which aims to solve the problem that the efficiency and the accuracy of resistivity test of the silicon epitaxial wafer are affected by the pretreatment method of the silicon epitaxial wafer in the prior art.
In a first aspect, an embodiment of the present application provides a method for preprocessing a silicon epitaxial wafer, including:
cleaning, rinsing and spin-drying the silicon epitaxial wafer to remove natural oxide layers and impurity residues on the surface of the silicon epitaxial wafer, so as to obtain a dried first silicon epitaxial wafer;
placing the first silicon epitaxial wafer in an annealing furnace chamber for annealing treatment, and oxidizing the first silicon epitaxial wafer in a temperature stabilization stage of the annealing treatment to obtain a second silicon epitaxial wafer after the annealing treatment;
and cooling the second silicon epitaxial wafer to obtain a target silicon epitaxial wafer, so as to perform resistivity test based on the target silicon epitaxial wafer.
In one possible implementation manner, the annealing treatment of the first silicon epitaxial wafer in the annealing furnace chamber includes:
placing the first silicon epitaxial wafer in an annealing furnace cavity for heating treatment so as to adjust the temperature of the first silicon epitaxial wafer to a first preset temperature range, simultaneously introducing nitrogen in a preset flow range into the cavity, and maintaining the pressure in the cavity to be stable in the preset pressure range, wherein the heating treatment lasts for a first preset time period;
maintaining the temperature of the first silicon epitaxial wafer to be stable in the first preset temperature range so that the first silicon epitaxial wafer is in a temperature stable stage of annealing treatment and lasts for a second preset time period;
and cooling the first silicon epitaxial wafer to adjust the temperature of the first silicon epitaxial wafer to a second preset temperature range, wherein the cooling process lasts for a first preset time period.
In one possible implementation manner, the oxidizing treatment is performed on the first silicon epitaxial wafer, including:
reducing the first flow of nitrogen into the cavity until the first flow is reduced from a preset flow range to zero; simultaneously introducing oxygen into the cavity, and raising the second flow rate of the introduced oxygen to a preset flow rate range; simultaneously maintaining the pressure in the cavity to be stable in a preset pressure range and the temperature of the first silicon epitaxial wafer to be stable in a first preset temperature range, and maintaining the third preset time period;
maintaining the second flow of oxygen in the cavity stable in a preset flow range, the pressure in the cavity stable in a preset pressure range and the temperature of the first silicon epitaxial wafer stable in a first preset temperature range, and continuously oxidizing for a fourth preset time period to prepare an oxide layer on the surface of the first silicon epitaxial wafer;
reducing a second flow rate of oxygen introduced into the cavity until the second flow rate is reduced from a preset flow rate range to zero; simultaneously introducing nitrogen into the cavity, and raising the first flow rate of the introduced nitrogen to a preset flow rate range; and simultaneously, maintaining the pressure in the cavity to be stable in a preset pressure range, and maintaining the temperature of the first silicon epitaxial wafer to be stable in a first preset temperature range for a third preset time period.
In one possible implementation manner, before the first silicon epitaxial wafer is placed in the annealing furnace chamber for heating treatment, the method further includes:
and introducing nitrogen with a preset flow range into an annealing furnace chamber for placing the first silicon epitaxial wafer, so as to purge the first silicon epitaxial wafer, and maintaining the pressure in the chamber stable in a preset pressure range and the temperature of the first silicon epitaxial wafer stable in a second preset temperature range for a third preset time period.
In one possible implementation, the rinsing process for the silicon epitaxial wafer includes:
immersing the silicon epitaxial wafer in flowing deionized water, and turning on a megasonic generator arranged in a rinsing device;
and rinsing the silicon epitaxial wafer for a fourth preset time based on the megasonic wave with the preset frequency and the deionized water generated by the megasonic generator.
In one possible implementation, the flow rate of deionized water is: 3-7 liters/min;
the water temperature of the deionized water is as follows: 20-30 ℃;
the preset frequency is as follows: 800-900 khz.
In one possible implementation, spin-drying the silicon epitaxial wafer includes:
and placing the silicon epitaxial wafer in a spin dryer, and spin-drying the silicon epitaxial wafer for a third preset time based on the spin dryer with the preset rotating speed.
In one possible implementation, the first preset temperature range is: 250-300 ℃;
the second preset temperature range is as follows: 100-150 ℃;
the preset flow range is as follows: 20-40 standard liters/min;
the preset pressure range is as follows: 750-755 Torr;
the first preset duration is as follows: 10-20 minutes;
the second preset time period is as follows: 40-80 minutes;
the third preset time period is as follows: 5-10 minutes;
the fourth preset duration is as follows: 30-60 minutes.
In one possible implementation, adjusting the temperature of the first silicon epitaxial wafer includes:
a heating device with adjustable power is arranged at a preset position in the annealing furnace chamber;
and adjusting the temperature of the first silicon epitaxial wafer by adjusting the heating temperature of the heating device.
In one possible implementation, the cleaning process for the silicon epitaxial wafer includes:
and cleaning the silicon epitaxial wafer by adopting hydrofluoric acid solution to remove the natural oxide layer on the surface of the silicon epitaxial wafer.
The embodiment of the application provides a pretreatment method of a silicon epitaxial wafer, which comprises the steps of cleaning, rinsing and spin-drying the silicon epitaxial wafer to remove natural oxide layers, impurity residues and the like on the surface of the silicon epitaxial wafer, so as to obtain a dried first silicon epitaxial wafer; then placing the first silicon epitaxial wafer in an annealing furnace chamber for annealing treatment, and oxidizing the first silicon epitaxial wafer in a temperature stabilization stage of the annealing treatment, so as to obtain a second silicon epitaxial wafer with a uniform and stable oxide layer prepared on the surface after the annealing treatment is finished; and then, carrying out cooling treatment on the second silicon epitaxial wafer to obtain a target silicon epitaxial wafer so as to carry out resistivity test based on the target silicon epitaxial wafer. For the existing method for testing the resistivity of the silicon epitaxial wafer by forming an oxide layer on the surface of the silicon epitaxial wafer in a natural oxidation mode, the integral pretreatment scheme provided by the application can be used for quickly forming a uniform and stable oxide layer on the surface of the silicon epitaxial wafer, so that the treatment efficiency and the treatment process precision of the silicon epitaxial wafer are effectively improved, and meanwhile, a high-quality silicon epitaxial wafer element is provided for the subsequent resistivity test of the silicon epitaxial wafer, and the efficiency and the precision of the resistivity test of the silicon epitaxial wafer are further effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of an implementation of a method for preprocessing a silicon epitaxial wafer according to an embodiment of the present application;
FIG. 2 is a schematic illustration of a rinsing process provided by an embodiment of the present application;
FIG. 3 is a process flow diagram of an annealing process provided by an embodiment of the present application;
fig. 4 is a schematic diagram of adjusting a temperature of a first silicon epitaxial wafer according to an embodiment of the present application;
fig. 5 is a schematic diagram of a surface temperature zone distribution of a first silicon epitaxial wafer according to an embodiment of the present application.
Detailed Description
In order to make the present solution better understood by those skilled in the art, the technical solution in the present solution embodiment will be clearly described below with reference to the accompanying drawings in the present solution embodiment, and it is obvious that the described embodiment is an embodiment of a part of the present solution, but not all embodiments. All other embodiments, based on the embodiments in this solution, which a person of ordinary skill in the art would obtain without inventive faculty, shall fall within the scope of protection of this solution.
The term "comprising" in the description of the present solution and the claims and in the above-mentioned figures, as well as any other variants, means "including but not limited to", intended to cover a non-exclusive inclusion, and not limited to only the examples listed herein. Furthermore, the terms "first" and "second," etc. are used for distinguishing between different objects and not for describing a particular sequential order.
The implementation of the application is described in detail below with reference to the specific drawings:
fig. 1 is a flowchart of an implementation of a method for preprocessing a silicon epitaxial wafer according to an embodiment of the present application, as shown in fig. 1, where the method for preprocessing a silicon epitaxial wafer according to an embodiment of the present application includes:
step 101: and cleaning, rinsing and spin-drying the silicon epitaxial wafer to remove natural oxide layers and impurity residues on the surface of the silicon epitaxial wafer, thereby obtaining a dried first silicon epitaxial wafer.
In step 101, a technician typically performs a series of operations such as cleaning, rinsing, spin-drying, etc. on the surface of the obtained silicon epitaxial wafer to effectively remove the natural oxide layer and impurity residues on the surface of the current silicon epitaxial wafer, thereby obtaining a dry first silicon epitaxial wafer. Therefore, the quality of the oxide layer prepared on the surface of the silicon epitaxial wafer can be guaranteed, and the method is further beneficial to obtaining a relatively accurate resistivity test value when the resistivity test is carried out on the silicon epitaxial wafer. Alternatively, the silicon epitaxial wafer may be an ultra-high resistance silicon epitaxial wafer applied to the fields of high-performance charge coupled devices and the like.
In one possible implementation, the cleaning process for the silicon epitaxial wafer includes:
and cleaning the silicon epitaxial wafer by adopting hydrofluoric acid solution to remove the natural oxide layer on the surface of the silicon epitaxial wafer.
In this embodiment, optionally, the silicon epitaxial wafer may be soaked in a hydrofluoric acid solution, so that an oxide layer generated by naturally oxidizing the surface of the silicon epitaxial wafer in a natural environment is cleaned and removed, and preparation is made for preparing a uniform and stable oxide layer on the surface of the silicon epitaxial wafer later.
In one possible implementation, the rinsing process for the silicon epitaxial wafer includes:
the silicon epitaxial wafer is immersed in flowing deionized water, and a megasonic generator arranged in a rinsing device is turned on.
And rinsing the silicon epitaxial wafer for a fourth preset time based on the megasonic wave with the preset frequency and the deionized water generated by the megasonic generator.
In this embodiment, fig. 2 is a schematic diagram of a rinsing process according to an embodiment of the present application, and the rinsing device shown in fig. 2 is composed of a quartz container, a megasonic generator, and a deionized water circulation system of 18.25mΩ. When the silicon epitaxial wafer is rinsed, the silicon epitaxial wafer can be placed in a quartz container to be immersed in flowing deionized water, then a switch of a megasonic generator is turned on to generate megasonic waves with preset frequency, and the silicon epitaxial wafer is rinsed under the combined action of the megasonic waves and the flowing deionized water. Therefore, particles, impurities and the like attached to the surface of the silicon epitaxial wafer can be effectively removed, and the rinsing effect on the surface of the silicon epitaxial wafer is improved.
Alternatively, to save cost, deionized water may be used to rinse the surface of the silicon epitaxial wafer in a circulating flow manner. Optionally, the total volume of the quartz container may be 30 liters, 35 liters, etc., the total amount of deionized water in the quartz container may be dynamically maintained at 27 liters, 29 liters, etc., the fourth preset time period may be 30-60 minutes, and in order to ensure the rinsing effect of the silicon epitaxial wafer, the time limit may be 30 minutes, 45 minutes, 60 minutes, etc., which is not limited in the present application.
And for the silicon epitaxial wafer with smaller volume, the silicon epitaxial wafer can be rinsed by using a test basket made of polytetrafluoroethylene materials. That is, the silicon epitaxial wafer is placed in the test basket, and then the test basket containing the silicon epitaxial wafer is placed in the rinsing device for rinsing, so that the rinsing effect of the silicon epitaxial wafer can be effectively guaranteed.
In one possible implementation, the flow rate of deionized water is: 3-7 litres/min.
The water temperature of the deionized water is: 20-30 ℃.
The preset frequency is: 800-900 khz.
In the embodiment, for the process of rinsing the silicon epitaxial wafer, the flow rate of deionized water in the rinsing device can be controlled to be 3-7 liters/min, the water temperature of the deionized water is 20-30 ℃, and the frequency of the megasonic generator is 800-900 kilohertz, so that the rinsing effect of the silicon epitaxial wafer is effectively ensured.
For example, the frequency of the megasonic generator may be 800 khz, 825 khz, 900 khz, etc., the flow rate of deionized water may be 3 l/min, 5 l/min, 7 l/min, etc., and the water temperature of deionized water may be 20 degrees celsius, 25 degrees celsius, 30 degrees celsius, etc., as the present application is not limited thereto.
In one possible implementation, spin-drying the silicon epitaxial wafer includes:
and placing the silicon epitaxial wafer in a spin dryer, and spin-drying the silicon epitaxial wafer for a third preset time based on the spin dryer with the preset rotating speed.
In this embodiment, water stains of deionized water may remain on the surface of the silicon epitaxial wafer after the rinsing treatment, and at this time, the silicon epitaxial wafer may be put into a spin dryer, and spin-drying and drying are performed on the silicon epitaxial wafer by using the spin dryer.
Optionally, the preset rotation speed may be set to 360 rpm, the third preset time period may be set to 5-10 minutes, and for better spin-drying effect, the spin-drying time period may be limited to 5 minutes, 8 minutes, 10 minutes, or the like, which is not limited in the present application.
Step 102: and placing the first silicon epitaxial wafer in an annealing furnace chamber for annealing treatment, and oxidizing the first silicon epitaxial wafer in a temperature stabilization stage of the annealing treatment to obtain a second silicon epitaxial wafer after the annealing treatment.
In step 102, a first silicon epitaxial wafer may be placed in a chamber of a monolithic annealing furnace to anneal the first silicon epitaxial wafer in an annealing furnace chamber. And then preparing a layer of uniform and stable oxide layer on the surface of the first silicon epitaxial wafer in the temperature stabilization stage of the annealing treatment, namely carrying out oxidation treatment on the first silicon epitaxial wafer, so as to obtain a second silicon epitaxial wafer after the annealing treatment is finished.
In one possible implementation, before the first silicon epitaxial wafer is placed in the annealing furnace chamber for temperature raising treatment, the method further includes:
and introducing nitrogen with a preset flow range into an annealing furnace chamber for placing the first silicon epitaxial wafer, so as to purge the first silicon epitaxial wafer, maintain the pressure in the chamber to be stable in a preset pressure range, maintain the temperature of the first silicon epitaxial wafer to be stable in a second preset temperature range and maintain a third preset time period.
In this embodiment, fig. 3 is a process flow chart of an annealing process provided in the embodiment of the present application, and in fig. 3, six processing operations including purging, heating, replacing 1, baking, replacing 2, and cooling are listed. Before the first silicon epitaxial wafer is subjected to temperature rising treatment, the first silicon epitaxial wafer is subjected to purging treatment so as to keep the surface of the first silicon epitaxial wafer dry and clean.
Optionally, the purging treatment on the first silicon epitaxial wafer may be described in detail as follows: and continuously introducing nitrogen with constant flow into the annealing furnace chamber, and maintaining the pressure and the temperature in the chamber constant, wherein the treatment time of the process can be 5-10 minutes. For example, the preset flow range of nitrogen may be: 20-40 standard liters/min; the process temperature of the purging treatment can be maintained at 100-150 ℃; the pressure in the chamber may be maintained at 750-755 torr, etc., as the application is not limited in this regard.
In one possible implementation, adjusting the temperature of the first silicon epitaxial wafer includes:
a heating device with adjustable power is arranged at a preset position in the annealing furnace chamber;
the temperature of the first silicon epitaxial wafer is adjusted by adjusting the heating temperature of the heating device.
In this embodiment, fig. 4 is a schematic diagram of adjusting the temperature of the first silicon epitaxial wafer provided by the embodiment of the present application, and fig. 5 is a schematic diagram of the distribution of the surface temperature area of the first silicon epitaxial wafer provided by the embodiment of the present application, please refer to fig. 3 to 5 together, in which a heating device with adjustable power is specially provided at a preset position in the annealing furnace chamber, and the adjustment of the heating temperature of the heating device can be achieved by adjusting the power of the heating device, so that the accurate adjustment of the temperature of the first silicon epitaxial wafer in the annealing furnace chamber is achieved. According to the embodiment of the application, the temperature of the first silicon epitaxial wafer is accurately controlled by adjusting the temperature in the cavity in a real-time controllable manner, so that the effects of annealing treatment and oxidation treatment are optimized. Illustratively, the predetermined location may be the top and/or the periphery of the annealing furnace chamber, which is not limited in this regard by the present application.
As shown in fig. 4, the heating device may be set as an inner and outer ring bulb, and then the heating temperature of the heating device is adjusted by adjusting the power of the inner ring bulb and the outer ring bulb, so as to realize accurate adjustment of the temperature of the first silicon epitaxial wafer. Fig. 5 shows the temperature distribution of the surface of the first silicon epitaxial wafer during temperature adjustment, wherein for the first silicon epitaxial wafer with a circular cross section, the area close to the center position is an inner ring heating area, namely the area of the inner ring bulb playing a main temperature adjustment role, and the area far away from the center position is an outer ring heating area, namely the area of the outer ring bulb playing a main temperature adjustment role.
In one possible implementation, the annealing treatment is performed by placing the first silicon epitaxial wafer in an annealing furnace chamber, including:
and placing the first silicon epitaxial wafer in an annealing furnace cavity for heating treatment so as to adjust the temperature of the first silicon epitaxial wafer to a first preset temperature range, simultaneously introducing nitrogen in a preset flow range into the cavity, maintaining the pressure in the cavity to be stable in the preset pressure range, and continuously heating for a first preset time.
And maintaining the temperature of the first silicon epitaxial wafer to be stable in a first preset temperature range so that the first silicon epitaxial wafer is in a temperature stable stage of annealing treatment and lasts for a second preset time period.
And cooling the first silicon epitaxial wafer to adjust the temperature of the first silicon epitaxial wafer to a second preset temperature range, wherein the cooling process lasts for a first preset time period.
In this embodiment, as shown in fig. 3, after the purge treatment, when the temperature of the first silicon epitaxial wafer is raised, the temperature of the first silicon epitaxial wafer may be raised to 250-300 degrees celsius by adjusting the outer ring temperature of the outer ring bulb and the inner ring temperature of the inner ring bulb. Illustratively, the power adjustment range of the outer ring bulb may be: the power adjustment range of the inner ring bulb can be 5.2-6.0 kilowatts of 8.0-8.8 kilowatts. At the same time, continuously introducing nitrogen with the flow of 20-40 standard liters/min into the cavity, and maintaining the pressure in the cavity to be stable at 750-755 Torr, wherein the heating treatment process can last for 10-20 minutes.
Then, the temperature of the current first silicon epitaxial wafer is maintained to be stabilized at 250-300 degrees celsius, so that the first silicon epitaxial wafer is in a temperature stabilization stage of the annealing process (i.e., three process operations of substitution 1, baking, and substitution 2 shown in fig. 3). And maintaining for 30-60 minutes at the stage, so as to facilitate forming a uniform and stable oxide layer on the surface of the first silicon epitaxial wafer at the same time.
And then, the temperature corresponding to each of the outer ring bulb and the inner ring bulb can be adjusted, so that the temperature of the first silicon epitaxial wafer is reduced to 100-150 ℃. Illustratively, the power adjustment range of the outer ring bulb may be: the power adjustment range of the inner ring bulb can be 1.2-2.0 kilowatts of 2.0-2.8 kilowatts. At the same time, continuously introducing nitrogen with the flow of 20-40 standard liters/min into the cavity, and maintaining the pressure in the cavity to be stable at 750-755 Torr, wherein the heating treatment process can last for 10-20 minutes.
Thus, the annealing process is completed.
In one possible implementation, the oxidizing the first silicon epitaxial wafer includes:
reducing the first flow of nitrogen into the cavity until the first flow is reduced from a preset flow range to zero; simultaneously introducing oxygen into the cavity, and raising the second flow rate of the introduced oxygen to a preset flow rate range; and simultaneously, maintaining the pressure in the cavity to be stable in a preset pressure range, and maintaining the temperature of the first silicon epitaxial wafer to be stable in a first preset temperature range for a third preset time period.
Maintaining the second flow of oxygen in the cavity stable in a preset flow range, the pressure in the cavity stable in a preset pressure range and the temperature of the first silicon epitaxial wafer stable in a first preset temperature range, and continuously oxidizing for a fourth preset time period to prepare an oxide layer on the surface of the first silicon epitaxial wafer.
Reducing a second flow rate of oxygen introduced into the cavity until the second flow rate is reduced from a preset flow rate range to zero; simultaneously introducing nitrogen into the cavity, and raising the first flow rate of the introduced nitrogen to a preset flow rate range; and simultaneously, maintaining the pressure in the cavity to be stable in a preset pressure range, and maintaining the temperature of the first silicon epitaxial wafer to be stable in a first preset temperature range for a third preset time period.
In this embodiment, as shown in fig. 3, under the replacement 1 treatment operation, the first flow rate of nitrogen in the chamber may be gradually reduced from 20 to 40 standard liters/minute to 0; simultaneously, oxygen is introduced into the cavity, and the second flow rate of the oxygen in the cavity is controlled to gradually rise from 0 to 20-40 standard liters/min, so that the nitrogen is successfully replaced by the oxygen. Meanwhile, the power range of the outer ring bulb is adjusted to be 6.8-7.6 kilowatts, the power range of the inner ring bulb is adjusted to be 4.4-5.2 kilowatts, and the temperature of the first silicon epitaxial wafer is stabilized at 250-300 ℃ based on the power of the inner ring bulb and the outer ring bulb. At the same time, the pressure in the chamber is maintained stable at 750-755 torr. The treatment operation may last from 5 to 10 minutes.
The second flow of oxygen within the chamber is stabilized at 20-40 standard liters per minute during the bake treatment operation. Meanwhile, the power range of the outer ring bulb is maintained to be 6.8-7.6 kilowatts, the power range of the inner ring bulb is maintained to be 4.4-5.2 kilowatts, and the temperature of the first silicon epitaxial wafer is stabilized at 250-300 ℃ based on the power of the inner ring bulb and the outer ring bulb. At the same time, the pressure in the chamber is maintained stable at 750-755 torr. The treatment operation may last from 30 to 60 minutes.
Under the replacement 2 treatment operation, the second flow rate of oxygen in the cavity can be gradually reduced from 20-40 standard liters/min to 0; at the same time, nitrogen is introduced into the cavity, and the first flow rate of the nitrogen in the cavity is controlled to gradually rise from 0 to 20-40 standard liters/min, so that oxygen is successfully replaced by the nitrogen. Meanwhile, the power range of the outer ring bulb is maintained to be 6.8-7.6 kilowatts, the power range of the inner ring bulb is maintained to be 4.4-5.2 kilowatts, and the temperature of the first silicon epitaxial wafer is stabilized at 250-300 ℃ based on the power of the inner ring bulb and the outer ring bulb. At the same time, the pressure in the chamber is maintained stable at 750-755 torr. The treatment operation may last from 5 to 10 minutes.
In this embodiment, in the annealing process, the first silicon epitaxial wafer is annealed by replacing nitrogen with oxygen, and the method of simultaneously introducing nitrogen and oxygen is not used, which aims to: the first silicon epitaxial wafer is subjected to oxidation annealing in a mode of replacing nitrogen with oxygen, so that the oxidation effect and the annealing efficiency of the surface of the first silicon epitaxial wafer can be remarkably improved. In addition, at the temperature stabilization stage of the annealing treatment, nitrogen may form trace amounts of nitride on the surface of the first silicon epitaxial wafer at high temperature, which extremely affects the oxidation effect of the first silicon epitaxial wafer, and therefore, the trace amounts of nitride can be effectively eliminated by replacing nitrogen with oxygen. In addition, by oxidizing the first silicon epitaxial wafer at the temperature stabilization stage, the problem of unstable oxidation effect caused by oxidizing the first silicon epitaxial wafer at the time of the temperature increase treatment can be effectively eliminated.
In one possible implementation, according to actual needs, the first preset temperature range may be: 250-300 ℃. Alternatively, the first preset temperature may be 250 degrees celsius, 275 degrees celsius, 300 degrees celsius, or the like, which is not limited by the present application.
According to actual needs, the second preset temperature range may be: 100-150 ℃. Alternatively, the second preset temperature may be 100 degrees celsius, 125 degrees celsius, 150 degrees celsius, or the like, which is not limited by the present application.
According to actual needs, the preset flow range may be: 20-40 standard liters/min. Alternatively, the preset flow rate may be 20 standard liters/minute, 30 standard liters/minute, 40 standard liters/minute, or the like, which is not limited in the present application.
According to actual needs, the preset pressure range may be: 750-755 torr. Alternatively, the predetermined pressure may be 750 torr, 752 torr, 755 torr, or the like, which is not limited by the present application.
According to actual needs, the first preset duration may be: 10-20 minutes. Alternatively, the first preset duration may be 10 minutes, 15 minutes, 20 minutes, or the like, which is not limited in the present application.
According to actual needs, the second preset duration may be: 40-80 minutes. Alternatively, the second preset time period may be 40 minutes, 60 minutes, 80 minutes, or the like, which is not limited in the present application.
According to actual needs, the third preset duration may be: 5-10 minutes. Alternatively, the third preset duration may be 5 minutes, 7 minutes, or 10 minutes, which is not limited in the present application.
According to actual needs, the fourth preset duration may be: 30-60 minutes. Alternatively, the fourth preset duration may be 30 minutes, 45 minutes, 60 minutes, or the like, which is not limited in the present application.
Step 103: and cooling the second silicon epitaxial wafer to obtain a target silicon epitaxial wafer so as to perform resistivity test based on the target silicon epitaxial wafer.
In step 103, the annealed second silicon epitaxial wafer may be cooled to room temperature in a monolithic annealing furnace, and then taken out to obtain a target silicon epitaxial wafer, so as to perform a resistivity test based on the target silicon epitaxial wafer. The pretreatment method for the silicon epitaxial wafer provided by the embodiments effectively shortens the process time for pretreatment of the silicon epitaxial wafer, and further improves the efficiency of resistivity test of the silicon epitaxial wafer.
The embodiment of the application provides a pretreatment method of a silicon epitaxial wafer, which comprises the steps of cleaning, rinsing and spin-drying the silicon epitaxial wafer to remove natural oxide layers, impurity residues and the like on the surface of the silicon epitaxial wafer, so as to obtain a dried first silicon epitaxial wafer; then placing the first silicon epitaxial wafer in an annealing furnace chamber for annealing treatment, and oxidizing the first silicon epitaxial wafer in a temperature stabilization stage of the annealing treatment, so as to obtain a second silicon epitaxial wafer with a uniform and stable oxide layer prepared on the surface after the annealing treatment is finished; and then, carrying out cooling treatment on the second silicon epitaxial wafer to obtain a target silicon epitaxial wafer so as to carry out resistivity test based on the target silicon epitaxial wafer. For the existing method for testing the resistivity of the silicon epitaxial wafer by forming an oxide layer on the surface of the silicon epitaxial wafer in a natural oxidation mode, the integral pretreatment scheme provided by the application can be used for quickly forming a uniform and stable oxide layer on the surface of the silicon epitaxial wafer, so that the treatment efficiency and the treatment process precision of the silicon epitaxial wafer are effectively improved, and meanwhile, a high-quality silicon epitaxial wafer element is provided for the subsequent resistivity test of the silicon epitaxial wafer, and the efficiency and the precision of the resistivity test of the silicon epitaxial wafer are further effectively improved.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application. Moreover, the above-mentioned embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (8)

1. The pretreatment method of the silicon epitaxial wafer is characterized by comprising the following steps of:
cleaning, rinsing and spin-drying the silicon epitaxial wafer to remove natural oxide layers and impurity residues on the surface of the silicon epitaxial wafer, so as to obtain a dried first silicon epitaxial wafer;
placing the first silicon epitaxial wafer in an annealing furnace chamber for annealing treatment, and oxidizing the first silicon epitaxial wafer in a temperature stabilization stage of the annealing treatment to obtain a second silicon epitaxial wafer after the annealing treatment;
cooling the second silicon epitaxial wafer to obtain a target silicon epitaxial wafer, and performing resistivity test based on the target silicon epitaxial wafer;
placing the first silicon epitaxial wafer in an annealing furnace chamber for annealing treatment, wherein the annealing treatment comprises the following steps:
placing the first silicon epitaxial wafer in an annealing furnace cavity for heating treatment so as to adjust the temperature of the first silicon epitaxial wafer to a first preset temperature range, simultaneously introducing nitrogen in a preset flow range into the cavity, and maintaining the pressure in the cavity to be stable in the preset pressure range, wherein the heating treatment lasts for a first preset time period;
maintaining the temperature of the first silicon epitaxial wafer to be stable in the first preset temperature range so that the first silicon epitaxial wafer is in a temperature stable stage of annealing treatment and lasts for a second preset time period;
cooling the first silicon epitaxial wafer to adjust the temperature of the first silicon epitaxial wafer to a second preset temperature range, wherein the cooling process lasts for a first preset time period;
adjusting the temperature of the first silicon epitaxial wafer, comprising:
a heating device with adjustable power is arranged at a preset position in the annealing furnace chamber;
the temperature of the first silicon epitaxial wafer is adjusted by adjusting the heating temperature of the heating device;
the heating device comprises an outer ring bulb and an inner ring bulb which are concentrically arranged;
when the temperature raising treatment is carried out, the power adjusting range of the outer ring bulb is 8.0-8.8 kilowatts, the power adjusting range of the inner ring bulb is 5.2-6.0 kilowatts, and when the temperature lowering treatment is carried out, the power adjusting range of the outer ring bulb is 2.0-2.8 kilowatts, and the power adjusting range of the inner ring bulb is 1.2-2.0 kilowatts.
2. The method for pretreating a silicon epitaxial wafer according to claim 1, wherein oxidizing the first silicon epitaxial wafer comprises:
reducing the first flow of nitrogen into the cavity until the first flow is reduced from a preset flow range to zero; simultaneously introducing oxygen into the cavity, and raising the second flow rate of the introduced oxygen to a preset flow rate range; simultaneously maintaining the pressure in the cavity to be stable in a preset pressure range and the temperature of the first silicon epitaxial wafer to be stable in a first preset temperature range, and maintaining the third preset time period;
maintaining the second flow of oxygen in the cavity stable in a preset flow range, the pressure in the cavity stable in a preset pressure range and the temperature of the first silicon epitaxial wafer stable in a first preset temperature range, and continuously oxidizing for a fourth preset time period to prepare an oxide layer on the surface of the first silicon epitaxial wafer;
reducing a second flow rate of oxygen introduced into the cavity until the second flow rate is reduced from a preset flow rate range to zero; simultaneously introducing nitrogen into the cavity, and raising the first flow rate of the introduced nitrogen to a preset flow rate range; and simultaneously, maintaining the pressure in the cavity to be stable in a preset pressure range, and maintaining the temperature of the first silicon epitaxial wafer to be stable in a first preset temperature range for a third preset time period.
3. The method for pretreating a silicon epitaxial wafer according to claim 1 or 2, further comprising, before placing the first silicon epitaxial wafer in an annealing furnace chamber for heating treatment:
and introducing nitrogen with a preset flow range into an annealing furnace chamber for placing the first silicon epitaxial wafer, so as to purge the first silicon epitaxial wafer, and maintaining the pressure in the chamber stable in a preset pressure range and the temperature of the first silicon epitaxial wafer stable in a second preset temperature range for a third preset time period.
4. A pretreatment method of a silicon epitaxial wafer according to claim 3, characterized in that the rinsing treatment of the silicon epitaxial wafer comprises:
immersing the silicon epitaxial wafer in flowing deionized water, and turning on a megasonic generator arranged in a rinsing device;
and rinsing the silicon epitaxial wafer for a fourth preset time based on the megasonic wave with the preset frequency and the deionized water generated by the megasonic generator.
5. The method for pretreating a silicon epitaxial wafer of claim 4, wherein the flow rate of deionized water is: 3-7 liters/min;
the water temperature of the deionized water is as follows: 20-30 ℃;
the preset frequency is as follows: 800-900 khz.
6. The method for pretreating a silicon epitaxial wafer according to claim 4, wherein spin-drying the silicon epitaxial wafer comprises:
and placing the silicon epitaxial wafer in a spin dryer, and spin-drying the silicon epitaxial wafer for a third preset time based on the spin dryer with the preset rotating speed.
7. The method for pretreatment of silicon epitaxial wafer of claim 6, wherein the first preset temperature range is: 250-300 ℃;
the second preset temperature range is as follows: 100-150 ℃;
the preset flow range is as follows: 20-40 standard liters/min;
the preset pressure range is as follows: 750-755 Torr;
the first preset duration is as follows: 10-20 minutes;
the second preset time period is as follows: 40-80 minutes;
the third preset time period is as follows: 5-10 minutes;
the fourth preset duration is as follows: 30-60 minutes.
8. The method for pretreating a silicon epitaxial wafer according to claim 1, wherein the cleaning treatment of the silicon epitaxial wafer comprises:
and cleaning the silicon epitaxial wafer by adopting hydrofluoric acid solution to remove the natural oxide layer on the surface of the silicon epitaxial wafer.
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CN101724911A (en) * 2009-11-30 2010-06-09 北京有色金属研究总院 Surface heat treatment process used before measuring electrical resistivity of P-type silicon epitaxial slice
JP2011228330A (en) * 2010-04-15 2011-11-10 Shin Etsu Handotai Co Ltd Silicon epitaxial wafer manufacturing method
CN104282595A (en) * 2014-10-23 2015-01-14 中国电子科技集团公司第四十六研究所 Method for preparing silicon epitaxy test wafers with multiple sizes compatible

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101140891A (en) * 2006-09-05 2008-03-12 上海华虹Nec电子有限公司 Preparation method of extension testing piece
CN101724911A (en) * 2009-11-30 2010-06-09 北京有色金属研究总院 Surface heat treatment process used before measuring electrical resistivity of P-type silicon epitaxial slice
JP2011228330A (en) * 2010-04-15 2011-11-10 Shin Etsu Handotai Co Ltd Silicon epitaxial wafer manufacturing method
CN104282595A (en) * 2014-10-23 2015-01-14 中国电子科技集团公司第四十六研究所 Method for preparing silicon epitaxy test wafers with multiple sizes compatible

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