CN111524796A - Silicon carbide epitaxial wafer in preparation of silicon carbide power device and processing method thereof - Google Patents

Silicon carbide epitaxial wafer in preparation of silicon carbide power device and processing method thereof Download PDF

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Publication number
CN111524796A
CN111524796A CN202010238731.5A CN202010238731A CN111524796A CN 111524796 A CN111524796 A CN 111524796A CN 202010238731 A CN202010238731 A CN 202010238731A CN 111524796 A CN111524796 A CN 111524796A
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China
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silicon carbide
epitaxial wafer
carbide epitaxial
dielectric layer
front surface
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Inventor
张红丹
焦倩倩
刘瑞
吴昊
李玲
赛朝阳
吴军民
金锐
汤广福
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State Grid Corp of China SGCC
Global Energy Interconnection Research Institute
State Grid Beijing Electric Power Co Ltd
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State Grid Corp of China SGCC
Global Energy Interconnection Research Institute
State Grid Beijing Electric Power Co Ltd
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Priority to CN202010238731.5A priority Critical patent/CN111524796A/en
Publication of CN111524796A publication Critical patent/CN111524796A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/045—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide passivating silicon carbide surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

The invention provides a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device and a processing method thereof, wherein dielectric layers are respectively deposited on the front surface and the back surface of the silicon carbide epitaxial wafer; etching the dielectric layer on the front side of the silicon carbide epitaxial wafer, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer; and carrying out ion implantation on the front surface of the etched silicon carbide epitaxial wafer. The method greatly reduces the warping degree of the silicon carbide epitaxial wafer, reduces the wafer rejection rate, improves the precision of the photoetching process and the processing precision of ion implantation, reduces the wafer rejection rate and the fragment rate of the ion implantation, and greatly improves the precision and the qualification rate of the silicon carbide epitaxial wafer; respective dielectric layers are formed on the front surface and the back surface of the silicon carbide epitaxial wafer step by step, so that material stress caused by directly depositing the dielectric layers on the front surface of the silicon carbide epitaxial wafer is counteracted, and a foundation is provided for improving the warping degree of the silicon carbide epitaxial wafer; low cost, high efficiency and is suitable for various specifications of silicon carbide epitaxial wafers.

Description

Silicon carbide epitaxial wafer in preparation of silicon carbide power device and processing method thereof
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a silicon carbide epitaxial wafer in preparation of a silicon carbide power device and a processing method thereof.
Background
The third generation semiconductor silicon carbide (SiC) material has great difference with the electrical parameters of the traditional silicon (Si) base semiconductor substrate material. The SiC material has larger thermal conductivity, wider forbidden gap, higher electronic saturation velocity and breakdown voltage and lower dielectric constant, the application potential of the SiC material in the aspects of high-temperature, high-frequency and high-power semiconductor devices and the like is determined by the characteristics, and the research and development focus in the current semiconductor field is gradually transferred to the silicon carbide material. The difference of physical parameters of the silicon carbide material and the silicon material is large, because the diffusion coefficient of the SiC material is low, the concentration of the silicon carbide material cannot be changed greatly after high-temperature doping by the traditional ion diffusion process, the SiC material cannot be selectively doped by a thermal diffusion method in the actual process, and even if the ion implantation process is used, the silicon carbide material needs to be implanted at high temperature, so that the high ionization rate can be obtained, and meanwhile, the crystal lattice damage can be repaired. Therefore, high temperature ion implantation is a preferred means for selectively doping SiC.
In the preparation of the SiC device, the SiC element doping, namely the ion implantation process, comprises the following steps: depositing a layer of SiO on the surface of the SiC epitaxial wafer by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method2Forming a mesa pattern by photolithography, and transferring the mesa pattern to SiO by etching2On the mask, after removing the photoresist, use SiO2And performing high-temperature ion implantation on the SiC epitaxial wafer by using the pattern as a mask. The silicon carbide power device prepared by the process needs to use a silicon carbide epitaxial wafer with a thicker epitaxial layer, and uses a thicker dielectric film as a masking layer, but the thick mask has larger stress, so that the epitaxial wafer is easy to warp, and the wafer transfer and processing precision of the photoetching process are influenced; in addition, stress is easily introduced in the high-temperature and high-energy ion implantation process, and then the epitaxial wafer is warped in the ion implantation process, so that the processing precision is reduced, and the risk of fragments is faced.
In the prior art, a prepared silicon carbide epitaxial wafer is usually placed into a reaction chamber, the temperature is kept for 10-30min at the temperature of 650-1050 ℃, then the temperature is reduced to be less than or equal to 300 ℃ for 10-15 min, and the silicon carbide epitaxial wafer is taken out of the reaction chamber, so that the warping degree of the silicon carbide epitaxial wafer is reduced by means of high-temperature annealing, but the warping degree of the silicon carbide epitaxial wafer is still large, and the wafer rejection rate is high.
Disclosure of Invention
In order to overcome the defects of large warping degree and high wafer rejection rate of the silicon carbide epitaxial wafer in the prior art, the invention provides a processing method of a silicon carbide epitaxial wafer in preparation of a silicon carbide power device, which comprises the following steps:
respectively depositing dielectric layers on the front surface and the back surface of the silicon carbide epitaxial wafer;
etching the dielectric layer on the front side of the silicon carbide epitaxial wafer, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer;
and carrying out ion implantation on the front surface of the etched silicon carbide epitaxial wafer.
Respectively depositing dielectric layers on the front surface and the back surface of the silicon carbide epitaxial wafer, wherein the depositing dielectric layers comprise:
depositing a first dielectric layer on the front surface of the silicon carbide epitaxial wafer;
after the first dielectric layer is formed for a preset time, depositing a second dielectric layer on the back of the silicon carbide epitaxial wafer;
and after the first dielectric layer is formed for a preset time, depositing a third dielectric layer on the front surface of the silicon carbide epitaxial wafer.
The etching of the dielectric layer on the front side of the silicon carbide epitaxial wafer and the removal of the dielectric layer on the back side of the silicon carbide epitaxial wafer comprise the following steps:
coating photoresist outside a third dielectric layer on the front surface of the silicon carbide epitaxial wafer, and carrying out graphical treatment on the photoresist;
etching the front side of the silicon carbide epitaxial wafer by taking the patterned photoresist as a mask, and removing the photoresist;
coating photoresist on the front surface of the silicon carbide epitaxial wafer;
and carrying out wet etching on the second dielectric layer on the back of the silicon carbide epitaxial wafer.
After the removing of the dielectric layer on the back side, the method further comprises:
and removing the photoresist on the front surface of the silicon carbide epitaxial wafer.
The ion implantation of the front surface of the etched silicon carbide epitaxial wafer comprises the following steps:
determining the ion implantation dosage and the ion implantation temperature;
and carrying out ion implantation on the front surface of the etched silicon carbide epitaxial wafer based on the dosage and the temperature.
After the ion implantation is carried out on the front surface of the etched silicon carbide epitaxial wafer, the method further comprises the following steps:
and removing the third dielectric layer and the first dielectric layer.
The deposition adopts a plasma enhanced chemical vapor deposition method or a low-pressure chemical vapor deposition method.
The first dielectric layer, the second dielectric layer and the third dielectric layer are all one or a combination of at least two of silicon dioxide, silicon nitride and polysilicon.
The thickness of the first dielectric layer is 0.2-10 μm;
the thickness of the second dielectric layer is 0.2-10 μm;
the thickness of the third dielectric layer is 0.2-6 μm.
The ion implantation dosage is 1E11cm-2～1E18cm-2；
The ion implantation temperature is 25-600 ℃.
Before depositing dielectric layers on the front surface and the back surface of the silicon carbide epitaxial wafer respectively, the method comprises the following steps:
and cleaning the silicon carbide epitaxial wafer by adopting an RCA standard cleaning method to remove metals, organic matters and pollutants on the surface of the silicon carbide epitaxial wafer.
The invention also provides a silicon carbide epitaxial wafer in the preparation of the silicon carbide power device, which comprises the following steps: the front surface of the silicon carbide epitaxial wafer and the back surface of the silicon carbide epitaxial wafer;
the front surface of the silicon carbide epitaxial wafer and the back surface of the silicon carbide epitaxial wafer are respectively obtained according to a treatment method.
Compared with the closest prior art, the technical scheme provided by the invention has the following beneficial effects:
according to the processing method of the silicon carbide epitaxial wafer in the preparation of the silicon carbide power device, dielectric layers are respectively deposited on the front surface and the back surface of the silicon carbide epitaxial wafer; etching the dielectric layer on the front side of the silicon carbide epitaxial wafer, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer; ion implantation is carried out on the front surface of the etched silicon carbide epitaxial wafer, so that the warping degree of the silicon carbide epitaxial wafer is greatly reduced, and the wafer rejection rate is reduced;
the processing method provided by the invention improves the precision of the photoetching process and the processing precision of ion implantation, reduces the wafer rejection rate and the fragment rate of the ion implantation, and greatly improves the precision and the qualification rate of the silicon carbide epitaxial wafer;
the processing method provided by the invention forms respective dielectric layers on the front surface and the back surface of the silicon carbide epitaxial wafer step by step, namely, a first dielectric layer is deposited on the front surface of the silicon carbide epitaxial wafer firstly, then a second dielectric layer is deposited on the back surface of the silicon carbide epitaxial wafer, and finally a third dielectric layer is deposited on the front surface of the silicon carbide epitaxial wafer, so that the material stress caused by directly depositing the dielectric layers on the front surface is counteracted, and a foundation is provided for improving the warping degree of the silicon carbide epitaxial wafer;
according to the technical scheme provided by the invention, after the third dielectric layer and the first dielectric layer are etched, the stress on the front surface of the silicon carbide epitaxial wafer is released, the second dielectric layer on the back surface becomes a main factor causing the silicon carbide epitaxial wafer to warp, the front surface of the silicon carbide epitaxial wafer is protected by coating photoresist on the front surface of the silicon carbide epitaxial wafer, the front surface of the silicon carbide epitaxial wafer is prevented from being corroded, the second dielectric layer on the back surface of the silicon carbide epitaxial wafer is subjected to wet etching, and the warping degree of the silicon carbide epitaxial wafer is effectively reduced;
the invention has low cost and high efficiency, and is suitable for various specifications of silicon carbide epitaxial wafers.
Drawings
FIG. 1 is a flow chart of a method for processing a silicon carbide epitaxial wafer in the fabrication of a silicon carbide power device in accordance with an embodiment of the present invention;
FIG. 2 is a schematic illustration of the deposition of a first dielectric layer on the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;
FIG. 3 is a schematic illustration of a second dielectric layer deposited on the backside of a silicon carbide epitaxial wafer in an embodiment of the present invention;
FIG. 4 is a schematic illustration of the deposition of a third dielectric layer on the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;
FIG. 5 is a schematic diagram of applying photoresist on the front surface of the third dielectric layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a process for patterning a photoresist layer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating etching of the front surface of a silicon carbide epitaxial wafer using a patterned photoresist as a mask according to an embodiment of the present invention;
FIG. 8 is a schematic illustration showing removal of photoresist after etching of the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;
FIG. 9 is a schematic illustration of the front side of a silicon carbide epitaxial wafer coated with a photoresist in an embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating a wet etching process performed on a second dielectric layer according to an embodiment of the invention;
FIG. 11 is a schematic diagram illustrating the removal of photoresist after wet etching of the second dielectric layer in an embodiment of the invention;
FIG. 12 is a schematic illustration of ion implantation of the front side of an etched silicon carbide epitaxial wafer in an embodiment of the present invention;
FIG. 13 is a schematic illustration of a silicon carbide epitaxial wafer resulting from the removal of the third dielectric layer and the first dielectric layer in an embodiment of the present invention;
in the figure, 1, a silicon carbide epitaxial wafer, 2, a first dielectric layer, 3, a sample obtained after coating the first dielectric layer, 4, a second dielectric layer, 5, a sample obtained after coating the second dielectric layer, 6, a third dielectric layer, 7, a sample obtained after coating the third dielectric layer, 8, a photoresist coated on the sample 7, 9, the method comprises the steps of obtaining a sample after patterning a photoresist 8, 10 obtaining a sample after etching the front surface of a silicon carbide epitaxial wafer by taking the patterned photoresist as a mask, 11 removing the sample obtained by removing the photoresist 8, 12 removing the photoresist coated on the front surface of the silicon carbide epitaxial wafer before removing a dielectric layer on the back surface, 13 obtaining a sample after coating the photoresist 12, 14 obtaining a sample after performing wet etching on a second dielectric layer, 15 removing the sample obtained by removing the photoresist 12, and 16 obtaining a sample after performing ion implantation on the front surface of the etched silicon carbide epitaxial wafer.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
The embodiment of the invention provides a processing method for preparing a silicon carbide epitaxial wafer in a silicon carbide power device, a specific flow chart is shown in figure 1, and the specific process is as follows:
s101: respectively depositing dielectric layers on the front surface and the back surface of the silicon carbide epitaxial wafer 1;
s102: etching the dielectric layer on the front side of the silicon carbide epitaxial wafer 1, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer 1;
s103: and carrying out ion implantation on the front surface of the etched silicon carbide epitaxial wafer 1.
Before the dielectric layers are respectively deposited on the front surface and the back surface of the silicon carbide epitaxial wafer 1, the silicon carbide epitaxial wafer 1 needs to be cleaned by adopting an RCA standard cleaning method so as to remove metals, organic matters and pollutants on the surface of the silicon carbide epitaxial wafer 1. The specific cleaning process is as follows:
soaking the silicon carbide epitaxial wafer 1 in SC1 cleaning solution to prepare hydrofluoric acid solution (HF: H)2O1: 10), the sample holder was then cleaned, blow dried, and sample 3 was placed on the holder.
Preparing No. 3 liquid (sulfuric acid: H)2O23: 1). It should be noted that: the sulfuric acid is added last, while the water is boiled in another container. After the preparation of the 3# solution is finished, putting the sample 3 into the 3# solution for boiling and washing for about 15min, and taking out; heating the sample 3 to 250 ℃, lifting the bracket with the sample 3 for a little cooling, and then putting the bracket into hot water for flushing.
Preparing solution No. 1 (ammonia water: H)2O2：H2O ═ 1:1:5-1:1: 7): pouring the two into hot water, and heating to 75-85 ℃ for 10-20 min; the rack with sample 3 was then placed in solution # 1 for about 15min, and the rack was removed and placed in hot water for flushing.
Preparing No. 2 liquid (HCl: H)2O2：H2O ═ 1:1: 5): the first two were poured into hot water. After preparation, the stent containing sample 3 was removed and placed in solution # 2 for about 15 min. The rack is then removed, and the hot water is released and flushed.
And (3) washing the sample 3 by adopting 10% hydrofluoric acid for about 5-30 s to remove the oxide layer on the surface of the sample 3. Then, the substrate is rinsed with deionized water for about 20 min.
After a sample is cleaned by adopting an RCA cleaning method, respectively depositing dielectric layers on the front surface and the back surface of a silicon carbide epitaxial wafer 1, and specifically comprises the following steps:
depositing a first dielectric layer 2 on the front surface of the silicon carbide epitaxial wafer 1, as shown in fig. 2, to obtain a sample 3 in fig. 2, wherein the thickness of the first dielectric layer 2 is 0.2-10 μm; in the embodiment of the invention, the first dielectric layer 2 deposited on the front surface is 1.5 mu m SiO2A film; the first dielectric layer 2 deposited on the front surface of the silicon carbide epitaxial wafer 1 can protect the front surface of the silicon carbide epitaxial wafer 1 and prevent the influence of contamination, scratch and the like on the epitaxy; and the influence of the stress of a directly grown thick film can be avoided through multiple film forming, and the warping degree of the silicon carbide epitaxial wafer 1 can be effectively controlled.
After a preset time after the first dielectric layer 2 is formed, depositing a second dielectric layer 4 on the back surface of the silicon carbide epitaxial wafer 1, as shown in fig. 3, to obtain a sample 5 in fig. 3; after the first dielectric layer 2 on the front side is formed, the second dielectric layer 4 needs to be deposited on the back side of the silicon carbide epitaxial wafer 1 as soon as possible, in the embodiment, within 15 minutes after the first dielectric layer 2 is formed, the second dielectric layer 4 is deposited on the back side of the silicon carbide epitaxial wafer 1, the thickness of the second dielectric layer 4 is 0.2-10 mu m, and in the embodiment of the invention, the second dielectric layer 4 is 2.5 mu m of SiO2A film;
after the first dielectric layer 2 is formed for a preset time, depositing a third dielectric layer 6 on the front surface of the silicon carbide epitaxial wafer 1, as shown in fig. 4, to obtain a sample 7 in fig. 4, wherein the thickness of the third dielectric layer 6 is 0.2 μm to 6 μm, and the third dielectric layer 6 is 1 μm SiO in this embodiment2A film.
The dielectric layer can be deposited by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or a Low Pressure Chemical Vapor Deposition (LPCVD) method, and in the embodiment of the invention, the first dielectric layer 2, the second dielectric layer 4 and the third dielectric layer 6 are deposited by a PECVD method. The deposition of the third dielectric layer 6 meets the requirements of high-temperature high-energy ion implantation film masking.
In the step S101, two dielectric layers are formed on the front surface twice, or a thicker dielectric layer is deposited on the front surface, and then a dielectric layer is deposited on the back surface, when a dielectric layer is deposited on each of the front surface and the back surface, the thickness of the dielectric layer deposited on the front surface may be 0.2 μm to 3 μm, and the thickness of the dielectric layer deposited on the back surface is 0.2 μm to 10 μm. The dielectric layer deposited on the back side is used for balancing the warping of the silicon carbide wafer caused by the deposition of the dielectric layer on the front side, regardless of the deposition of the dielectric layer on the front side at one time or the deposition of the dielectric layer on the front side at two times.
Etching the dielectric layer on the front surface of the silicon carbide epitaxial wafer 1, and then removing the dielectric layer on the back surface of the silicon carbide epitaxial wafer 1, wherein the steps of:
coating photoresist 8 outside the third dielectric layer 6 on the front surface of the silicon carbide epitaxial wafer 1, as shown in FIG. 5; then, patterning the photoresist 8, as shown in fig. 6, to obtain a sample 9 in fig. 6; in the embodiment of the invention, before the front surface of the third dielectric layer 6 is coated with the photoresist 8, the front surface of the sample is coated with a layer of HMDS (hexamethyldisilazane) tackifier, the type of the photoresist 8 is AZ703, and the photoresist 8 can be coated by adopting any other positive photoresist in a full-automatic gluing mode or a manual gluing mode. The graphic processing technology comprises the steps of forming a base film (HMDS) by a gas phase, gluing, pre-baking, exposing, post-baking, developing, hardening and developing inspection.
Etching the front surface of the silicon carbide epitaxial wafer 1 by using the patterned photoresist as a mask, as shown in fig. 7, to obtain a sample 10 in fig. 7, and removing the photoresist, as shown in fig. 8, to obtain a sample 11; and carrying out dry etching or wet etching on the front surface of the silicon carbide epitaxial wafer 1 by using the patterned photoresist as a mask to obtain an ion implantation masking pattern, and simultaneously reducing the influence of the front surface dielectric layer stress on the warping degree of the silicon carbide epitaxial wafer.
Coating a photoresist 12 on the front surface of the silicon carbide epitaxial wafer 1 as shown in fig. 9 to obtain a sample 13;
and (3) carrying out wet etching on the second dielectric layer 4 on the back surface of the silicon carbide epitaxial wafer 1 as shown in FIG. 10 to obtain a sample 14, and then removing the photoresist 12 as shown in FIG. 11 to obtain a sample 15. In the embodiment of the present invention, a layer of HMDS (i.e., hexamethyldisilazane) adhesion promoter is coated on the front surface of sample 11, and then photoresist 12 is coated on the front surface of silicon carbide epitaxial wafer 1. In the embodiment of the invention, the BOE corrosion liquid is adopted to carry out wet etching on the second dielectric layer 4, namely, the BOE corrosion liquid is adopted to remove the second dielectric layer 4 on the back surface.
And performing ion implantation on the front surface of the etched silicon carbide epitaxial wafer 1, wherein the ion implantation comprises the following steps:
determining the ion implantation dosage and the ion implantation temperature;
performing ion implantation on the front surface of the etched silicon carbide epitaxial wafer 1 based on the dose and the temperature, as shown in fig. 12, to obtain a sample 16; ion(s)The implantation dose is 1E11cm-2～1E18cm-2(ii) a The ion implantation temperature is 25-600 ℃, and the type of implanted ions is not limited;
after ion implantation is performed on the front surface of the etched silicon carbide epitaxial wafer 1, the third dielectric layer 6 and the first dielectric layer 2 are removed, and the processed silicon carbide epitaxial wafer 1 is obtained, as shown in fig. 13.
The first dielectric layer 2, the second dielectric layer 4 and the third dielectric layer 6 are all one or a combination of at least two of silicon dioxide, silicon nitride and polysilicon.
The practical silicon carbide epitaxial wafer of the embodiment of the invention has a diameter of 100mm, 150mm, 200mm or more and a thickness of 0 to 200 μm. The method for processing the silicon carbide epitaxial wafer 1 in the preparation of the silicon carbide power device provided by the embodiment of the invention is adopted to process the silicon carbide epitaxial wafer 1, so as to obtain the front surface and the back surface of the silicon carbide epitaxial wafer; the warpage of the treated silicon carbide epitaxial wafer is greatly reduced, and the wafer rejection rate is low.
For convenience of description, each part of the above apparatus is separately described as being functionally divided into various modules or units. Of course, the functionality of the various modules or units may be implemented in the same one or more pieces of software or hardware when implementing the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person of ordinary skill in the art can make modifications or equivalent substitutions to the specific embodiments of the present invention with reference to the above embodiments, and any modifications or equivalent substitutions which do not depart from the spirit and scope of the present invention are within the protection scope of the present invention as claimed in the appended claims.

Claims (12)

1. A processing method for preparing a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device is characterized by comprising the following steps:
respectively depositing dielectric layers on the front surface and the back surface of the silicon carbide epitaxial wafer;
etching the dielectric layer on the front side of the silicon carbide epitaxial wafer, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer;
and carrying out ion implantation on the front surface of the etched silicon carbide epitaxial wafer.
2. The method for processing the silicon carbide epitaxial wafer in the preparation of the silicon carbide power device according to claim 1, wherein the depositing dielectric layers on the front surface and the back surface of the silicon carbide epitaxial wafer respectively comprises:
depositing a first dielectric layer on the front surface of the silicon carbide epitaxial wafer;
after the first dielectric layer is formed for a preset time, depositing a second dielectric layer on the back of the silicon carbide epitaxial wafer;
and after the first dielectric layer is formed for a preset time, depositing a third dielectric layer on the front surface of the silicon carbide epitaxial wafer.
3. The method for processing the silicon carbide epitaxial wafer in the preparation of the silicon carbide power device according to claim 2, wherein the step of etching the dielectric layer on the front side of the silicon carbide epitaxial wafer and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer comprises the following steps:
coating photoresist outside a third dielectric layer on the front surface of the silicon carbide epitaxial wafer, and carrying out graphical treatment on the photoresist;
etching the front side of the silicon carbide epitaxial wafer by taking the patterned photoresist as a mask, and removing the photoresist;
coating photoresist on the front surface of the silicon carbide epitaxial wafer;
and carrying out wet etching on the second dielectric layer on the back of the silicon carbide epitaxial wafer.
4. The method for processing the silicon carbide epitaxial wafer in the preparation of the silicon carbide power device according to claim 3, wherein after the removing the dielectric layer on the back surface, the method further comprises:
and removing the photoresist on the front surface of the silicon carbide epitaxial wafer.
5. The method for processing the silicon carbide epitaxial wafer in the preparation of the silicon carbide power device according to claim 3, wherein the step of performing ion implantation on the front surface of the etched silicon carbide epitaxial wafer comprises the following steps:
determining the ion implantation dosage and the ion implantation temperature;
and carrying out ion implantation on the front surface of the etched silicon carbide epitaxial wafer based on the dosage and the temperature.
6. The processing method for preparing the silicon carbide epitaxial wafer in the silicon carbide power device according to claim 5, wherein after the ion implantation is performed on the front surface of the etched silicon carbide epitaxial wafer, the method further comprises:
and removing the third dielectric layer and the first dielectric layer.
7. The method for processing the silicon carbide epitaxial wafer in the preparation of the silicon carbide power device according to claim 2, wherein the deposition adopts a plasma enhanced chemical vapor deposition method or a low pressure chemical vapor deposition method.
8. The processing method for preparing the silicon carbide epitaxial wafer in the silicon carbide power device according to claim 2, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are all one or a combination of at least two of silicon dioxide, silicon nitride and polysilicon.
9. The processing method for preparing the silicon carbide epitaxial wafer in the silicon carbide power device according to claim 2, wherein the thickness of the first dielectric layer is 0.2 μm to 10 μm;
the thickness of the second dielectric layer is 0.2-10 μm;
the thickness of the third dielectric layer is 0.2-6 μm.
10. The method for processing the silicon carbide epitaxial wafer in the preparation of the silicon carbide power device according to claim 5, wherein the ion implantation dosage is 1E11cm-2～1E18cm-2；
The ion implantation temperature is 25-600 ℃.
11. The processing method of the silicon carbide epitaxial wafer in the preparation of the silicon carbide power device according to claim 1, wherein before depositing the dielectric layers on the front surface and the back surface of the silicon carbide epitaxial wafer respectively, the processing method comprises the following steps:
and cleaning the silicon carbide epitaxial wafer by adopting an RCA standard cleaning method to remove metals, organic matters and pollutants on the surface of the silicon carbide epitaxial wafer.
12. A silicon carbide epitaxial wafer in preparation of a silicon carbide power device is characterized by comprising the following components: the front surface of the silicon carbide epitaxial wafer and the back surface of the silicon carbide epitaxial wafer;
the front surface of the silicon carbide epitaxial wafer and the back surface of the silicon carbide epitaxial wafer are obtained by the treatment method according to any one of claims 1 to 9.
CN202010238731.5A 2020-03-30 2020-03-30 Silicon carbide epitaxial wafer in preparation of silicon carbide power device and processing method thereof Pending CN111524796A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115110153A (en) * 2022-06-24 2022-09-27 东莞市天域半导体科技有限公司 Method for reducing warping degree of semiconductor epitaxial wafer
CN115110147A (en) * 2022-06-24 2022-09-27 东莞市天域半导体科技有限公司 Method for growing low-warpage semiconductor substrate wafer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115110153A (en) * 2022-06-24 2022-09-27 东莞市天域半导体科技有限公司 Method for reducing warping degree of semiconductor epitaxial wafer
CN115110147A (en) * 2022-06-24 2022-09-27 东莞市天域半导体科技有限公司 Method for growing low-warpage semiconductor substrate wafer
CN115110153B (en) * 2022-06-24 2024-01-02 广东天域半导体股份有限公司 Method for reducing warping degree of semiconductor epitaxial wafer
CN115110147B (en) * 2022-06-24 2024-01-02 广东天域半导体股份有限公司 Method for growing low-warpage semiconductor substrate wafer

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