JP2002175985A - Method for manufacturing nitride semiconductor epitaxial wafer and the nitride semiconductor epitaxial wafer - Google Patents

Method for manufacturing nitride semiconductor epitaxial wafer and the nitride semiconductor epitaxial wafer

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Publication number
JP2002175985A
JP2002175985A JP2000370391A JP2000370391A JP2002175985A JP 2002175985 A JP2002175985 A JP 2002175985A JP 2000370391 A JP2000370391 A JP 2000370391A JP 2000370391 A JP2000370391 A JP 2000370391A JP 2002175985 A JP2002175985 A JP 2002175985A
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JP
Japan
Prior art keywords
nitride semiconductor
epitaxial wafer
layer
semiconductor epitaxial
sapphire substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2000370391A
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Japanese (ja)
Other versions
JP3729065B2 (en
Inventor
Yuichi Oshima
祐一 大島
Harunori Sakaguchi
春典 坂口
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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Publication of JP2002175985A publication Critical patent/JP2002175985A/en
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Publication of JP3729065B2 publication Critical patent/JP3729065B2/en
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Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor epitaxial wafer and a method of manufacturing the same, with which few crystal defects, bending or cracks occur, and to provide a nitride semiconductor epitaxial wafer which can provide large area. SOLUTION: An intermediate layer 2, 12 is obtained by implanting ions of hydrogen, nitrogen, oxygen, etc., into a nitride semiconductor layer 11 to be peeled, which is formed in the vicinity of the surface of a sapphire substrate 1 or on a hetero substrate 10. Since these intermediate layers 2, 12 have amorphous structures, deformation is absorbed and relieved, thereby reducing cracks, bending, etc. Since the intermediate layers 2, 12 are heated during growth of a nitride semiconductor layer 3, 14 voids occur. The voids are highly effective in absorbing and relieving deformation, reduces cracks, bending, etc., and reduces crystal relaxation, and since the substrate surface is a hetero substrate 10 or the nitride semiconductor layer 14, the deformation absorbing effect of the intermediate layer 2, 12 having voids is increased, and thus a nitride semiconductor epitaxial wafer having high quality and large diameter can be obtained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、窒化物半導体エピ
タキシャルウェハの製造方法及び窒化物半導体エピタキ
シャルウェハに関する。
[0001] The present invention relates to a method for manufacturing a nitride semiconductor epitaxial wafer and a nitride semiconductor epitaxial wafer.

【0002】[0002]

【従来の技術】近年、発光ダイオード(LED)やレー
ザダイオード(LD)等の高出力化、高効率化等を図る
ため、バンドギャップが大きく(3.4eV)、直接遷
移型であり、しかもバンドギャップを広範囲で制御でき
ることから窒化物半導体が用いられるようになってき
た。
2. Description of the Related Art In recent years, in order to achieve high output and high efficiency of a light emitting diode (LED) and a laser diode (LD), a band gap is large (3.4 eV), a direct transition type, and a band is used. Since the gap can be controlled in a wide range, a nitride semiconductor has been used.

【0003】[0003]

【発明が解決しようとする課題】ところで、GaNある
いはその混晶であるAlGaNやInGaN等は実用的
な同種の基板がないため、サファイアやSiC等の異種
基板上で結晶成長が行われる。これら異種基板は格子定
数が成長層と大きく異なるために成長層の結晶欠陥が多
い。また、膨張係数も大きく異なるために厚膜成長時や
成長後に反りやクラックが発生する。これらの反りやク
ラックは特に窒化物半導体厚膜を成長させるときに深刻
な問題となる。
However, since GaN or its mixed crystal, such as AlGaN or InGaN, does not have a practical substrate of the same kind, crystal growth is performed on a heterogeneous substrate such as sapphire or SiC. These dissimilar substrates have a lot of crystal defects in the growth layer because the lattice constant is significantly different from that of the growth layer. Also, since the expansion coefficients are greatly different, warpage and cracks occur during and after the growth of a thick film. These warpages and cracks become serious problems especially when growing a nitride semiconductor thick film.

【0004】そこでこのような問題を根本的に解決する
ためにGaN基板の開発が進められており、高温高圧下
でGaN単結晶を合成する高温高圧法(S.Porow
ski et al,J.Cryst.Growth
178(1997)p174)やサファイヤ基板上にH
VPE法で数百μm程度の厚膜を成長させた後、サファ
イア基板を取り除くことによってGaNの自立単結晶基
板を得る方法(Michael K.Kelly et
al,Jpn.J.Appl.Phys.38(19
99)Pt.2,No.3A,pp.L217)等の方
法が代表的である。
[0004] Therefore, in order to fundamentally solve such a problem, development of a GaN substrate has been advanced, and a high-temperature high-pressure method (S. Porow) for synthesizing a GaN single crystal under high temperature and high pressure has been developed.
Ski et al, J. Mol. Cryst. Growth
178 (1997) p174) or H on a sapphire substrate.
A method of obtaining a GaN free-standing single crystal substrate by removing a sapphire substrate after growing a thick film of about several hundred μm by VPE method (Michael K. Kelly et.
al, Jpn. J. Appl. Phys. 38 (19
99) Pt. 2, No. 3A, pp. L217) and the like are typical.

【0005】しかし、高温高圧法は超高圧セル中で結晶
成長が行われるため、得られるGaN単結晶のサイズを
あまり大きくすることができず、現在のところ直径10
mm程度のものしか得られていない。そのうえ製造コス
トが非常に高く、実用的ではない。HVPE(ハイドラ
イド気相成長法:Hydride Vapor Pha
se Epitaxy)でサファイア基板上に直接Ga
N厚膜を成長させる方法はより現実的ではあるが、この
場合でも結晶欠陥はかなり多く、サファイア基板の実用
的な除去方法が無い。しかも、除去後もGaN厚膜には
反りが残る等の問題がある。
However, in the high-temperature and high-pressure method, since the crystal is grown in an ultra-high-pressure cell, the size of the obtained GaN single crystal cannot be increased so much.
Only about mm is obtained. Moreover, the production cost is very high and not practical. HVPE (Hydride Vapor Pha)
(Se Epitaxy) directly on the sapphire substrate
Although a method of growing an N-thick film is more realistic, even in this case, crystal defects are considerably large, and there is no practical method for removing the sapphire substrate. In addition, there is a problem that the GaN thick film remains warped even after the removal.

【0006】窒化物半導体のエピタキシャル成長の時サ
ファイア基板の反りは、窒化物半導体のエピタキシャル
成長中に、例えばグラファイトのサセプタ等の加熱物体
との接触の不均一を生じ、成長層のキャリア濃度や組成
等の特性を不均一にする。特にInGaNではこの濃度
不均一は致命的である。また、成長後のサファイア基板
の反りは、フォトリソグラフィにおける微細パターンの
露光で大きな問題となる。
During the epitaxial growth of the nitride semiconductor, the warpage of the sapphire substrate causes non-uniform contact with a heated object such as a graphite susceptor during the epitaxial growth of the nitride semiconductor. Uneven characteristics. In particular, in InGaN, this uneven concentration is fatal. Also, warpage of the sapphire substrate after growth poses a major problem in exposing fine patterns in photolithography.

【0007】また、結晶欠陥は光素子の発光特性や信頼
性を悪化させ、電子デバイスのリーク電流や非線形性、
信頼性低下等の原因となる。
Further, the crystal defects deteriorate the light emitting characteristics and reliability of the optical device, and cause leakage current, nonlinearity,
This may cause a decrease in reliability.

【0008】この対策として、選択成長によるラテラル
方向成長を利用したELO法(O.H.Nam et
al,Appl.phys.Lett.71(199
7)2472)やFIELO法(A.Sakai et
al,Appl.Phys.Lett.71(199
7)2259)等が開発されているが、いまだに結晶欠
陥は106 〜107 cm-3ほど存在し、反りの問題はま
ったく改善されていないという問題があった。
As a countermeasure for this, an ELO method (OH Namet) utilizing lateral growth by selective growth is used.
al, Appl. phys. Lett. 71 (199
7) 2472) and the FIELO method (A. Sakai et.
al, Appl. Phys. Lett. 71 (199
7) 2259) has been developed, but there is a problem that crystal defects still exist at about 10 6 to 10 7 cm −3 , and the problem of warpage has not been improved at all.

【0009】一方、反りを軽減する方法に関しては例え
ば特開平9−223819号公報に開示されているよう
に、Si基板の表面より下に酸素若しくは窒素のイオン
打ち込みによって緩和層兼剥離層を形成し、さらに表面
を炭化してSiCとしたSi基板上に窒化物半導体を成
長させ、その後のエッチングによってSi基板を除去す
る方法がある。
On the other hand, with respect to a method of reducing the warpage, as disclosed in, for example, Japanese Patent Application Laid-Open No. 9-223819, a relaxation layer and a release layer are formed below the surface of a Si substrate by ion implantation of oxygen or nitrogen. Further, there is a method in which a nitride semiconductor is grown on a Si substrate whose surface is carbonized to form SiC, and the Si substrate is removed by etching thereafter.

【0010】しかし、この方法では窒化物半導体への応
力を軽減するためにSi基板とそのSi基板上に形成す
るSiC層、AlGaNバッファ層及び窒化物半導体層
構造の厚さのバランスを精密に制御しなければならな
い。特に窒素打ち込みによって形成した窒化物半導体層
を歪み緩和層とした場合、Si基板をエッチングによっ
て除去するためになSiC層と歪み緩和層との間にSi
の層を残さなければならないので、表面炭化の条件が厳
しく、かつ歪み緩和層が窒化物半導体成長層から遠くな
るので、歪み緩和効果が小さくなってしまう。また、基
板表面を完全に覆うほどに表面炭化を行うのは量産を考
えた場合困難である。
However, in this method, in order to reduce the stress on the nitride semiconductor, the balance between the thickness of the Si substrate and the thickness of the SiC layer, the AlGaN buffer layer, and the structure of the nitride semiconductor layer formed on the Si substrate is precisely controlled. Must. In particular, when the nitride semiconductor layer formed by implanting nitrogen is used as a strain relaxation layer, Si is placed between the SiC layer and the strain relaxation layer to remove the Si substrate by etching.
Must be left, the conditions for surface carbonization are severe, and the strain relaxation layer is far from the nitride semiconductor growth layer, so that the strain relaxation effect is reduced. In addition, it is difficult to perform surface carbonization so as to completely cover the substrate surface when considering mass production.

【0011】そこで、本発明の目的は、上記課題を解決
し、結晶欠陥が少なく、反りやクラックの少ない窒化物
半導体エピタキシャルウェハの製造方法及び窒化物半導
体エピタキシャルウェハを提供することにある。
An object of the present invention is to solve the above-mentioned problems and to provide a method of manufacturing a nitride semiconductor epitaxial wafer having few crystal defects and having less warpage and cracks, and a nitride semiconductor epitaxial wafer.

【0012】さらに、本発明の目的は、上記課題を解決
し、結晶欠陥や反りやクラックが少なく大面積の窒化物
半導体エピタキシャルが得られる窒化物半導体エピタキ
シャルウェハの製造方法及び窒化物半導体エピタキシャ
ルウェハを提供することにある。
Further, an object of the present invention is to solve the above-mentioned problems, and to provide a method of manufacturing a nitride semiconductor epitaxial wafer and a nitride semiconductor epitaxial wafer capable of obtaining a large-area nitride semiconductor epitaxial with less crystal defects, warpage and cracks. To provide.

【0013】[0013]

【課題を解決するための手段】上記目的を達成するため
に本発明の窒化物半導体エピタキシャルウェハの製造方
法は、サファイア基板の表面近傍にサファイア基板より
機械的強度の弱い中間層を形成し、中間層を形成したサ
ファイア基板の上にデバイス用窒化物半導体層をエピタ
キシャル成長させるものである。
In order to achieve the above object, a method for manufacturing a nitride semiconductor epitaxial wafer according to the present invention comprises forming an intermediate layer near the surface of a sapphire substrate with a mechanical strength lower than that of a sapphire substrate; A nitride semiconductor layer for a device is epitaxially grown on a sapphire substrate on which a layer is formed.

【0014】本発明の窒化物半導体エピタキシャルウェ
ハの製造方法は、サファイア基板の上に剥離用窒化物半
導体層を形成し、剥離用窒化物半導体層の表面近傍に機
械的強度が該剥離用窒化物半導体層より弱い中間層を形
成し、中間層を形成した剥離用窒化物半導体層の上にデ
バイス用窒化物半導体層をエピタキシャル成長させるも
のである。
According to a method of manufacturing a nitride semiconductor epitaxial wafer of the present invention, a peeling nitride semiconductor layer is formed on a sapphire substrate, and the mechanical strength of the peeling nitride semiconductor layer is increased near the surface of the peeling nitride semiconductor layer. An intermediate layer weaker than the semiconductor layer is formed, and a nitride semiconductor layer for a device is epitaxially grown on the nitride semiconductor layer for separation on which the intermediate layer is formed.

【0015】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、デバイス用窒化物半導
体層の厚さを10μm以下とするのが好ましい。
In addition to the above structure, in the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention, it is preferable that the thickness of the nitride semiconductor layer for a device is 10 μm or less.

【0016】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、剥離用窒化物半導体層
若しくはサファイア基板の表面から中間層を形成すべき
深さにイオンを打ち込むことによって中間層を形成する
のが好ましい。
In addition to the above structure, the method of manufacturing a nitride semiconductor epitaxial wafer of the present invention forms the intermediate layer by implanting ions from the surface of the peeling nitride semiconductor layer or the surface of the sapphire substrate to a depth at which the intermediate layer is to be formed. Is preferred.

【0017】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、イオンとして水素イオ
ン、窒素イオン及び酸素イオンのうち少なくとも1種類
を用いるのが好ましい。
In addition to the above configuration, in the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention, it is preferable to use at least one of hydrogen ions, nitrogen ions and oxygen ions as ions.

【0018】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、イオンの打ち込みの加
速電圧を1keV以上1MeV以下とし、かつ、イオン
のドーズ量を1×1015cm-2以上1×1019cm-2
下とするのが好ましい。
In addition to the above structure, the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention has an ion implantation acceleration voltage of 1 keV or more and 1 MeV or less, and an ion dose of 1 × 10 15 cm −2 or more and 1 ×. It is preferably 10 19 cm -2 or less.

【0019】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、イオンを打ち込んだ
後、熱処理を行ってサファイア基板の表面結晶層若しく
は剥離用窒化物半導体層のイオン打ち込みによるダメー
ジを回復させると共に、表面近傍に微細なボイド及びボ
イドの集合体を生じさせることにより中間層を形成して
もよい。
In addition to the above structure, the method of manufacturing a nitride semiconductor epitaxial wafer of the present invention recovers damage caused by ion implantation of the surface crystal layer of the sapphire substrate or the nitride semiconductor layer for peeling after heat treatment after ion implantation. At the same time, the intermediate layer may be formed by generating fine voids and aggregates of voids in the vicinity of the surface.

【0020】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、ボイド及びボイドの集
合体の大きさ、数量、密度、分布等を熱処理によって制
御するのが好ましい。
In addition to the above configuration, in the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention, it is preferable to control the size, quantity, density, distribution, etc. of the voids and the aggregates of the voids by heat treatment.

【0021】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、熱処理をH2 若しくは
NH3 あるいは両者の混合雰囲気下で行うのが好まし
い。
In addition to the above structure, in the method of manufacturing a nitride semiconductor epitaxial wafer of the present invention, it is preferable that the heat treatment is performed in an atmosphere of H 2 or NH 3 or a mixture of both.

【0022】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、中間層からサファイア
基板までの部分を記中間層を境に剥離させて除去するの
が好ましい。
In addition to the above structure, in the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention, it is preferable that a portion from the intermediate layer to the sapphire substrate is removed by peeling off the intermediate layer.

【0023】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、デバイス用窒化物半導
体層の表面に他の基板を貼り付けた後中間層からサファ
イア基板までの部分を、中間層を境に剥離、除去しても
よい。
In addition to the above structure, the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention comprises the steps of: attaching another substrate to the surface of the nitride semiconductor layer for a device; It may be separated and removed at the boundary.

【0024】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、他の基板としてSi等
の半導体若しくはAlN等の高熱伝導性基板あるいはC
u、Al等の金属を用いてもよい。
In addition to the above structure, the method of manufacturing a nitride semiconductor epitaxial wafer according to the present invention is characterized in that a semiconductor such as Si or a high thermal conductive substrate such as AlN or C
A metal such as u or Al may be used.

【0025】上記構成に加え本発明の窒化物半導体エピ
タキシャルウェハの製造方法は、サファイア基板を除去
したデバイス用窒化物半導体層に残ったサファイア基板
の一部若しくは記サファイア基板を除去したデバイス用
窒化物半導体に残った剥離用窒化物半導体層の一部を研
磨等の方法によって除去してもよい。
In addition to the above structure, the method for manufacturing a nitride semiconductor epitaxial wafer according to the present invention provides a device nitride semiconductor device in which a part of the sapphire substrate remaining in the device nitride semiconductor layer from which the sapphire substrate has been removed or the sapphire substrate has been removed. A part of the peeling nitride semiconductor layer remaining on the semiconductor may be removed by a method such as polishing.

【0026】本発明の窒化物半導体エピタキシャルウェ
ハは上記いずれかに記載の方法で製造された、Inx
y Ga1-x-y N(x,y≧1、x+y≦1)の組成を
有するものである。
The nitride semiconductor epitaxial wafer of the present invention is manufactured by any one of the methods described above, and is manufactured by using In x A
l y Ga 1-xy N ( x, y ≧ 1, x + y ≦ 1) and has a composition.

【0027】本発明によれば、窒化物半導体と異なるサ
ファイア基板の表面近傍若しくはサファイア基板上に形
成された剥離用窒化物半導体層に水素や窒素、酸素等の
イオンを打ち込むことにより得られる中間層は、アモル
ファス的な構造となるため、歪みを吸収、緩和し、クラ
ックや反り等が低減する。水素が打ち込まれた中間層は
窒化物半導体層の成長中に加熱されることによりボイド
が生じる。ボイドは歪みの吸収、緩和効果が高く、クラ
ックや反り等が低減し、結晶欠陥を減少させる。基板表
面がサファイア基板若しくは窒化物半導体であり、ボイ
ドを有する中間層の歪み吸収効果、歪み緩和効果が大き
いので、面倒な表面炭化処理や複数の層の膜厚バランス
を精密に制御する必要もなく、高品質で大口径の窒化物
半導体エピタキシャルウェハが得られる。
According to the present invention, an intermediate layer obtained by implanting ions such as hydrogen, nitrogen, and oxygen into a separation nitride semiconductor layer formed near the surface of a sapphire substrate different from a nitride semiconductor or on a sapphire substrate. Has an amorphous structure, so that it absorbs and relaxes distortion and reduces cracks and warpage. The intermediate layer implanted with hydrogen is heated during the growth of the nitride semiconductor layer, so that voids are generated. Voids have high strain absorption and relaxation effects, reduce cracks and warpage, and reduce crystal defects. Since the substrate surface is a sapphire substrate or a nitride semiconductor, and the interlayer having voids has a large strain absorption effect and a large strain relaxation effect, there is no need for complicated surface carbonization treatment or precise control of the film thickness balance of multiple layers. Thus, a high-quality, large-diameter nitride semiconductor epitaxial wafer can be obtained.

【0028】[0028]

【発明の実施の形態】以下、本発明の実施の形態につい
て説明する。
Embodiments of the present invention will be described below.

【0029】本発明の窒化物半導体エピタキシャルウェ
ハの製造方法は、サファイア基板の表面近傍にサファイ
ア基板より機械的強度の弱い中間層を形成し、この中間
層を形成したサファイア基板の上にデバイス用窒化物半
導体層をエピタキシャル成長させるものである。成長す
る層構造は1層以上のエピタキシャル構造であり、P/
N接合、ヘテロ接合等の半導体構造を有してもよい。発
光ダイオード、レーザ、受光素子、電界効果トランジス
タ、HEMT、HBT等種々の半導体素子に適した層構
造、あるいはその一部を構成するエピタキシャル層構造
となる。
According to the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention, an intermediate layer having a lower mechanical strength than a sapphire substrate is formed near the surface of a sapphire substrate, and a device nitride is formed on the sapphire substrate on which the intermediate layer is formed. The target semiconductor layer is grown epitaxially. The layer structure to be grown is an epitaxial structure of one or more layers.
It may have a semiconductor structure such as an N junction or a hetero junction. A layer structure suitable for various semiconductor elements such as a light emitting diode, a laser, a light receiving element, a field effect transistor, HEMT, and HBT, or an epitaxial layer structure constituting a part thereof.

【0030】中間層は、サファイア基板の表面近傍に水
素や窒素、酸素等のイオンを打ち込むことにより機械的
強度をサファイア基板よりも小さくした層である。イオ
ン打ち込み後のサファイア基板に熱処理を加えることに
より中間層に多数の微細なボイドを生じさせることがで
き、中間層の機械的強度をさらに小さくすることができ
る。
The intermediate layer is a layer whose mechanical strength is made smaller than that of the sapphire substrate by implanting ions such as hydrogen, nitrogen and oxygen into the vicinity of the surface of the sapphire substrate. By applying heat treatment to the sapphire substrate after the ion implantation, a large number of fine voids can be generated in the intermediate layer, and the mechanical strength of the intermediate layer can be further reduced.

【0031】この中間層がデバイス用窒化物半導体結晶
とサファイア基板との熱膨張差を緩和するバッファ層と
して機能するため、従来問題となっていたクラックや反
りが解消し、高品質な窒化物半導体エピタキシャルウェ
ハが得られる。さらにこの中間層を境にしてサファイア
基板までの部分は容易に剥離、除去することができる。
Since the intermediate layer functions as a buffer layer for alleviating the difference in thermal expansion between the nitride semiconductor crystal for a device and the sapphire substrate, cracks and warpage, which have conventionally been problems, are eliminated, and a high-quality nitride semiconductor is obtained. An epitaxial wafer is obtained. Further, the portion from the intermediate layer to the sapphire substrate can be easily peeled and removed.

【0032】剥離の方法は、デバイス用窒化物半導体層
の結晶膜成長過程での加熱による自然剥離、あるいはそ
の後の熱処理による剥離、側面からの窒素ジェットによ
る剥離、ウォータジェットによる剥離、レーザ照射によ
る剥離等種々の方法が使用できる。
The method of peeling includes natural peeling by heating during the process of growing the crystal film of the nitride semiconductor layer for a device, or peeling by subsequent heat treatment, peeling by a nitrogen jet from the side, peeling by a water jet, and peeling by laser irradiation. Various methods can be used.

【0033】剥離後にデバイス用窒化物半導体層の裏面
にわずかに残ったサファイア基板の一部を研磨等によっ
て除去することにより、大口径でフラットな自立窒化物
半導体エピタキシャルウェハを容易に得ることができ
る。
By removing a part of the sapphire substrate slightly remaining on the back surface of the nitride semiconductor layer for device after peeling by polishing or the like, a large-diameter flat flat freestanding nitride semiconductor epitaxial wafer can be easily obtained. .

【0034】また、本発明の窒化物半導体エピタキシャ
ルウェハの製造方法は、上記製造方法の他に、サファイ
ア基板の上に剥離用窒化物半導体層を形成し、剥離用窒
化物半導体層の表面近傍に機械的強度が剥離用窒化物半
導体層より弱い中間層を形成し、この中間層を形成した
剥離用窒化物半導体層の上にデバイス用窒化物半導体層
をエピタキシャル成長させてもよい。
[0034] In addition to the above-described manufacturing method, the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention further comprises forming a peeling nitride semiconductor layer on a sapphire substrate, and forming a nitride semiconductor layer near the surface of the peeling nitride semiconductor layer. An intermediate layer whose mechanical strength is weaker than that of the peeling nitride semiconductor layer may be formed, and the device nitride semiconductor layer may be epitaxially grown on the peeling nitride semiconductor layer on which the intermediate layer has been formed.

【0035】デバイス用窒化物半導体層の膜厚は10μ
m以下が好ましい。これはサファイア基板の反りを防ぐ
ためであり、これ以上の厚さになると、窒化物半導体と
サファイアとの熱膨張差によって基板が反ってしまうた
めである。
The thickness of the nitride semiconductor layer for the device is 10 μm.
m or less is preferable. This is to prevent the sapphire substrate from warping, and if the sapphire substrate has a greater thickness, the substrate is warped due to a difference in thermal expansion between the nitride semiconductor and the sapphire.

【0036】イオン打ち込みの加速電圧は1keV以上
1MeV以下が好ましい。これは、中間層の形成深さを
適切にし、サファイア基板表面の結晶状態を良好に保つ
ためである。1keV以下では中間層の形成される位置
が浅すぎて、サファイア基板表面の結晶性に悪影響を与
える。これとは逆に1MeV以上では打ち込んだイオン
が基板表面の結晶に与えるダメージが無視できなくな
る。また、中間層の形成される位置が深くなりすぎて中
間層による歪み緩衝効果が小さくなったり、サファイア
基板剥離後にデバイス用窒化物半導体結晶の裏面に残る
サファイア等が厚くなり、除去するための研磨に時間が
かかってしまうためである。
The acceleration voltage for ion implantation is preferably 1 keV or more and 1 MeV or less. This is to make the formation depth of the intermediate layer appropriate and keep the crystal state of the sapphire substrate surface favorable. If it is 1 keV or less, the position where the intermediate layer is formed is too shallow, which adversely affects the crystallinity of the sapphire substrate surface. Conversely, at 1 MeV or more, the damage caused by the implanted ions to the crystal on the substrate surface cannot be ignored. In addition, the position at which the intermediate layer is formed is too deep, and the strain buffering effect of the intermediate layer is reduced, or sapphire or the like remaining on the back surface of the nitride semiconductor crystal for device after the sapphire substrate is peeled becomes thicker, and polishing for removal is performed. This is because it takes time.

【0037】ドーズ量は1×1015cm-2以上1×10
19cm-2以下とするのが好ましい。これは、サファイア
基板表面の結晶のダメージを無視できる範囲に抑えつつ
反りを緩和し、歪み緩衝と基板の剥離に十分なほどのボ
イドを発生させるためである。ドーズ量が1×1015
-2以下の場合にはボイドの発生密度が小さいため歪み
緩衝効果が小さくなり、基板を剥離するのに不十分であ
る。これとは逆にドーズ量が1×1019cm-2以上にな
ると打ち込んだイオンがサファイア基板の表面の結晶に
与えるダメージが無視できなくなってしまうためであ
る。
The dose amount is 1 × 10 15 cm −2 or more and 1 × 10 5
It is preferably 19 cm- 2 or less. This is for suppressing the damage of the crystal on the surface of the sapphire substrate to a negligible range, relaxing the warp, and generating voids sufficient for buffering the strain and peeling the substrate. Dose amount is 1 × 10 15 c
In the case of m −2 or less, the density of voids is low, so that the strain buffering effect is small, and it is insufficient to peel the substrate. Conversely, if the dose is 1 × 10 19 cm −2 or more, the damage caused by the implanted ions to the crystal on the surface of the sapphire substrate cannot be ignored.

【0038】[0038]

【実施例】(実施例1)図1(a)〜(e)は本発明の
窒化物半導体基板の製造方法の一実例を示す工程図であ
る。
(Embodiment 1) FIGS. 1A to 1E are process diagrams showing one embodiment of a method for manufacturing a nitride semiconductor substrate according to the present invention.

【0039】基板として、サファイア基板(直径約50
mm、厚さ約0.33mm)を準備する(図1
(a))。
As a substrate, a sapphire substrate (having a diameter of about 50
mm and a thickness of about 0.33 mm) (FIG. 1).
(A)).

【0040】サファイア基板1に水素のイオン打ち込み
を行う。その条件はドーズ量を1×1017cm-2とし、
加速電圧を100keVとして、サファイア基板1の表
面から0.5μmの深さに厚さ0.1μmの中間層2を
形成する。水素を打ち込んだサファイア基板1の表面近
傍1aには単結晶層が維持されており、その単結晶層1
aの下に水素の打ち込み層、すなわち中間層2が存在す
る(図1(b))。
Hydrogen ions are implanted into the sapphire substrate 1. The condition is that the dose is 1 × 10 17 cm -2 ,
At an acceleration voltage of 100 keV, an intermediate layer 2 having a thickness of 0.1 μm is formed at a depth of 0.5 μm from the surface of the sapphire substrate 1. A single crystal layer is maintained in the vicinity 1a of the surface of the sapphire substrate 1 into which hydrogen has been implanted.
There is an implanted layer of hydrogen, that is, an intermediate layer 2 underneath (a) (FIG. 1 (b)).

【0041】サファイア基板1aの表面に有機金属気相
成長法(MOVPE法)を用いてデバイス用窒化物半導
体層3となるGaN単結晶を2μmエピタキシャル成長
させた。成長炉は、横型常圧MOVPE炉を用い、原料
としてアンモニアガスとトリメチルガリウムを用い、キ
ャリアガスとして水素と窒素との混合ガスを用いた。
On the surface of the sapphire substrate 1a, a 2 μm GaN single crystal serving as the device nitride semiconductor layer 3 was epitaxially grown by metal organic chemical vapor deposition (MOVPE). As a growth furnace, a horizontal atmospheric pressure MOVPE furnace was used, and ammonia gas and trimethylgallium were used as raw materials, and a mixed gas of hydrogen and nitrogen was used as a carrier gas.

【0042】まず、基板を水素雰囲気で1100℃に加
熱し、表面の酸化物等をクリーニングする。続いて基板
温度を550℃に下げてGaNを20nm成長させ、さ
らに基板温度を1050℃に上げて、GaNを2μm成
長させる。
First, the substrate is heated to 1100 ° C. in a hydrogen atmosphere to clean oxides and the like on the surface. Subsequently, the substrate temperature is lowered to 550 ° C., and GaN is grown to 20 nm, and further, the substrate temperature is raised to 1050 ° C., and GaN is grown to 2 μm.

【0043】MOVPE炉から取り出したGaNエピタ
キシャル成長基板のうちの1枚を割ってその断面を走査
型電子顕微鏡で観察したところ、中間層に微細なボイド
が多数発生している様子が観測された。
When one of the GaN epitaxial growth substrates taken out of the MOVPE furnace was split and its cross section was observed with a scanning electron microscope, it was observed that many fine voids were generated in the intermediate layer.

【0044】作製したGaNエピタキシャル成長基板4
上に、HVPE法を用いてGaN単結晶を300μmエ
ピタキシャル成長させる。装置は横型常圧HVPE炉を
用いる。原料としてアンモニアガス及び金属Gaと、H
Clガスとを850℃で反応させたGaClを用い、キ
ャリアガスとして水素ガスを用いる。成長温度を105
0℃とし、成長速度を80μm/hとする(図1
(c))。
The manufactured GaN epitaxial growth substrate 4
A GaN single crystal is epitaxially grown to a thickness of 300 μm using the HVPE method. The apparatus uses a horizontal normal pressure HVPE furnace. Ammonia gas and metal Ga as raw materials and H
GaCl obtained by reacting Cl gas at 850 ° C. is used, and hydrogen gas is used as a carrier gas. Growth temperature 105
0 ° C. and the growth rate was 80 μm / h (FIG. 1).
(C)).

【0045】エピタキシャル成長終了後、成長温度から
室温までの冷却過程において中間層(ボイド層)2を境
に中間層2からサファイア基板1bまでの部分が自然に
剥離する(図1(d))。
After the completion of the epitaxial growth, the part from the intermediate layer 2 to the sapphire substrate 1b is naturally separated from the intermediate layer (void layer) 2 in the cooling process from the growth temperature to room temperature (FIG. 1D).

【0046】得られたGaN単結晶からなるデバイス用
窒化物半導体層3の裏面に残った薄いサファイア層1a
を研磨して除去することにより、直径約50mm、厚さ
約300μmのGaN自立単結晶基板が得られた。この
基板は無色透明であり、クラックや反りが全くなかった
(図1(e))。 (実施例2)図2(a)〜(f)は本発明の窒化物半導
体エピタキシャルウェハの製造方法の他の実施例を示す
工程図である。
The thin sapphire layer 1a remaining on the back surface of the obtained nitride semiconductor layer for device 3 made of GaN single crystal
Was removed by polishing to obtain a GaN free-standing single crystal substrate having a diameter of about 50 mm and a thickness of about 300 μm. This substrate was colorless and transparent, and had no cracks or warpage (FIG. 1 (e)). (Embodiment 2) FIGS. 2A to 2F are process diagrams showing another embodiment of the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention.

【0047】基板として、サファイア基板(直径約50
mm、厚さ約0.33mm)10に有機金属気相成長法
(MOVPE法)を用いて剥離用窒化物半導体層11と
なるGaN単結晶を2μmエピタキシャル成長させる。
成長炉には横型常圧MOVPE炉を用い、原料としてア
ンモニアガスとトリメチルガリウムを用い、キャリアガ
スとして水素と窒素との混合ガスを用いる。
As a substrate, a sapphire substrate (having a diameter of about 50
A GaN single crystal serving as the peeling nitride semiconductor layer 11 is epitaxially grown to a thickness of 2 μm using a metal organic chemical vapor deposition method (MOVPE method) to a thickness of about 0.33 mm.
A horizontal atmospheric pressure MOVPE furnace is used as a growth furnace, and ammonia gas and trimethylgallium are used as raw materials, and a mixed gas of hydrogen and nitrogen is used as a carrier gas.

【0048】サファイア基板10を水素雰囲気中で11
00℃に加熱し、表面の酸化物等をクリーニングした。
続いて基板温度を550℃に下げてGaNを20nm成
長させ、さらに基板温度を1050℃に上げて、GaN
を約2μm成長させる(図2(a))。
The sapphire substrate 10 is placed in a hydrogen atmosphere at 11
It was heated to 00 ° C. to clean oxides and the like on the surface.
Subsequently, the temperature of the substrate was lowered to 550 ° C., and GaN was grown to a thickness of 20 nm.
Is grown to about 2 μm (FIG. 2A).

【0049】成長したGaN単結晶層からなる剥離用窒
化物半導体層11に水素をイオン打ち込みする。その条
件はドーズ量を1×1017cm-2とし、加速電圧を10
0keVとし、剥離用窒化物半導体層11の表面から約
0.5μmの深さに厚さ約0.1μm程度の中間層12
を形成する。水素が打ち込まれた剥離用窒化物半導体層
11の表面には単結晶層が維持されており、その剥離用
窒化物半導体層11の表面の下には水素の打ち込み層
(中間層)12が存在する(図2(b))。
Hydrogen is ion-implanted into the nitride semiconductor layer 11 for separation made of the grown GaN single crystal layer. The conditions are a dose of 1 × 10 17 cm −2 and an accelerating voltage of 10
0 keV, an intermediate layer 12 having a thickness of about 0.1 μm and a depth of about 0.5 μm from the surface of the nitride semiconductor layer 11 for separation.
To form A single crystal layer is maintained on the surface of the nitride semiconductor layer 11 for separation into which hydrogen has been implanted, and a hydrogen implantation layer (intermediate layer) 12 exists below the surface of the nitride semiconductor layer 11 for separation. (FIG. 2B).

【0050】水素を打ち込んだGaNエピタキシャル成
長基板13をアンモニア雰囲気中、800℃で30分間
熱処理する。熱処理が終了したGaNエピタキシャル成
長基板13と同様の試料の断面を走査型電子顕微鏡で観
察したところ、中間層は微細なボイドの多数発生したボ
イド層になった(図2(c))。
The hydrogen-implanted GaN epitaxial growth substrate 13 is heat-treated at 800 ° C. for 30 minutes in an ammonia atmosphere. When a cross section of the same sample as the GaN epitaxial growth substrate 13 after the heat treatment was observed with a scanning electron microscope, the intermediate layer was a void layer in which many fine voids were generated (FIG. 2C).

【0051】熱処理の済んだGaNエピタキシャル成長
基板13a上に、HVPE法を用いてデバイス用窒化物
半導体層14となるGaN単結晶を約300μmエピタ
キシャル成長させる。装置は横型常圧HVPE炉を用い
た。原料としてアンモニアガス及び金属GaとHClガ
スを850℃で反応させたGaClを用い、n型の導電
型を得るためにSiH2 Cl2 を同時に流す。キャリア
ガスには水素ガスを用いる。成長温度を1050℃とし
たところ、成長速度は80μm/hであった(図2
(d))。
On the heat-treated GaN epitaxial growth substrate 13a, a GaN single crystal serving as the device nitride semiconductor layer 14 is epitaxially grown to about 300 μm by HVPE. The apparatus used was a horizontal normal pressure HVPE furnace. As a raw material, GaCl obtained by reacting ammonia gas and metal Ga with HCl gas at 850 ° C. is used, and SiH 2 Cl 2 is simultaneously flowed to obtain an n-type conductivity type. Hydrogen gas is used as a carrier gas. When the growth temperature was set to 1050 ° C., the growth rate was 80 μm / h (FIG. 2).
(D)).

【0052】エピタキシャル成長終了後、成長温度から
室温までの冷却過程においてボイドからなる中間層12
を境に中間層12からサファイア基板10までの部分が
自然に剥離する(図2(e))。
After the completion of the epitaxial growth, the intermediate layer 12 consisting of voids is formed in a cooling process from the growth temperature to room temperature.
After that, the part from the intermediate layer 12 to the sapphire substrate 10 is spontaneously separated (FIG. 2E).

【0053】得られたn型GaN単結晶からなるデバイ
ス用窒化物半導体層14の裏面に残った剥離用窒化物半
導体層11aを研磨して除去することにより、直径約5
0mm、厚さ約300μmのn型GaN自立単結晶基板
が得られた。この基板は無色透明のものであり、クラッ
クや反りが全くなかった(図2(f))。 (実施例3)図3は本発明の窒化物半導体エピタキシャ
ルウェハを用いたレーザダイオードの構造模式図であ
る。
The removal nitride semiconductor layer 11a remaining on the back surface of the obtained device nitride semiconductor layer 14 made of n-type GaN single crystal is polished and removed to obtain a diameter of about 5 mm.
An n-type GaN free-standing single crystal substrate having a thickness of 0 mm and a thickness of about 300 μm was obtained. This substrate was colorless and transparent, and had no cracks or warpage (FIG. 2 (f)). (Embodiment 3) FIG. 3 is a schematic structural view of a laser diode using a nitride semiconductor epitaxial wafer of the present invention.

【0054】実施例2で得られたn型GaN自立単結晶
基板上にMOVPE法によって図3に示すような構造の
LD素子を形成する場合について説明する。
A case in which an LD element having a structure as shown in FIG. 3 is formed on the n-type GaN free-standing single crystal substrate obtained in Example 2 by MOVPE will be described.

【0055】このLD構造は、n型GaN自立単結晶基
板21側から順にSiドープGaNバッファ層(厚さ約
2μm、n=5×1017cm-3)22、SiドープAl
0.07Ga0.93Nクラッド層(厚さ約1.0μm、n=5
×1017cm-3)23、SiドープGaN SCH層
(厚さ約0.1μm、n=1×1017cm-3)24、ア
ンドープIn0.2 Ga0.8 N/In0.05Ga0.95N多重
量子井戸層(3nm/5nm×3)25、MgドープA
0.2 Ga0.8 Nオーバーフロー防止層(厚さ約20n
m、p=2×1019cm-3)26、MgドープGaN光
閉込層(厚さ約0.1μm、p=2×1019cm-3)2
7、MgドープAl0.07Ga0.93Nクラッド層(厚さ約
0.5μm、p=2×1019cm-3)28、Mgドープ
GaNコンタクト層(厚さ約50nm、p=2×1019
cm-3)29を形成したものである。
The LD structure is composed of a Si-doped GaN buffer layer (about 2 μm, n = 5 × 10 17 cm −3 ) 22 and a Si-doped Al
0.07 Ga 0.93 N cladding layer (about 1.0 μm thick, n = 5
× 10 17 cm −3 ) 23, Si-doped GaN SCH layer (thickness: about 0.1 μm, n = 1 × 10 17 cm −3 ) 24, undoped In 0.2 Ga 0.8 N / In 0.05 Ga 0.95 N multiple quantum well layer (3 nm / 5 nm × 3) 25, Mg-doped A
l 0.2 Ga 0.8 N overflow prevention layer (thickness: about 20 n
m, p = 2 × 10 19 cm −3 ) 26, Mg-doped GaN light confinement layer (thickness: about 0.1 μm, p = 2 × 10 19 cm −3 ) 2
7, Mg-doped Al 0.07 Ga 0.93 N cladding layer (thickness: about 0.5 μm, p = 2 × 10 19 cm −3 ) 28; Mg-doped GaN contact layer (thickness: about 50 nm, p = 2 × 10 19)
cm −3 ) 29.

【0056】p側にドライエッチングにより幅約4μ
m、深さ約0.4μmのリッジ構造を作製し、電流狭窄
を行った。リッジの上部にNi/Au電極30を形成
し、p型オーミック電極とした。裏面の自立GaN基板
側にはTi/Al電極20を全面に形成し、n型オーミ
ック電極とした。両端面にTiO2 /SiO2 からなる
高反射コーティング膜を形成した。素子の長さは約50
0μmとすることによりLD素子が得られた。
The width of the p-side is about 4 μm by dry etching.
A ridge structure having a depth of about 0.4 μm and a depth of about 0.4 μm was manufactured, and current constriction was performed. A Ni / Au electrode 30 was formed on the ridge to form a p-type ohmic electrode. A Ti / Al electrode 20 was formed on the entire surface of the backside of the self-standing GaN substrate to form an n-type ohmic electrode. A high reflection coating film made of TiO 2 / SiO 2 was formed on both end surfaces. Element length is about 50
By setting the thickness to 0 μm, an LD element was obtained.

【0057】このようなLD素子に通電すると、閾値電
流密度が約4.5kA/cm2 で、閾値電圧が約5.5
Vで、室温で連続発振した。また結晶欠陥が低減されて
いるため、LD素子の寿命は気温25℃で、30mW駆
動時において5000時間と良好な特性を有していた。
When power is supplied to such an LD element, the threshold current density is about 4.5 kA / cm 2 and the threshold voltage is about 5.5.
And continuous oscillation at room temperature. Further, since the crystal defects were reduced, the life of the LD element was excellent at 5,000 hours when driven at 30 mW at an air temperature of 25 ° C.

【0058】さらに本発明による自立基板は、反りが無
いうえにサファイア基板上にLD構造を形成した場合に
比べて劈開が容易なため、プロセス時の歩留まりが大幅
に改善され、90%以上の素子で良好な特性が得られ
た。 (実施例4)次に本発明の窒化物半導体エピタキシャル
ウェハを用いた発光ダイオードについて説明する。図4
は本発明の窒化物半導体エピタキシャルウェハを用いた
発光ダイオードの構造模式図である。この発光ダイオー
ドは、実施例2における図2(a)から図2(c)まで
の工程で選ばれたGaNエピタキシャル成長基板上にL
ED構造を形成し、そのLED構造の上にNi/Au層
を真空蒸着し、そのNi/Au層の上にAl基板を電気
炉中の窒素雰囲気下で660℃で融着しその後にサファ
イア基板を中間層から剥離、除去し、その剥離、除去し
たサファイア基板のあった面にTi/Al電極を形成す
ることによって製造した。
Further, the self-standing substrate according to the present invention has no warpage and is easy to cleave as compared with the case where an LD structure is formed on a sapphire substrate. And good characteristics were obtained. Embodiment 4 Next, a light emitting diode using the nitride semiconductor epitaxial wafer of the present invention will be described. FIG.
FIG. 1 is a schematic structural view of a light emitting diode using a nitride semiconductor epitaxial wafer of the present invention. This light emitting diode is formed on the GaN epitaxial growth substrate selected in the steps from FIG. 2A to FIG.
An ED structure is formed, a Ni / Au layer is vacuum-deposited on the LED structure, an Al substrate is fused on the Ni / Au layer at 660 ° C. in a nitrogen atmosphere in an electric furnace, and then a sapphire substrate Was removed from the intermediate layer, and a Ti / Al electrode was formed on the surface where the sapphire substrate had been removed and removed.

【0059】こうして得られた発光ダイオードの構造
は、Al基板40側から順に、Ni/Au層41、Mg
ドープGaN層(厚さ50nm、p=2×1019
-3)42、MgドープAl0.2 Ga0.8 N層(厚さ
0.5μm、p=2×1019cm-3)43、アンドープ
量子井戸層(In0.2Ga0.8N)44、SiドープGa
Nクラッド層(厚さ3μm、n=5×1017cm-3)4
5及びn型電極(Ti/Al電極)46である。
The structure of the light emitting diode thus obtained is such that the Ni / Au layer 41 and the Mg
Doped GaN layer (50 nm thick, p = 2 × 10 19 c
m −3 ) 42, Mg-doped Al 0.2 Ga 0.8 N layer (thickness 0.5 μm, p = 2 × 10 19 cm −3 ) 43, undoped quantum well layer (In 0.2 Ga 0.8 N) 44, Si-doped Ga
N cladding layer (thickness 3 μm, n = 5 × 10 17 cm −3 ) 4
5 and an n-type electrode (Ti / Al electrode) 46.

【0060】このLED素子に通電したところ、発光波
長は450nmで、発光出力は20mA通電時で約7m
Wであった。中間層を形成しないサファイア基板上に成
長した発光ダイオードと違って結晶欠陥が少なく、放熱
特性も良いために素子の信頼性も高く、樹脂モールドし
た状態で40℃、湿度100%とした環境下で、20m
Aで1000時間の連続通電試験を行ったところ、10
00時間通電後においても発光出力は初期状態とほぼ変
わらなかった。
When the LED element was energized, the emission wavelength was 450 nm, and the emission output was about 7 m when 20 mA was applied.
W. Unlike a light-emitting diode grown on a sapphire substrate without an intermediate layer, it has few crystal defects and good heat dissipation characteristics, so the reliability of the element is high. In an environment of 40 ° C. and 100% humidity in a resin molded state , 20m
When a continuous energization test was performed for 1000 hours at A,
Even after the current supply for 00 hours, the light emission output was almost the same as the initial state.

【0061】上述した実施例では、基板としてサファイ
ア基板若しくは表面に窒化物半導体を形成したサファイ
ア基板を用い、打ち込むイオンとして水素を用いた場合
について説明したが、サファイア基板以外の基板や水素
イオン以外のイオンを用いてもよい。
In the above-described embodiment, a case was described in which a sapphire substrate or a sapphire substrate having a nitride semiconductor formed on the surface was used as the substrate and hydrogen was used as the ion to be implanted. Ions may be used.

【0062】窒化物半導体のエピタキシャル成長法とし
ては、MOVPE法、HVPE法、MBE法等とすでに
公知の様々な方法があり、利用することができる。ま
た、窒化ガリウムや窒化アルミニウム等の低温バッファ
層を用いる2段階成長方法、直接高温で成長する方法、
成長の途中で微細加工と再成長を用いてラテラル成長に
よる転位低減を図るELO法、FIELO法等公知の種
々の方法を用いることができる。
As the epitaxial growth method of the nitride semiconductor, there are various known methods such as the MOVPE method, the HVPE method and the MBE method, which can be used. A two-step growth method using a low-temperature buffer layer of gallium nitride or aluminum nitride, a method of directly growing at a high temperature,
Various known methods such as an ELO method and a FIELO method for reducing dislocations by lateral growth using microfabrication and regrowth during growth can be used.

【0063】中間層をボイド層とするのは他の窒化物半
導体層の成長前の昇温中、冷却中、成長後のいずれか、
あるいは全ての過程あるいは幾つかの複数の過程で行う
ことができる。またはイオン打ち込み後、他の窒化物半
導体層の成長開始前に熱処理を行ってもよい。
The intermediate layer may be formed as a void layer either during the temperature increase before the growth of the other nitride semiconductor layer, during the cooling, or after the growth,
Alternatively, it can be performed in all or some of the steps. Alternatively, heat treatment may be performed after ion implantation and before the start of growth of another nitride semiconductor layer.

【0064】中間層を境にサファイア基板を剥離する方
法は、成長後の熱処理による剥離、側面からの窒素ジェ
ットによる剥離、ウォータジェットによる剥離、レーザ
照射による剥離等の種々の方法でも実施できる。
The sapphire substrate can be peeled off from the intermediate layer by various methods such as peeling by heat treatment after growth, peeling by a nitrogen jet from a side surface, peeling by a water jet, and peeling by laser irradiation.

【0065】また、実施例4ではAl基板を貼り付けた
上で剥離を行ったが、その他、例えばSi基板、ガラス
基板、Cu等金属基板、AlN等の熱伝導性の良い薄膜
を積層した金属基板等、その後の素子作製プロセスに適
した基板を用いることができる。
In the fourth embodiment, peeling was performed after attaching an Al substrate. However, for example, a metal substrate such as a Si substrate, a glass substrate, a metal substrate such as Cu, or a thin film having good thermal conductivity such as AlN was laminated. A substrate such as a substrate suitable for a subsequent element manufacturing process can be used.

【0066】ここで、従来、窒化物半導体のエピタキシ
ャル成長は、熱膨張係数が大きく異なるサファイア等の
基板上で行われていたので、結晶欠陥が多かったり、厚
膜を成長すると反りやクラックが発生するという問題が
あった。この問題を根本的に解決するために窒化物半導
体基板の開発も行われてきたが、窒化物半導体基板の作
製は超高圧下で行われていたのでコストが非常に高く、
10mm程度のものしか得られなかった。また、HVP
E法で数百μm程度のGaN厚膜をサファイア基板上に
成長させた後でサファイア基板を取り除くことによって
GaNの自立基板を得る方法より現実的であるが、サフ
ァイア基板と窒化物半導体との熱膨張率の差に起因する
反りやクラックが発生するうえ結晶欠陥がかなり多い、
サファイア基板の実用的な除去方法が無い、除去後も反
りが残る等の問題があった。
Here, conventionally, epitaxial growth of a nitride semiconductor has been performed on a substrate such as sapphire having a significantly different coefficient of thermal expansion, so that many crystal defects occur, and when a thick film is grown, warpage and cracks occur. There was a problem. In order to fundamentally solve this problem, the development of nitride semiconductor substrates has also been carried out, but since the production of nitride semiconductor substrates was performed under ultra-high pressure, the cost was extremely high,
Only about 10 mm was obtained. Also, HVP
It is more realistic than a method of obtaining a GaN free-standing substrate by growing a GaN thick film of about several hundred μm on a sapphire substrate by the E method and then removing the sapphire substrate, but the heat between the sapphire substrate and the nitride semiconductor is more realistic. Warpage and cracks due to the difference in expansion coefficient occur, and crystal defects are quite large.
There are no practical methods for removing the sapphire substrate, and there are problems such as warpage remaining after the removal.

【0067】しかしながら、本発明によれば、水素打ち
込み及び熱処理によって基板中に形成された中間層が熱
膨張率の差を緩和するバッファ層として機能するので、
従来問題となっていた結晶欠陥が著しく減少し、反りや
クラックが解消された高品質な窒化物半導体エピタキシ
ャルウェハを容易に得ることができる。また、窒化物半
導体層を、この中間層を境にして基板から剥離して窒化
物半導体の大面積でフラットな自立エピタキシャルウェ
ハを容易に得ることができる。
However, according to the present invention, the intermediate layer formed in the substrate by hydrogen implantation and heat treatment functions as a buffer layer for reducing the difference in thermal expansion coefficient.
It is possible to easily obtain a high-quality nitride semiconductor epitaxial wafer in which crystal defects, which have conventionally been a problem, are significantly reduced and warpage and cracks are eliminated. In addition, the nitride semiconductor layer is separated from the substrate with the intermediate layer as a boundary, so that a large-area flat freestanding epitaxial wafer of the nitride semiconductor can be easily obtained.

【0068】[0068]

【発明の効果】以上、要するに本発明によれば、次のよ
うな優れた効果を発揮する。
In summary, according to the present invention, the following excellent effects can be obtained.

【0069】結晶欠陥が少なく、反りやクラックのない
窒化物半導体エピタキシャルウェハの製造方法及び窒化
物半導体エピタキシャルウェハの提供を実現することが
できる。
A method for manufacturing a nitride semiconductor epitaxial wafer having few crystal defects and free from warpage and cracks and the provision of a nitride semiconductor epitaxial wafer can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(e)は本発明の窒化物半導体エピタ
キシャルウェハの製造方法の一実例を示す工程図であ
る。
FIGS. 1A to 1E are process diagrams showing an example of a method for manufacturing a nitride semiconductor epitaxial wafer according to the present invention.

【図2】(a)〜(f)は本発明の窒化物半導体エピタ
キシャルウェハの製造方法の他の実施例を示す工程図で
ある。
2 (a) to 2 (f) are process diagrams showing another embodiment of the method for manufacturing a nitride semiconductor epitaxial wafer of the present invention.

【図3】本発明の窒化物半導体エピタキシャルウェハを
用いたレーザダイオードの構造模式図である。
FIG. 3 is a schematic structural view of a laser diode using the nitride semiconductor epitaxial wafer of the present invention.

【図4】本発明の窒化物半導体エピタキシャルウェハを
用いた発光ダイオードの構造模式図である。
FIG. 4 is a schematic structural view of a light emitting diode using the nitride semiconductor epitaxial wafer of the present invention.

【符号の説明】[Explanation of symbols]

1、1a、1b サファイア基板 2 中間層 3 デバイス用窒化物半導体層 1, 1a, 1b Sapphire substrate 2 Intermediate layer 3 Device nitride semiconductor layer

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 4K030 AA03 AA11 AA13 AA17 AA18 BA02 BA08 BA11 BA38 CA01 DA03 DA08 FA10 JA01 JA06 LA11 5F041 AA40 CA05 CA34 CA40 CA46 CA57 CA65 CA67 CA71 CA73 CA82 CA92 5F045 AA04 AB14 AB18 AC08 AC12 AC13 AD09 AD14 AF03 AF09 BB12 BB16 CA10 CA12 DA53 HA05 5F073 AA45 AA74 CA07 CB05 CB07 DA05 DA14 DA35  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4K030 AA03 AA11 AA13 AA17 AA18 BA02 BA08 BA11 BA38 CA01 DA03 DA08 FA10 JA01 JA06 LA11 5F041 AA40 CA05 CA34 CA40 CA46 CA57 CA65 CA67 CA71 CA73 CA82 CA92 5F045 AA04 AB14 AB18 AC08 AC12 AD14 AF03 AF09 BB12 BB16 CA10 CA12 DA53 HA05 5F073 AA45 AA74 CA07 CB05 CB07 DA05 DA14 DA35

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】 サファイア基板の表面近傍に該サファイ
ア基板より機械的強度の弱い中間層を形成し、該中間層
を形成したサファイア基板の上にデバイス用窒化物半導
体層をエピタキシャル成長させることを特徴とする窒化
物半導体エピタキシャルウェハの製造方法。
An intermediate layer having a lower mechanical strength than the sapphire substrate is formed near the surface of the sapphire substrate, and a nitride semiconductor layer for a device is epitaxially grown on the sapphire substrate on which the intermediate layer is formed. Of manufacturing a nitride semiconductor epitaxial wafer.
【請求項2】 サファイア基板の上に剥離用窒化物半導
体層を形成し、該剥離用窒化物半導体層の表面近傍に機
械的強度が該剥離用窒化物半導体層より弱い中間層を形
成し、該中間層を形成した剥離用窒化物半導体層の上に
デバイス用窒化物半導体層をエピタキシャル成長させる
ことを特徴とする窒化物半導体エピタキシャルウェハの
製造方法。
2. A nitride semiconductor layer for separation is formed on a sapphire substrate, and an intermediate layer whose mechanical strength is weaker than that of the nitride semiconductor layer for separation is formed near a surface of the nitride semiconductor layer for separation. A method for manufacturing a nitride semiconductor epitaxial wafer, comprising epitaxially growing a device nitride semiconductor layer on the peeling nitride semiconductor layer on which the intermediate layer is formed.
【請求項3】 上記デバイス用窒化物半導体層の厚さを
10μm以下とする請求項1又は2に記載の窒化物半導
体エピタキシャルウェハの製造方法。
3. The method for manufacturing a nitride semiconductor epitaxial wafer according to claim 1, wherein the thickness of the device nitride semiconductor layer is 10 μm or less.
【請求項4】 上記剥離用窒化物半導体層若しくは上記
サファイア基板の表面から上記中間層を形成すべき深さ
にイオンを打ち込むことによって上記中間層を形成する
請求項1から3のいずれかに記載の窒化物半導体エピタ
キシャルウェハの製造方法。
4. The intermediate layer according to claim 1, wherein ions are implanted from a surface of the nitride semiconductor layer for separation or a surface of the sapphire substrate to a depth at which the intermediate layer is to be formed. Of manufacturing a nitride semiconductor epitaxial wafer.
【請求項5】 上記イオンとして水素イオン、窒素イオ
ン及び酸素イオンのうち少なくとも1種類を用いる請求
項4に記載の窒化物半導体エピタキシャルウェハの製造
方法。
5. The method for manufacturing a nitride semiconductor epitaxial wafer according to claim 4, wherein at least one of hydrogen ions, nitrogen ions, and oxygen ions is used as said ions.
【請求項6】 上記イオンの打ち込みの加速電圧を1k
eV以上1MeV以下とし、かつ、上記イオンのドーズ
量を1×1015cm-2以上1×1019cm-2以下とする
請求項5に記載の窒化物半導体エピタキシャルウェハの
製造方法。
6. An accelerating voltage for ion implantation is 1 k
6. The method for producing a nitride semiconductor epitaxial wafer according to claim 5, wherein the nitride semiconductor epitaxial wafer has an eV of not less than 1 MeV and a dose of the ions of not less than 1 × 10 15 cm −2 and not more than 1 × 10 19 cm −2 .
【請求項7】 上記イオンを打ち込んだ後、熱処理を行
って上記サファイア基板の表面結晶層若しくは上記剥離
用窒化物半導体層のイオン打ち込みによるダメージを回
復させると共に、表面近傍に微細なボイド及びボイドの
集合体を生じさせることにより上記中間層を形成する請
求項4から6のいずれかに記載の窒化物半導体エピタキ
シャルウェハの製造方法。
7. After the ion implantation, heat treatment is performed to recover damage caused by ion implantation of the surface crystal layer of the sapphire substrate or the nitride semiconductor layer for exfoliation, and to form minute voids and voids near the surface. The method for manufacturing a nitride semiconductor epitaxial wafer according to any one of claims 4 to 6, wherein the intermediate layer is formed by forming an aggregate.
【請求項8】 上記ボイド及びボイドの集合体の大き
さ、数量、密度、分布等を熱処理によって制御する請求
項7に記載の窒化物半導体エピタキシャルウェハの製造
方法。
8. The method for manufacturing a nitride semiconductor epitaxial wafer according to claim 7, wherein the size, quantity, density, distribution, and the like of the voids and the aggregate of the voids are controlled by heat treatment.
【請求項9】 上記熱処理をH2 若しくはNH3 あるい
は両者の混合雰囲気下で行う請求項7または8に記載の
窒化物半導体エピタキシャルウェハの製造方法。
9. The method of manufacturing a nitride semiconductor epitaxial wafer according to claim 7, wherein the heat treatment is performed in an atmosphere of H 2 or NH 3 or a mixture of both.
【請求項10】 上記中間層から上記サファイア基板ま
での部分を上記中間層を境に剥離させて除去する請求項
1から9のいずれかに記載の窒化物半導体エピタキシャ
ルウェハの製造方法。
10. The method for manufacturing a nitride semiconductor epitaxial wafer according to claim 1, wherein a portion from said intermediate layer to said sapphire substrate is removed by separating said intermediate layer from said intermediate layer.
【請求項11】 上記デバイス用窒化物半導体層の表面
に他の基板を貼り付けた後上記中間層から上記サファイ
ア基板までの部分を、上記中間層を境に剥離、除去する
請求項10に記載の窒化物半導体エピタキシャルウェハ
の製造方法。
11. The device according to claim 10, wherein a portion from the intermediate layer to the sapphire substrate is peeled off and removed from the intermediate layer after attaching another substrate to the surface of the nitride semiconductor layer for device. Of manufacturing a nitride semiconductor epitaxial wafer.
【請求項12】 上記他の基板としてSi等の半導体若
しくはAlN等の高熱伝導性基板あるいはCu、Al等
の金属を用いる請求項11に記載の窒化物半導体エピタ
キシャルウェハの製造方法。
12. The method of manufacturing a nitride semiconductor epitaxial wafer according to claim 11, wherein a semiconductor such as Si, a high thermal conductive substrate such as AlN, or a metal such as Cu or Al is used as the other substrate.
【請求項13】 上記サファイア基板を除去したデバイ
ス用窒化物半導体層に残ったサファイア基板の一部若し
くは上記サファイア基板を除去したデバイス用窒化物半
導体に残った剥離用窒化物半導体層の一部を研磨等の方
法によって除去する請求項10から12に記載の窒化物
半導体エピタキシャルウェハの製造方法。
13. A part of the sapphire substrate remaining in the device nitride semiconductor layer from which the sapphire substrate has been removed or a part of the peeling nitride semiconductor layer remaining in the device nitride semiconductor from which the sapphire substrate has been removed. The method for producing a nitride semiconductor epitaxial wafer according to claim 10, wherein the nitride semiconductor epitaxial wafer is removed by a method such as polishing.
【請求項14】 請求項1から13のいずれかに記載の
方法で製造された、Inx Aly Ga1-x-y N(x,y
≧1、x+y≦1)の組成を有することを特徴とする窒
化物半導体エピタキシャルウェハ。
14. produced by the method according to any of claims 1 13, In x Al y Ga 1-xy N (x, y
≧ 1, x + y ≦ 1) A nitride semiconductor epitaxial wafer having a composition of:
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CN111326409A (en) * 2018-12-14 2020-06-23 云谷(固安)科技有限公司 Laser lift-off method and light emitting diode device epitaxial structure on sapphire substrate
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CN111326409A (en) * 2018-12-14 2020-06-23 云谷(固安)科技有限公司 Laser lift-off method and light emitting diode device epitaxial structure on sapphire substrate
CN111326409B (en) * 2018-12-14 2023-01-31 云谷(固安)科技有限公司 Laser lift-off method and light emitting diode device epitaxial structure on sapphire substrate
CN113690263A (en) * 2020-05-18 2021-11-23 成都辰显光电有限公司 Display substrate and preparation method thereof
CN113690263B (en) * 2020-05-18 2024-02-06 成都辰显光电有限公司 Display substrate and preparation method thereof

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