JPS5821423B2 - Processing method for semiconductor devices - Google Patents

Processing method for semiconductor devices

Info

Publication number
JPS5821423B2
JPS5821423B2 JP54167278A JP16727879A JPS5821423B2 JP S5821423 B2 JPS5821423 B2 JP S5821423B2 JP 54167278 A JP54167278 A JP 54167278A JP 16727879 A JP16727879 A JP 16727879A JP S5821423 B2 JPS5821423 B2 JP S5821423B2
Authority
JP
Japan
Prior art keywords
semiconductor device
hydrogen
semiconductor devices
low
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54167278A
Other languages
Japanese (ja)
Other versions
JPS5690529A (en
Inventor
田玉尚武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Original Assignee
CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHO ERU ESU AI GIJUTSU KENKYU KUMIAI filed Critical CHO ERU ESU AI GIJUTSU KENKYU KUMIAI
Priority to JP54167278A priority Critical patent/JPS5821423B2/en
Publication of JPS5690529A publication Critical patent/JPS5690529A/en
Publication of JPS5821423B2 publication Critical patent/JPS5821423B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 本発明は電子線、X線等の粒子線による照射損傷を受け
た半導体装置かアニールするだめの処理方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for annealing semiconductor devices that have been damaged by irradiation with particle beams such as electron beams and X-rays.

周知の如く、半導体装置の製造においては、半導体基板
上に絶縁膜や金属膜をスパッタ蒸着する工程、電子線、
X線を用いた光蝕刻により形成されたレジストパターン
をマスクとして前記絶縁膜等を選択的にプラズマエツチ
ングする、いわゆるPEP工程等が繰り返し行なわれる
As is well known, in the manufacturing of semiconductor devices, there are processes such as sputter deposition of insulating films and metal films on semiconductor substrates, electron beams,
A so-called PEP process, etc., in which the insulating film and the like are selectively plasma etched using a resist pattern formed by photoetching using X-rays as a mask, is repeatedly performed.

ところが、これら工程のスパッタ、電子線露光等の粒子
線照射時に半導体基板が損傷を受け、C−■特性の変動
等が起こり、素子特性が著しく悪化する問題があった。
However, there is a problem in that the semiconductor substrate is damaged during particle beam irradiation such as sputtering and electron beam exposure in these steps, causing fluctuations in C-■ characteristics and the like, resulting in a significant deterioration of device characteristics.

このようなことから、従来、700℃以上の高温にした
電気炉内で水素又は不活性ガス雰囲気中・で熱処理して
半導体装置の粒子線照射損傷をアニールすることが行な
われている。
For this reason, conventionally, semiconductor devices have been subjected to heat treatment in an electric furnace heated to a high temperature of 700° C. or higher in a hydrogen or inert gas atmosphere to anneal damage caused by particle beam irradiation on semiconductor devices.

しかしながら、かかる方法では高温熱処理が必要なため
、半導体基板の反り発生を招き、結晶欠陥の発生による
特性劣化を起こし、しかも熱汚染による特性劣化を起こ
す等の不都合があった。
However, since such a method requires high-temperature heat treatment, there are disadvantages such as warping of the semiconductor substrate, deterioration of characteristics due to generation of crystal defects, and deterioration of characteristics due to thermal contamination.

またA[等の低融点金属配線の形成後に生じた粒子線照
射損傷は前記配線の低融点性から高温熱処理を行なうこ
とができず、完全にアニールすることが困難であった。
Further, particle beam irradiation damage caused after formation of a low melting point metal wiring such as A[ cannot be subjected to high temperature heat treatment due to the low melting point of the wiring, making it difficult to completely anneal it.

本発明は上記事情に鑑みなされたもので、粒子線の照射
損傷を受けた半導体装置を低温でアニールし得る処理方
法を提供しようとするものである。
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a processing method capable of annealing a semiconductor device damaged by particle beam irradiation at a low temperature.

すなわち、本発明は低融点金属配線の形成工程後の半導
体装置を少なくとも水素原子を含むプラズマ中で処理し
て該半導体装置の粒子線損傷を除去せしめることを特徴
とするものである。
That is, the present invention is characterized in that the semiconductor device after the step of forming the low melting point metal wiring is treated in plasma containing at least hydrogen atoms to remove particle beam damage from the semiconductor device.

本発明における低融点金属としては、例えばAl又はA
A−8i p Al−Cu5 Al−81−Cuなどの
AA金合金を挙げることができる。
Examples of the low melting point metal in the present invention include Al or A
Mention may be made of AA gold alloys such as A-8ip Al-Cu5 Al-81-Cu.

本発明における少なくとも水素原子を含むプラズマの生
成手段としては、水素ガスもしくは水素ガスと不活性ガ
ス(例えばHeガス)を所望圧力でプラズマ発生装置内
に導入し、所定の出力条件で水素原子のプラズマを発生
する方法が採用し得る。
In the present invention, as a means for generating plasma containing at least hydrogen atoms, hydrogen gas or hydrogen gas and an inert gas (for example, He gas) are introduced into a plasma generator at a desired pressure, and hydrogen atoms are generated under predetermined output conditions. A method of generating this can be adopted.

ここに言う水素原子とは水素ラジカル、水素分子、水素
イオン等が混在した状態である。
The hydrogen atom referred to here is a mixture of hydrogen radicals, hydrogen molecules, hydrogen ions, etc.

かかる水素ガスの圧力は0.5〜1.0Torr程度に
することが望ましく、0.5Torr未満にすると粒子
線損傷のアニールを十分達成し難くなり、かといって1
.0Torrを越えるとそのアニール効果に変わらなく
なるばかりか危険度が高くなる恐れがある。
It is desirable that the pressure of such hydrogen gas be about 0.5 to 1.0 Torr; if it is less than 0.5 Torr, it will be difficult to achieve sufficient annealing for particle beam damage, and on the other hand,
.. If the temperature exceeds 0 Torr, not only will the annealing effect not change, but the danger level may increase.

まだプラズマ中での処理はあまり長時間荷なうと、かえ
って損傷が増大することから、水素ガスの圧力や出力等
により適宜選定することが望ましい。
However, if the treatment in plasma is carried out for too long, the damage will increase, so it is desirable to select the hydrogen gas appropriately depending on the pressure and output of the hydrogen gas.

本発明における粒子線の照射損傷は電子線照射電子線蒸
着、プラズマエツチング、スパッタ蒸着X線照射等によ
り受けるものである。
In the present invention, particle beam irradiation damage is caused by electron beam irradiation, electron beam evaporation, plasma etching, sputter evaporation, X-ray irradiation, and the like.

なお、本発明においては少なくとも水素原子を含むプラ
ズマ中で処理すると共に低温アニールを施してもよい。
Note that in the present invention, low-temperature annealing may be performed while processing in plasma containing at least hydrogen atoms.

かかる低温アニールは窒素ガス又は窒素ガスと水素ガス
のフォーミングガス中で400〜500℃の温度で行な
うものであるが、プラズマ処理後に行なっても、場合に
よってはプラズマ処理時に同時に行なってもよい。
Such low-temperature annealing is carried out at a temperature of 400 to 500° C. in nitrogen gas or a forming gas of nitrogen gas and hydrogen gas, and may be carried out after the plasma treatment or, depending on the case, at the same time as the plasma treatment.

このような低温アニールを更に施せば半導体装置の粒子
線損傷を更に除去できると共に、MO8型半導体装置に
適用した場合、ゲート酸化膜の中性電子捕獲中心を除去
でき閾値電圧(VTI()の変動を抑制できる。
If such low-temperature annealing is further applied, particle beam damage to the semiconductor device can be further removed, and when applied to an MO8 type semiconductor device, neutral electron trapping centers in the gate oxide film can be removed, and fluctuations in the threshold voltage (VTI()) can be reduced. can be suppressed.

次に、本発明をMO8型集積回路に適用した例について
説明する。
Next, an example in which the present invention is applied to an MO8 type integrated circuit will be described.

実施例 l まず、面指数(100)、比抵抗1〜2Ω一口のP型シ
リコンウェハに選択的なイオン注入により素子分離のた
めのP十型反転防止層及び選択酸化により厚さ6000
Aのフィールド酸化膜を形成した後、酸素雰囲気中で熱
処理を施してフィールド酸化膜で囲まれた各素子形成領
域上に厚さ500にのシリコン酸化膜を成長させた。
Example 1 First, a P-type silicon wafer with a surface index (100) and a specific resistance of 1 to 2 Ω was subjected to selective ion implantation to form a P-type anti-inversion layer for device isolation and selective oxidation to a thickness of 6000 Ω.
After forming the field oxide film A, heat treatment was performed in an oxygen atmosphere to grow a silicon oxide film to a thickness of 500 mm on each element formation region surrounded by the field oxide film.

つづいて、厚さ4oooXのリンドープ多結晶シリコン
酸化膜し、パターニングして各素子形成領域のゲート酸
化膜上にゲート電極を形成し、さらにリンのイオンイン
プラによりソース、ドレインを形成した。
Subsequently, a phosphorus-doped polycrystalline silicon oxide film with a thickness of 400X was formed and patterned to form a gate electrode on the gate oxide film in each element formation region, and a source and drain were further formed by phosphorus ion implantation.

ひきつづき、全面に厚さ3oooXのCvD−8iO2
膜を堆積し、ソース、ドレイン、ゲートのコンタクトホ
ールを開孔し、更にA7膜を全面に堆積した。
Continue to apply CvD-8iO2 with a thickness of 3oooX on the entire surface.
A film was deposited, contact holes for the source, drain, and gate were opened, and then an A7 film was deposited on the entire surface.

その後、A7膜上に電子線感応レジスト膜を被覆し、加
速電圧20KeV、照射量3X 10−5C/crtf
、の条件で露光し、現像処理して所望のレジストパター
ンを形成した後、レジストパターンヲマスクとしてA7
膜を選択エツチングして各nチャンネルMO8)ランジ
スタと相互に結線したAl配線を形成してMO8型集積
回路を製造した。
After that, an electron beam sensitive resist film was coated on the A7 film, and the acceleration voltage was 20KeV and the irradiation amount was 3X 10-5C/crtf.
After exposing and developing under the following conditions to form a desired resist pattern, use an A7 mask as a mask for the resist pattern.
An MO8 type integrated circuit was manufactured by selectively etching the film to form Al wiring interconnecting each n-channel MO8 transistor.

ここで得られたMO8型集積回路は紫外線露光で形成さ
れたレジストパターンヲマスクとしてA7膜を選択エツ
チングしAl配線を形1成しだMO8型集積回路(初期
値)に比較して、高周波C−■特性が負側に犬きくシフ
トすると共に、低周波C−■特性も大きく変動した。
The MO8 type integrated circuit obtained here has high frequency C The -■ characteristic shifted sharply to the negative side, and the low-frequency C-■ characteristic also changed greatly.

次いで、図に示す円筒型プラズマ発生装置における真空
に保たれた石英シリンダー1内のホルダ′)−2に上記
方法で得たMO8型集積回路3を固定し、同シリンダー
1に連続した導入管4より水素ガスを0.8Torrの
条件で導入すると共に排気管5から排気しつつRFF極
6に接続した13.56MHz のRF電電源釦より出
力を400Wに設定ゴしてシリンダー1内のMO8型集
積回路3を15分間水素プラズマ処理した。
Next, the MO8 type integrated circuit 3 obtained by the above method was fixed to a holder')-2 in a quartz cylinder 1 maintained in a vacuum in the cylindrical plasma generator shown in the figure, and an inlet pipe 4 continuous to the cylinder 1 was fixed. Introducing hydrogen gas under the condition of 0.8 Torr and exhausting it from the exhaust pipe 5, set the output to 400W from the 13.56MHz RF electric power button connected to the RFF pole 6, and set the output to 400W. Circuit 3 was treated with hydrogen plasma for 15 minutes.

その結果、水素プラズマ処理後のMO3型集積回路は、
C−■特性が初期値に近い値となり、電子線露光で受け
だ損傷は大巾にアニールされていることがわかった。
As a result, the MO3 type integrated circuit after hydrogen plasma treatment is
The C-■ characteristic was close to the initial value, and it was found that the damage caused by electron beam exposure had been extensively annealed.

まノだ、この水素プラズマ処理中においては集積回路の
温度が200℃以上とならず、A7配線の劣化や、シリ
コンウェハーの反りに基因する結晶欠陥発生等はほとん
ど起きなかった。
Indeed, during this hydrogen plasma treatment, the temperature of the integrated circuit did not rise above 200°C, and there was almost no deterioration of the A7 wiring or the occurrence of crystal defects due to warping of the silicon wafer.

実施例 2 前記実施例1においてMO8型集積回路を水素プラズマ
中で処理した後、400℃のフォーミングガス中で30
分間低温アニール処理を施した。
Example 2 After the MO8 type integrated circuit was treated in hydrogen plasma in Example 1, it was treated in a forming gas at 400°C for 30 minutes.
A low-temperature annealing treatment was performed for 1 minute.

その結果、低温アニール処理後のMO8型集積回路はC
−■特性が初期値と同等の値となり、電子線露光で受け
た損傷をほぼ除去できることがわかった。
As a result, the MO8 type integrated circuit after low-temperature annealing is C
- ■Characteristics became values equivalent to the initial values, and it was found that damage caused by electron beam exposure could be almost eliminated.

しかも、MO8型集積回路のゲート酸化膜中の中性電子
捕獲中心も除去でき、VTf(の変動を抑制できた。
Furthermore, the neutral electron trapping center in the gate oxide film of the MO8 type integrated circuit could also be removed, making it possible to suppress fluctuations in VTf.

なお、本発明は上記実施例の如きMO8型集積回路に限
定されず、バイポーラ型集積回路等にも同様に適用でき
る。
Note that the present invention is not limited to the MO8 type integrated circuit as in the above embodiment, but can be similarly applied to bipolar type integrated circuits and the like.

以上詳述した如く、本発明によれば粒子線の照射損傷を
受けた半導体装置を低温でアニールできることにより低
融点金属配線の劣化や半導体基板の反り、熱汚染を招く
ことなくC−V特性等が改善された高性能、高信頼性の
半導体装置を提供し得る等顕著な効果を有する。
As detailed above, according to the present invention, semiconductor devices damaged by particle beam irradiation can be annealed at low temperatures, thereby improving C-V characteristics without causing deterioration of low-melting point metal wiring, warping of semiconductor substrates, or thermal contamination. It has remarkable effects such as being able to provide a semiconductor device with improved performance and high reliability.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の実施例1で用いた円筒型プラズマ発生装置
の一形態を示す概略図である。 1・・・石英シリンダー、2・・・ホルダー、3・・・
MO8型集積回路、4・・・導入管、5・・・排気管、
6・・・RF電極、7・・・RF主電源
The figure is a schematic diagram showing one form of a cylindrical plasma generator used in Example 1 of the present invention. 1...Quartz cylinder, 2...Holder, 3...
MO8 type integrated circuit, 4...introduction pipe, 5...exhaust pipe,
6...RF electrode, 7...RF main power supply

Claims (1)

【特許請求の範囲】 1 低融点金属配線の形成工程後の半導体装置を少なく
とも水素原子を含むプラズマ中で処理して該半導体装置
の粒子線損傷を除去せしめることを特徴とする半導体装
置の処理方法。 2 低融点金属配線がアルミニウム配線であることを特
徴とする特許請求の範囲第1項記載の半導体装置の処理
方法。 3 少なくとも水素原子を含むプラズマ中で処理すると
共に低温アニール処理を施すことを特徴とする特許請求
の範囲第1項記載の半導体装置の処理方法。
[Claims] 1. A method for processing a semiconductor device, which comprises treating the semiconductor device after the step of forming a low melting point metal wiring in plasma containing at least hydrogen atoms to remove particle beam damage from the semiconductor device. . 2. The method of processing a semiconductor device according to claim 1, wherein the low melting point metal wiring is an aluminum wiring. 3. The method of processing a semiconductor device according to claim 1, characterized in that processing is performed in plasma containing at least hydrogen atoms and low-temperature annealing treatment is performed.
JP54167278A 1979-12-22 1979-12-22 Processing method for semiconductor devices Expired JPS5821423B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54167278A JPS5821423B2 (en) 1979-12-22 1979-12-22 Processing method for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54167278A JPS5821423B2 (en) 1979-12-22 1979-12-22 Processing method for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5690529A JPS5690529A (en) 1981-07-22
JPS5821423B2 true JPS5821423B2 (en) 1983-04-30

Family

ID=15846772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54167278A Expired JPS5821423B2 (en) 1979-12-22 1979-12-22 Processing method for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS5821423B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137218A (en) * 1982-02-09 1983-08-15 Nec Corp Treatment of silicon single crystal substrate
JPS6045040A (en) * 1983-08-23 1985-03-11 Ricoh Co Ltd Formation of thin film pattern

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123276A (en) * 1973-03-29 1974-11-26
JPS5146882A (en) * 1974-10-18 1976-04-21 Mitsubishi Electric Corp Handotaisochi oyobisono seizohoho

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123276A (en) * 1973-03-29 1974-11-26
JPS5146882A (en) * 1974-10-18 1976-04-21 Mitsubishi Electric Corp Handotaisochi oyobisono seizohoho

Also Published As

Publication number Publication date
JPS5690529A (en) 1981-07-22

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