JPH0582473A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a tightly coupled metallic pattern to be formed on a semiconductor surface or inside a trench by a method wherein a semiconductor wafer is irradiated with inert gas ions and then immersed in a metallic ion solution to be heated later. CONSTITUTION:An insert gas e.g. Ar ion beams 2 are made pass through a shielding plate 3 to irradiate the specific region in a silicon wafer 4. Next, the Ar ion implanted silicon wafer 4 is immersed in a Cu ion solution to deposit Cu in the Ar ion irradiated region. Next, the silicon wafer 4 is heated to turn the Cu wiring formed on the wafer surface or inside a trench 13 into silicide for tightening the coupling of the Cu with the silicon wafer 4. Accordingly, the metallic wiring pattern need not be formed in vacuum state thereby enabling the thickness thereof to be controlled with high precision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to irradiating the surface of the semiconductor device with an inert gas ion to deposit a metal in a target region and heating the metal to form a strong metal. The present invention relates to a method of forming wiring.

[0002]

2. Description of the Related Art Conventionally, Al and Al alloys have been used for metal patterns on the surface of semiconductor devices.
Japanese Patent Application Laid-Open No. 58-1
As described in JP-A-06821, JP-A-59-20464 and JP-A-59-72131, PVD
Formed by a dry method such as a CVD method or a CVD method,
A refractory metal film such as W, a silicon compound thereof, or the like has been used.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention PVD method and CVD
In the dry method such as the 1) method, 1) the metal is formed in a vacuum, so that the apparatus is complicated and the processing time is long. 2) The inside of the processing tank is heavily contaminated. 3) Since the metal film formed on the entire surface of the semiconductor is patterned by etching, only the pattern portion cannot be selectively formed. 4) Since it is very difficult to control the partial vapor deposition and the deposition amount, it is necessary to use a photo-etching method in which a photoresist is applied to form the wiring pattern. There was a problem such as.

In particular, when the Cu film is wet-processed into a metal pattern, a fine pattern of a mask cannot be accurately formed on the semiconductor surface. For example, when Cu is formed on the surface of a silicon wafer in an HF solution, it is not possible to form a uniform Cu film because the deposition state of Cu differs depending on the crystal orientation. Further, there is also a problem that the metal cannot be uniformly deposited in the deep trench formed by dry etching or the like.
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of selectively forming a metal pattern having a strong bond on the semiconductor surface or in the trench.

[0005]

In order to solve the above problems, a semiconductor wafer such as silicon is irradiated with an inert gas ion such as Ar, and then the semiconductor wafer is exposed to Cu or Au whose standard electrode potential is higher than that of silicon. Alternatively, the metal is immersed in an ion solution of a metal such as Pt to deposit the metal on the irradiation portion of the Ar gas ions, and then the semiconductor wafer is heated to silicify the metal deposition portion. Further, the silicided metal film is patterned by masking, etching or the like. Further, a wiring pattern mask such as a resist film or a semiconductor oxide film is previously formed on the surface of the semiconductor wafer, and the inert gas ion beam is irradiated from above the wiring pattern mask. Also,
The surface of the semiconductor wafer is obliquely irradiated with the above-mentioned inert gas ions so that the above-mentioned inert gas ions are spread to the side surface portion of the trench (deep groove).

[0006]

By the irradiation of the inert gas ions, defects are formed on the wafer surface, and metal ions such as Cu, Au or Pt are selectively and densely and uniformly deposited using the defects as nuclei. Further, by controlling the amount of the inert gas ion implantation,
The amount of metal deposition is controlled according to the type of crystal plane of the semiconductor wafer. Also, by inclining to the surface of the semiconductor wafer, the inert gas ions spread to the side surface portion of the trench (deep groove), and metal ions are also deposited on the side surface portion.
Further, by the heating, the metal ion precipitation portion is silicified and becomes strong. Further, the patterning of the metal film is performed after the silicidation or by irradiating the inert gas ion beam through the mask pattern.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS To form a metal pattern of a semiconductor device according to the present invention, for example, a method of forming a metal film on the entire surface of a wafer or a chip on which a metal pattern is formed, and then etching the metal film to form a pattern. There are two methods, that is, a resist pattern or the like is previously provided on the wafer and then a metal film is formed in the opening.

FIG. 1 is a flow chart of the method for forming a metal film according to the present invention. In FIG. 1, the flow on the left side
Is a case where a metal film is formed on a wide area surface of a wafer or a chip, and the flow on the right side is a case where a metal pattern is formed through a wiring pattern mask such as a resist or silicon oxide provided on the wafer. In addition, step S in the left flow
1 to S3 and the contents of steps S1 to S3 in the right side flow are the same. In the left side flow, an inert gas ion such as Ar is implanted into a predetermined surface of the wafer or chip in step S1, and the wafer is immersed in a Cu ion solution in step S2 to implant the inert gas ion surface. Cu is deposited on. Next, in step S3, the silicon wafer is heated to silicify the deposited Cu to strengthen the bond between Cu and the silicon wafer, and in step S4, a resist pattern is formed on the silicidized Cu surface to perform etching. Then, the Cu surface is patterned. In the right side flow, a wiring pattern of a resist or a silicon oxide film is formed on the wafer in step S5, and then the above step S5 is performed.
A patterned Cu film is formed by the processes of 1 to S3.

When forming a metal film on a wide area surface of the above-mentioned wafer or chip, inert gas ions 2 are implanted into the surface of a semiconductor device such as a silicon wafer 4 as shown in FIG. For example, the Ar ion beam 2 generated by the Ar ion generator 1 is passed through the slit of the shield plate 3 and the silicon wafer 4
Irradiate a predetermined area of. The Ar ion implanter 1 can be evacuated. The implantation amount of the Ar ions is controlled by adjusting the irradiation current of the Ar ion beam and the irradiation time. For example, Ar ions accelerated to 300 keV are irradiated until the ion density on the surface of the silicon wafer reaches about 10 ¹⁴ / cm ^2. .. The shielding plate 3 is omitted, and the narrowed Ar ion beam is scanned on the silicon wafer 4, or the Ar ion beam is fixed and the silicon wafer 4 is moved to irradiate the Ar ion beam. You can also do

Then, the Ar ion-implanted silicon wafer 4 is dipped in a Cu ion solution for a predetermined time, and the above A
Cu is deposited in the r ion irradiation region. Since the standard electrode potential of Cu is higher than that of silicon, Cu is deposited on the silicon wafer 4 by the above immersion. In addition to Cu, a metal such as Au or Pt having a standard electrode potential higher than that of Si can be used. The Cu ion solution is, for example, an HF solution in which about 100 ppm Cu ions are dissolved.

FIG. 3 shows the case where Ar ions are implanted as described above to deposit Cu ((a) and (b)) and the case where Ar ion implantation is omitted ((c) and (d)). It is a figure which compares and shows the state of a Cu surface, (a) and (c) are top views,
(B) And (d) is sectional drawing. When Ar ions are implanted to deposit Cu ions, as shown in (a) and (b),
A uniform and dense Cu film is deposited on the Ar ion-implanted surface 7. Further, such uniform and dense Cu precipitation does not relate to the crystal orientations (100), (111), etc. of the silicon wafer 4. On the other hand, when the implantation of Ar ions is omitted, Cu is scattered and deposited as shown in (c) and (d). Further, as the silicon wafer 4, for example, the crystal orientation generated by the Czochralski method is (100)
And (111) P-type and N-type wafers CZ-P (1
00), CZ-N (100), CZ-P (111), C
ZN (111) or the like can be used.

Next, a method of forming a metal film after providing a resist pattern or the like on the wafer in advance will be described with reference to the process chart of FIG. In FIG. 4, a photoresist and a silicon oxide film are substantially used instead of the shield plate 3 of FIG. First, as shown in FIG. 4A, an oxide film 10 is formed on a silicon wafer 4, and a photoresist 9 is applied thereon. Next, as shown in FIG. 2B, the photoresist 9 is exposed and developed, and then the oxide film 10 is patterned as shown in FIG. Next, the photoresist 9 is removed as shown in FIG. 4 (4), and the oxide film 10 is removed as shown in FIG. 5 (5).
The Ar ion beam is irradiated from above the pattern to inject about 10 ¹⁴ / cm ² Ar ions into the surface of the silicon wafer 4 to remove the oxide film 10. Then, by dipping the above-mentioned wafer in an HF solution in which about 100 ppm of Cu ions are dissolved, an accurate Cu fine wiring pattern 11 can be formed as shown in FIG. The oxide film 10
Patterning photoresist 9 by omitting the step of forming
A Cu fine wiring pattern is formed by implanting the Ar ions from above.
It is also possible to form the ring 11 in the same manner.

Next, a method of forming the Cu pattern at the bottom of the trench (deep groove portion) formed on the silicon wafer 4 will be described with reference to FIGS. Usually, the trench is formed by dry etching an oxide film mask on the silicon wafer 4. Further, in the present invention, the implantation of Ar ions 2 using the oxide film 10 as a mask is also used for forming the metal wiring pattern in the trench in the same manner as in FIG. Generally, since it is necessary to form a metal wiring pattern also on the side surface of the trench, the Ar ion beam 2 is uniformly implanted also on the side surface of the trench as shown in FIG. That is, the silicon wafer 4 is appropriately tilted and is rotated while being irradiated with the Ar ion beam 2 as shown by 41 to 43 in FIG. 5, and the Ar ion beam 2 is evenly distributed on the side surface of the trench 13 as shown in FIG. To inject.

Next, about 100 of the silicon wafer 4 is placed.
When immersed in an HF solution in which ppm Cu ions are dissolved, Cu can be evenly deposited inside the trench 13. Next, the silicon wafer 4 is heated to silicify the Cu wiring 11 formed on the surface thereof or in the trench 13 to strengthen the bond between Cu and the silicon wafer. FIG. 7 is a diagram showing an example of the heat treatment apparatus. A quartz tray 14 on which a plurality of silicon wafers 4 are mounted is inserted into a heat treatment apparatus 18 from a wafer introduction port 17 and heated by a heater 15 covered with a heat insulating material 16 to silicidize a Cu wiring pattern.

[0015]

According to the present invention, since a silicon wafer previously irradiated with an inert gas such as Ar can be dipped in a metal solution such as Cu to form a dense metal film, a metal wiring pattern can be formed. Since it is not necessary to form in vacuum, the apparatus can be simplified and the processing time can be shortened. Further, the metal film can be formed uniformly regardless of the crystal orientation of the silicon wafer, and the thickness can be accurately controlled by controlling the implantation amount of the inert gas ions. Further, the metal film can be silicidized by a simple heat treatment and firmly bonded to the wafer surface. In addition, the inert gas ion beam is used as a mask pattern.
The metal film can be patterned by irradiating the metal film or etching the metal film after silicidation. Further, by irradiating the surface of the semiconductor wafer with the above-mentioned inert gas ions and irradiating them, the metal ions can be deposited on the side surfaces of the trench (deep groove) to form a metal film pattern.

[Brief description of drawings]

FIG. 1 is a flowchart of a method for forming a metal film according to the present invention.
It is

FIG. 2 is an explanatory diagram of a method of implanting inert gas ions into a silicon wafer.

FIG. 3 is an explanatory diagram of a Cu deposition state on an inert gas ion implantation surface.

FIG. 4 shows a metal film pattern on a silicon wafer according to the present invention.
FIG.

FIG. 5 is an explanatory view of a method of irradiating the inside of a trench of a silicon wafer with Ar ions according to the present invention.

FIG. 6 is an explanatory diagram of a method of irradiating the inside of a trench of a silicon wafer with Ar ions according to the present invention.

FIG. 7 is a front view of a heat treatment apparatus for a Cu protrusion on the surface of a silicon wafer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Ar ion generator 2 Ar ion beam 3 Shielding plate 4 Silicon wafer 6 Cu point deposition area 7 Cu dense deposition area 9 Photoresist 10 Silicon oxide film 11 Cu fine pattern 12 Rotation direction of silicon wafer 13 Trench 14 Tray 15 Heater 16 Thermal Insulation Cover 17 Wafer Inlet 18 Heat Treatment Device

Claims (7)

[Claims] 1. A first step of irradiating a semiconductor wafer with inert gas ions, and immersing the semiconductor wafer after the first step in a metal ion solution to deposit the metal ions on the irradiation portion of the inert gas ions. Manufacturing of a semiconductor device, characterized in that a metal film is formed on the semiconductor wafer by a second step and a third step of heating the semiconductor wafer after the second step to silicide the metal. Method. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a fourth step of forming a pattern on the metal film silicidized by the third step. 3. The semiconductor device according to claim 1, wherein a mask defining an irradiation range of the inert gas ion beam is formed on the surface of the semiconductor wafer as a pre-process of the first process. Production method. 4. The method according to any one of claims 1 to 3,
The inert gas ions in the first step were irradiated from an oblique direction on the surface of the semiconductor wafer, and the side surfaces of the trench (deep groove) formed on the semiconductor wafer were also irradiated with the inert gas ions. A method of manufacturing a semiconductor device, comprising: 5. The method according to any one of claims 1 to 4,
A method of manufacturing a semiconductor device, wherein the inert gas in the first step is Ar gas. 6. The method according to any one of claims 1 to 5,
A method for manufacturing a semiconductor device, wherein the metal ion solution is a solution of metal ions having a standard electrode potential higher than that of the semiconductor wafer material. 7. The semiconductor wafer material according to claim 6, wherein the semiconductor wafer material is silicon, and the metal of the metal ion is Cu or A.
A method of manufacturing a semiconductor device, wherein u or Pt is used.