CN115110147A - Method for growing low-warpage semiconductor substrate wafer - Google Patents
Method for growing low-warpage semiconductor substrate wafer Download PDFInfo
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- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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Abstract
The invention discloses a method for growing a low-warpage semiconductor substrate wafer, which comprises the following steps: s1) depositing a dielectric layer: depositing a first dielectric layer and a second dielectric layer on the back and the front of the substrate wafer, wherein the first dielectric layer and the second dielectric layer satisfy alpha 1 ×T 1 ＝α 2 ×T 2 (ii) a S2) high-temperature annealing; s3) removing the second medium layer and polishing and cleaning; s4) the substrate wafer is subjected to epitaxial growth: carrying out epitaxial growth on the substrate wafer with the first dielectric layer deposited on the back surface in the step S3); s5) removing the first medium layer and grinding, polishing and cleaning. The method comprises the steps of depositing a dielectric layer with rigidity higher than that of the substrate wafer on the front surface and the back surface of the substrate wafer in advance, wherein the deformation restraint can be carried out on the epitaxial wafer through the synergistic thermal expansion of the two dielectric layers, so that the warping degree of the substrate wafer is reduced during high-temperature annealing, removing the dielectric layer on the front surface after the high-temperature annealing, retaining the dielectric layer on the back surface, and protecting the substrate wafer through the dielectric layer on the back surfaceAnd the low warpage of the glass is maintained.
Description
Technical Field
The invention relates to the technical field of semiconductor epitaxy, in particular to a method for growing a low-warpage semiconductor substrate wafer.
Background
At present, the semiconductor material is not available for human life, and the application of the semiconductor material in the fields of new energy power generation, power processing, microwave radio frequency, photoelectricity and the like is ubiquitous. As an upstream process for semiconductor device applications, epitaxial growth is a very important fundamental link. The warping degree of the substrate wafer is an important parameter of the quality of the epitaxial wafer, the warping degree before and after epitaxy is obviously increased, the influence is more obvious particularly in large-size and thick epitaxy, the exposure precision is reduced, and the risk of fragments is increased; crystal defects and even microcracks are also associated to relieve the accumulation of stress; in addition, a thicker mask layer is usually formed on the surface of the substrate wafer during the epitaxial growth process, which also increases warpage and reduces the processing precision. Although the warpage is reduced by the high temperature annealing process in the prior art, the warpage of the substrate wafer is still large.
Disclosure of Invention
To overcome the disadvantages and shortcomings of the prior art, it is an object of the present invention to provide a method for growing a low warp semiconductor substrate wafer.
The purpose of the invention is realized by the following technical scheme: a method of growing a low warp semiconductor substrate wafer comprising the steps of:
s1) depositing a dielectric layer: depositing a first dielectric layer and a second dielectric layer on the back surface and the front surface of the substrate wafer, wherein the rigidity of the first dielectric layer and the rigidity of the second dielectric layer are higher than that of the substrate wafer, and the thermal expansion coefficients of the first dielectric layer and the second dielectric layer are respectively alpha 1 、α 2 The thicknesses of the first dielectric layer and the second dielectric layer are respectively T 1 、T 2 The first dielectric layer and the second dielectric layer satisfy alpha 1 ×T 1 ＝α 2 ×T 2 (ii) a The substrate wafer is positioned between the first medium layer and the second medium layer, and the warpage of the substrate wafer is reduced during high-temperature annealing due to the cooperative thermal expansion of the first medium layer and the second medium layer;
s2) high-temperature annealing: carrying out high-temperature annealing treatment on the substrate wafer in the step S1), and slowly cooling to room temperature; the high-temperature annealing treatment is an air isolation condition, the temperature is 500-;
s3) removing the second medium layer and polishing and cleaning: removing the second dielectric layer deposited on the front surface of the substrate wafer in the step S2), and grinding, polishing and cleaning;
s4) the substrate wafer is subjected to epitaxial growth: carrying out epitaxial growth on the substrate wafer with the first dielectric layer deposited on the back surface in the step S3);
s5) removing the first medium layer and grinding, polishing and cleaning: and removing the first dielectric layer deposited on the back surface of the substrate wafer in the step S4), and grinding, polishing and cleaning to obtain the substrate wafer with low warpage.
As an improvement of the method for growing the low-warpage semiconductor substrate wafer, the materials of the first dielectric layer and the second dielectric layer respectively comprise tungsten, molybdenum, tantalum, niobium, vanadium, chromium, titanium, zirconium, rare earth metals and alloys thereof, and non-metallic boride, carbide, nitride, silicide, phosphide, sulfide or the combination of any two or more of the above materials.
As an improvement of the method for growing the low-warpage semiconductor substrate wafer, the deposition method of the first dielectric layer and the second dielectric layer comprises magnetron sputtering, electrochemical deposition, physical vapor deposition or chemical vapor deposition.
As an improvement of the method for growing the low-warpage semiconductor substrate wafer, the first dielectric layer and the second dielectric layer are the same in thermal expansion coefficient and thickness, and are made of the same material.
As an improvement of the method for growing the low-warpage semiconductor substrate wafer, the method for removing the second dielectric layer in the step S3) comprises a wet or dry etching process of plasma etching and chemical reagent etching, wherein the grinding and polishing cleaning process comprises mechanical grinding, Chemical Mechanical Polishing (CMP) and cleaning to remove organic and inorganic impurities on the front surface of the substrate wafer, and the flat, smooth and clean front surface of the substrate wafer is obtained after the removing and grinding and polishing cleaning processes.
As an improvement of the method for growing the low-warpage semiconductor substrate wafer, the method for removing the first dielectric layer in the step S5) comprises a wet or dry etching process of plasma etching and chemical reagent etching, wherein the grinding and polishing cleaning process comprises mechanical grinding and chemical mechanical polishing CMP (chemical mechanical polishing), the upper surface of the substrate wafer is protected by waxing in the grinding and polishing process, and after the grinding and polishing process is finished, the cleaning is carried out to remove organic and inorganic impurities on the surface and the back surface of the substrate wafer.
As an improvement of the method for growing the low-warpage semiconductor substrate wafer, the reaction gas source for epitaxial growth in the step S4) is methane, trichlorosilane and nitrogen, the carrier gas is hydrogen, the flow rate is 80scl-100scl, the growth temperature is 1000-.
The invention has the beneficial effects that: according to the invention, the dielectric layers with rigidity higher than that of the substrate wafer are deposited on the front surface and the back surface of the substrate wafer in advance, deformation restraint can be carried out on the epitaxial wafer by synergistic thermal expansion of the two dielectric layers, so that the warpage of the substrate wafer is reduced during high-temperature annealing, the dielectric layer on the front surface is removed after high-temperature annealing, the dielectric layer on the back surface is reserved, the dielectric layer on the back surface can protect the substrate wafer, the low warpage of the substrate wafer is maintained, the warpage of the substrate wafer during epitaxial growth can be prevented, the problems of warpage or fragments and the like of the substrate wafer during the epitaxial growth process are reduced, and the processing precision of the substrate wafer is improved and the risks such as fragments and the like are reduced.
Drawings
FIG. 1 is a schematic diagram of the present invention structure for depositing a dielectric layer on both the back side and the front side of a substrate wafer;
FIG. 2 is a schematic diagram of the present invention showing the removal of the dielectric layer from the front side of the substrate wafer;
FIG. 3 is a schematic view of a substrate wafer structure after epitaxial growth of the present invention;
FIG. 4 is a schematic diagram of the present invention showing the removal of the dielectric layer from the backside of the substrate wafer;
the reference signs are: 1. substrate wafer 2, first dielectric layer 3, second dielectric layer 4, epitaxial layer
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The first embodiment is as follows: as shown in fig. 1 to 4, a method for growing a low warp semiconductor substrate wafer comprises the following steps:
s1) depositing a dielectric layer: depositing a first medium layer 2 and a second medium layer 3 on the back surface and the front surface of the substrate wafer 1, wherein the rigidity of the first medium layer 2 and the second medium layer 3 is higher than that of the substrate wafer 1, and the thermal expansion coefficients of the first medium layer 2 and the second medium layer 3 are respectively alpha 1 、α 2 The thicknesses of the first dielectric layer 2 and the second dielectric layer 3 are respectively T 1 、T 2 First dielectric layer 2 and second dielectric layerThe two dielectric layers 3 satisfy alpha 1 ×T 1 ＝α 2 ×T 2 (ii) a The substrate wafer 1 is positioned between the first medium layer 2 and the second medium layer 3, and deformation restraint can be carried out on the epitaxial wafer through the synergistic thermal expansion of the first medium layer 2 and the second medium layer 3, so that the warping degree of the substrate wafer is reduced during high-temperature annealing; the first dielectric layer 2 and the second dielectric layer 3 are both made of tantalum carbide; the deposition method of the first dielectric layer and the second dielectric layer adopts a chemical vapor phase method;
s2) high-temperature annealing: carrying out high-temperature annealing treatment on the substrate wafer 1 in the step S1), and slowly cooling to room temperature; the high-temperature annealing treatment is carried out under the condition of air isolation (or in a sealed environment), the temperature is 1200 ℃, the time is 30min, and after the high-temperature annealing is finished, the temperature is slowly reduced to the room temperature, wherein the temperature reduction rate is 39 ℃/min;
s3) removing the second dielectric layer 3 and polishing and cleaning: removing the second dielectric layer 3 deposited on the front surface of the substrate wafer 1 in the step S2), and grinding, polishing and cleaning; the method for removing the second dielectric layer 3 comprises but is not limited to a wet or dry etching process of plasma etching and chemical reagent etching, the grinding, polishing and cleaning process comprises mechanical grinding, Chemical Mechanical Polishing (CMP), cleaning to remove organic and inorganic impurities on the front surface of the substrate wafer, and obtaining a flat, smooth and clean front surface of the substrate wafer after the removal and grinding, polishing and cleaning processes;
s4) epitaxial growth of the substrate wafer 1 to form an epitaxial layer 4: carrying out epitaxial growth on the substrate wafer 1 with the first dielectric layer 2 deposited on the back surface in the step S3); the reaction gas source for epitaxial growth is methane, trichlorosilane and nitrogen, the carrier gas is hydrogen, the flow rate is 150scl, the growth temperature is 1600 ℃, the growth rate is 50um/h, the carbon-silicon ratio is 1, and the pressure is 100 mbar.
S5) removing the first dielectric layer 2 and polishing and cleaning: and removing, grinding, polishing and cleaning the first dielectric layer 2 deposited on the back surface of the substrate wafer 1 in the step S4). The method for removing the first dielectric layer 2 adopts a wet or dry etching process of chemical reagent etching, the grinding and polishing cleaning process comprises mechanical grinding and chemical mechanical polishing CMP, the upper surface of the substrate wafer is protected by waxing in the grinding and polishing process, and after the grinding and polishing process is finished, organic and inorganic impurities on the surface and the back of the substrate wafer are cleaned and removed, so that the substrate wafer with low warpage is obtained.
Example two: a method of growing a low warp semiconductor substrate wafer comprising the steps of:
s1) depositing a dielectric layer: depositing a first dielectric layer 2 and a second dielectric layer 3 on the back and the front of a substrate wafer 1, wherein the rigidity of the first dielectric layer 2 and the second dielectric layer 3 is higher than that of the substrate wafer 1, and the thermal expansion coefficients of the first dielectric layer 2 and the second dielectric layer 3 are respectively alpha 1 、α 2 The thicknesses of the first dielectric layer 2 and the second dielectric layer 3 are respectively T 1 、T 2 The first dielectric layer 2 and the second dielectric layer 3 satisfy α 1 ×T 1 ＝α 2 ×T 2 (ii) a The substrate wafer 1 is positioned between the first medium layer 2 and the second medium layer 3, and deformation restraint can be carried out on the epitaxial wafer through the synergistic thermal expansion of the first medium layer 2 and the second medium layer 3, so that the warping degree of the substrate wafer is reduced during high-temperature annealing; the first dielectric layer 2 and the second dielectric layer 3 are made of boron nitride, the first dielectric layer and the second dielectric layer are deposited by an electrochemical deposition method, and the first dielectric layer and the second dielectric layer are deposited simultaneously;
s2) high-temperature annealing: carrying out high-temperature annealing treatment on the substrate wafer 1 in the step S1), and slowly cooling to room temperature; the high-temperature annealing treatment is carried out under the condition of air isolation (or in a sealed environment), the temperature is 1000 ℃, the time is 15min, and after the high-temperature annealing is finished, the temperature is slowly reduced to the room temperature, wherein the temperature reduction rate is 30 ℃/min;
s3) removing the second dielectric layer 3 and polishing and cleaning: removing the second dielectric layer 3 deposited on the front surface of the substrate wafer 1 in the step S2), and grinding, polishing and cleaning; removing the second dielectric layer 3, namely a plasma etching process, wherein the grinding and polishing cleaning process comprises mechanical grinding, Chemical Mechanical Polishing (CMP), cleaning to remove organic and inorganic impurities on the front surface of the substrate wafer, and obtaining a flat, smooth and clean front surface of the substrate wafer after the removal and grinding and polishing cleaning processes;
s4) epitaxial growth of the substrate wafer 1 to form an epitaxial layer 4: carrying out epitaxial growth on the substrate wafer 1 with the first dielectric layer 2 deposited on the back surface in the step S3); the reaction gas source for epitaxial growth is methane, trichlorosilane and nitrogen, the carrier gas is hydrogen, the flow rate is 80scl, the growth temperature is 1600 ℃, the growth rate is 70um/h, the carbon-silicon ratio is 1, and the pressure is 70 mbar.
S5) removing the first dielectric layer 2 and polishing and cleaning: and removing, grinding, polishing and cleaning the first dielectric layer 2 deposited on the back surface of the substrate wafer 1 in the step S4). The method for removing the first dielectric layer 2 adopts a wet or dry etching process of chemical reagent etching, the grinding and polishing cleaning process comprises mechanical grinding and chemical mechanical polishing CMP, the upper surface of the substrate wafer is protected by waxing in the grinding and polishing process, and after the grinding and polishing process is finished, organic and inorganic impurities on the surface and the back of the substrate wafer are cleaned and removed, so that the substrate wafer with low warpage is obtained.
Example three: a method of growing a low warp semiconductor substrate wafer comprising the steps of:
s1) depositing a dielectric layer: depositing a first medium layer 2 and a second medium layer 3 on the back surface and the front surface of the substrate wafer 1, wherein the rigidity of the first medium layer 2 and the second medium layer 3 is higher than that of the substrate wafer 1, and the thermal expansion coefficients of the first medium layer 2 and the second medium layer 3 are respectively alpha 1 、α 2 The thicknesses of the first dielectric layer 2 and the second dielectric layer 3 are respectively T 1 、T 2 The first dielectric layer 2 and the second dielectric layer 3 satisfy α 1 ×T 1 ＝α 2 ×T 2 (ii) a The substrate wafer 1 is positioned between the first medium layer 2 and the second medium layer 3, and the deformation of the epitaxial wafer can be restrained by the synergistic thermal expansion of the first medium layer 2 and the second medium layer 3, so that the warping degree of the substrate wafer is reduced during high-temperature annealing; the first dielectric layer 2 and the second dielectric layer 3 are made of silicon nitride; the deposition method of the first dielectric layer and the second dielectric layer adopts physical vapor deposition or chemical vapor deposition;
s2) high-temperature annealing: carrying out high-temperature annealing treatment on the substrate wafer 1 in the step S1), and slowly cooling to room temperature; the high-temperature annealing treatment is carried out under the condition of air isolation (or in a sealed environment), the temperature is 900 ℃, the time is 20min, after the high-temperature annealing is finished, the temperature is slowly reduced to the room temperature, and the cooling rate is 39 ℃/min;
s3) removing the second dielectric layer 3 and polishing and cleaning: removing the second dielectric layer 3 deposited on the front surface of the substrate wafer 1 in the step S2), and grinding, polishing and cleaning; the method for removing the second dielectric layer 3 adopts a wet or dry etching process of chemical reagent etching, the grinding, polishing and cleaning process is firstly mechanical grinding, then Chemical Mechanical Polishing (CMP), and then cleaning and removing organic and inorganic impurities on the front surface of the substrate wafer, and the front surface of the substrate wafer which is flat, smooth and clean is obtained after the removal and grinding, polishing and cleaning processes;
s4) epitaxial growth of the substrate wafer 1 to form an epitaxial layer 4: carrying out epitaxial growth on the substrate wafer 1 with the first dielectric layer 2 deposited on the back surface in the step S3); the reaction gas source for epitaxial growth is methane, trichlorosilane and nitrogen, the carrier gas is hydrogen, the flow rate is 100scl, the growth temperature is 1600 ℃, the growth rate is 60um/h, the carbon-silicon ratio is 1, and the pressure is 80 mbar.
S5) removing the first dielectric layer 2 and polishing and cleaning: and removing, grinding, polishing and cleaning the first dielectric layer 2 deposited on the back surface of the substrate wafer 1 in the step S4). The method for removing the first dielectric layer 2 adopts a plasma etching process, the grinding and polishing cleaning process comprises mechanical grinding and chemical mechanical polishing CMP, the upper surface of the substrate wafer is protected by waxing in the grinding and polishing process, and after the grinding and polishing process is finished, organic and inorganic impurities on the surface and the back of the substrate wafer are cleaned and removed, so that the substrate wafer with low warpage is obtained.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and arrangements of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. A method of growing a low warp semiconductor substrate wafer, comprising the steps of:
s1) depositing a dielectric layer: depositing a first dielectric layer and a second dielectric layer on the back surface and the front surface of the substrate wafer, wherein the rigidity of the first dielectric layer and the rigidity of the second dielectric layer are higher than that of the substrate wafer, and the thermal expansion coefficients of the first dielectric layer and the second dielectric layer are respectively alpha 1 、α 2 Of the first dielectric layer and the second dielectric layerThickness is T 1 、T 2 The first dielectric layer and the second dielectric layer satisfy alpha 1 ×T 1 ＝α 2 ×T 2 ；
S2) high-temperature annealing: carrying out high-temperature annealing treatment on the substrate wafer in the step S1), and slowly cooling to room temperature; the high-temperature annealing treatment is an air isolation condition, the temperature is 500-;
s3) removing the second medium layer and polishing and cleaning: removing the second dielectric layer deposited on the front surface of the substrate wafer in the step S2), and grinding, polishing and cleaning;
s4) the substrate wafer is subjected to epitaxial growth: carrying out epitaxial growth on the substrate wafer with the first dielectric layer deposited on the back surface in the step S3);
s5) removing the first medium layer and polishing and cleaning: and removing the first dielectric layer deposited on the back surface of the substrate wafer in the step S4), and grinding, polishing and cleaning to obtain the substrate wafer with low warpage.
2. The method of growing low warpage semiconductor substrate wafers of claim 1, wherein the material of the first dielectric layer and the second dielectric layer each comprise tungsten, molybdenum, tantalum, niobium, vanadium, chromium, titanium, zirconium, rare earth metals and alloys thereof, and non-metallic borides, carbides, nitrides, silicides, phosphides, sulfides, or a combination of any two or more of the above.
3. The method for growing a low warpage semiconductor substrate wafer of claim 1, wherein the deposition method of the first dielectric layer and the second dielectric layer comprises magnetron sputtering, electrochemical deposition, physical vapor deposition or chemical vapor deposition.
4. The method for growing a low warpage semiconductor substrate wafer of claim 1, wherein the first dielectric layer and the second dielectric layer have the same coefficient of thermal expansion and thickness, and are the same material.
5. The method for growing a low-warpage semiconductor substrate wafer as claimed in claim 1, wherein the step S3) of removing the second dielectric layer comprises a wet or dry etching process of plasma etching or chemical reagent etching, the polishing and cleaning process comprises mechanical grinding, chemical mechanical polishing CMP, cleaning to remove organic and inorganic impurities on the front surface of the substrate wafer, and the removal and polishing and cleaning processes are performed to obtain a flat, smooth and clean front surface of the substrate wafer.
6. The method for growing a low warpage semiconductor substrate wafer as claimed in claim 1, wherein the step S5) of removing the first dielectric layer comprises a wet or dry etching process of plasma etching or chemical reagent etching, the polishing cleaning process comprises mechanical grinding and chemical mechanical polishing CMP, the upper surface of the substrate wafer is protected by waxing during the polishing process, and cleaning is performed after the polishing process to remove organic and inorganic impurities on the surface and the back surface of the substrate wafer.
7. The method as claimed in claim 1, wherein the reaction gas source for epitaxial growth in step S4) is methane, trichlorosilane, nitrogen, the carrier gas is hydrogen, the flow rate is 80scl-100scl, the growth temperature is 1000-.
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