JP2005079134A - Semiconductor substrate and its producing process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate suitable for fabricating a low breakdown voltage power discrete element requiring a low resistivity substrate in which generation of misfit dislocation can be suppressed on the surface of the substrate, and to provide its producing process. <P>SOLUTION: An epitaxial wafer is produced by a step for forming a heavily doped impurity diffusion layer containing impurities at a concentration higher than that of a lightly doped substrate by diffusing phosphorus and antimony to the surface of the lightly doped substrate, a step for mirror finishing the surface for forming the heavily doped impurity diffusion layer, and a step for forming an epitaxial layer containing impurities at a concentration lower than that of the heavily doped impurity diffusion layer on the mirror finished surface of the heavily doped impurity diffusion layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor substrate and a manufacturing method thereof, and more particularly to a semiconductor substrate suitably used for power discrete element manufacturing and a manufacturing method thereof.

  Epitaxial growth technology is used to form a single crystal layer that serves as an operating region for power discrete elements such as LSI integrated circuits and IGBTs (insulated gate bipolar transistors). This technique is an important technique that can form a steep impurity profile even at a junction where the dopant concentration difference is large.

  As an apparatus used for the epitaxial growth as described above, a vertical type and a barrel type are generally used. In these apparatuses, an epitaxial layer is grown on the substrate surface by heating a semiconductor single crystal substrate placed on a susceptor to a predetermined reaction temperature and thermally decomposing or hydrogen reducing the source gas. Manufacturing.

By the way, in recent years, the application field of low withstand voltage power discrete elements has been expanded as a power supply circuit for portable devices and the like, and not only the improvement of switching characteristics but also the driving time is lengthened, so the demand for a reduction in on-resistance has increased. ing.
In order to satisfy this requirement, it is necessary to increase the circuit integration and reduce the resistivity of the semiconductor substrate.

In order to reduce the substrate resistivity, it is common to increase the dopant concentration in the substrate. In a semiconductor substrate, antimony (Sb), arsenic ( As) and the like are doped.
However, since these dopants have a large evaporation amount when pulling a single crystal, there is a limit to increasing the concentration of the dope, that is, reducing the substrate resistivity.

Further, as a method for increasing the dopant concentration to reduce the substrate resistivity, for example, a method as disclosed in Patent Document 1 has been proposed.
According to this method, an element having a larger ionic radius than that of silicon (for example, phosphorus (P)) and an element having a smaller ionic radius (for example, boron (B)) are combined and combined at a specific ratio. By doing so, it is said that the dopant concentration in the silicon single crystal can be improved.
Japanese Patent Laid-Open No. 11-67768

As described above, in a semiconductor substrate for a low withstand voltage power discrete element, the reduction in substrate resistivity greatly contributes to the reduction in on-resistance.
However, when reducing the substrate resistivity when pulling up the single crystal, the amount of dopant evaporation is large and the amount of melting into the silicon melt is small, so that a dopant such as antimony or arsenic is added alone. Even so, there has been a limit to reducing the substrate resistivity.
In addition, when the single crystal is pulled, if doping is performed at a concentration close to the limit of the solid solution in order to make the dopant concentration higher, it is physically uniform in the pulling direction due to a phenomenon called segregation. It has been difficult to grow crystals with a high concentration, a single crystal having a desired resistance band cannot be obtained, yield is low, and manufacturing costs are high.

On the other hand, as described in Patent Document 1, a high concentration can be obtained by combining an element having a larger ionic radius than that of silicon (for example, phosphorus) and an element having a smaller ionic radius (for example, boron) as a dopant. It is believed that a dopant at is possible.
However, when an epitaxial layer is formed on a substrate having a high dopant concentration as described above, when a layer having a low dopant concentration is deposited and grown, the lattice constant difference (misfit) between the substrate and the epitaxial layer is large. There is a problem that misfit dislocations are highly likely to occur.

  The present invention has been made to solve the above technical problem, and is a semiconductor substrate suitable for manufacturing a low withstand voltage power discrete element that requires a substrate having a low resistivity, and has a mistake on the substrate surface. An object of the present invention is to provide a semiconductor substrate capable of suppressing the occurrence of fit dislocations and a method for manufacturing the same.

In the semiconductor substrate according to the present invention, a high-concentration impurity diffusion layer containing impurities at a concentration higher than that of the low-concentration impurity substrate formed by diffusing two kinds of elements among group 15 elements is formed on the surface of the low-concentration impurity substrate. An epitaxial layer containing impurities at a lower concentration than the high concentration impurity diffusion layer is formed on the surface of the high concentration impurity diffusion layer.
The low-concentration impurity substrate here is preferably a semiconductor substrate containing impurities that are not diffused out from the back side in a later step, and more preferably a low specific resistance of 0.5 Ω · cm or more. It is a semiconductor substrate containing a concentration of impurities.
In the semiconductor substrate, a high-concentration impurity diffusion layer in which the two kinds of dopants are diffused is formed on the low-concentration impurity substrate in order to cancel lattice distortion on the surface on which the epitaxial layer is formed. It is what.
Therefore, the semiconductor substrate according to the present invention has almost no lattice distortion on the epitaxial layer forming surface, the concentration of the diffused dopant is high, and therefore the substrate resistivity is low, and misfit dislocations are generated in the epitaxial layer. It is suppressed.

The two kinds of elements are preferably phosphorus and antimony.
In the case of an N-type semiconductor, it is preferable to use P and Sb as dopants because it is easy to adjust the ratio of the dopant concentration to cancel the lattice distortion.

The phosphorus and antimony are preferably diffused at a ratio of 3.02 ≦ N _P / N _Sb ≦ 3.74 (N _P : concentration of phosphorus, N _Sb : concentration of antimony). More preferably, it is 3.23 ≦ N _P / N _Sb ≦ 3.57, and it is particularly preferable that 3.23 ≦ N _P / N _Sb ≦ 3.40.
When the concentration ratio of both dopants is in the above range, the occurrence of misfit dislocations when the epitaxial layer is formed can be set to a standard value (10 / cm ² ) or less.

In addition, the method for manufacturing a semiconductor substrate according to the present invention includes a high concentration impurity having a higher concentration than the low concentration impurity substrate by diffusing two kinds of elements of group 15 elements on the surface of the low concentration impurity substrate. A step of forming a concentration impurity diffusion layer, a step of mirroring the surface of forming the high concentration impurity diffusion layer, and a surface of the high concentration impurity diffusion layer that is mirror-finished at a lower concentration than the high concentration impurity diffusion layer. And a step of forming an epitaxial layer containing impurities.
The mirroring here includes a chemical mechanical polishing (hereinafter simply referred to as polishing) process in which the surface state becomes a mirror surface as a final process. For example, grinding with a diamond grindstone, When etching using a mixed chemical solution of acidic chemicals such as hydrofluoric acid, nitric acid, and acetic acid is required as a pre-process, these pre-processes are also included. Similarly, the case where the plasma etching step is performed in the final step or the previous step is also included.
According to the above manufacturing method, the above-described semiconductor substrate according to the present invention suitable for forming a low withstand voltage power discrete element that requires a substrate having a low resistivity can be suitably obtained.

As described above, in the semiconductor substrate according to the present invention, since different types of dopants are diffused at a high concentration at a concentration ratio that cancels the lattice strain on the epitaxial layer forming surface, Generation of misfit dislocations is suppressed, and a low resistivity semiconductor substrate can be obtained.
Therefore, the epitaxial wafer which is a semiconductor substrate according to the present invention can be suitably used as a wafer for manufacturing a low breakdown voltage power discrete element that is required to have a low substrate resistivity. This can contribute to reduction.
Moreover, according to the manufacturing method which concerns on this invention, the above semiconductor substrates which concern on this invention can be manufactured easily and with a sufficient yield.
Further, the manufacturing method according to the present invention is not limited to the semiconductor substrate for the low-voltage power discrete element as described above, and has a high function even when a low on-resistance characteristic is required in a medium-voltage product, a rectifier element, or the like. It can be effectively used to provide an excellent semiconductor substrate as a material.

Hereinafter, a semiconductor substrate and a manufacturing method thereof according to the present invention will be described in detail with reference to some drawings.
The semiconductor substrate according to the present invention diffuses two kinds of elements of group 15 elements to the surface of the low-concentration impurity substrate in order to cancel the lattice distortion, so that a higher-concentration impurity than the low-concentration impurity substrate is present. A high-concentration impurity diffusion layer containing is formed, and an epitaxial layer containing impurities at a lower concentration than the high-concentration impurity diffusion layer is formed on the surface thereof.

  On the other hand, for example, when a single dopant is diffused without considering the cancellation of lattice distortion, misfit dislocations are generated in the epitaxial layer. These dislocations cause leakage defects and cause deterioration of transistor characteristics.

  Therefore, in the semiconductor substrate according to the present invention, by suppressing the lattice distortion in the substrate, it is possible to increase the concentration of the diffused dopant and reduce the substrate resistivity. Moreover, even when epitaxial growth is performed on the substrate, the occurrence of misfit dislocations as described above is also suppressed.

  As a combination of two kinds of dopant elements for canceling the lattice distortion, it is preferable to use two kinds of elements of Group 15, for example, combinations of P and Sb, P and As, Sb and As, and the like. However, the present invention is not limited to this. Of these, the combination of P and Sb is particularly preferable.

By the way, the stress β in the crystal at the time of high concentration dopant diffusion is expressed by the following formula (1).
β = 1/3 · {(1- (R _i / R _si ) ³ } · N _si ⁻¹ (1)
The lattice strain ε is expressed by the following formula (2).
ε = β · N _i (2)
In the above formulas (1) and (2), R _{si represents} the atomic radius of silicon, R _{i represents} the atomic radius of the dopant element, N _si represents the concentration of silicon, and N _i represents the concentration of the dopant.

Therefore, if the ε expressed by the above formula (2) matches for the two types of dopant elements to be combined, the lattice distortion is offset.
That is, the first dopant (for example, P) and the second dopant (for example, Sb) are diffused so as to have a concentration ratio N ₁ / N ₂ shown in the following formula (3), respectively.
_{N 1 / N 2 = {1-} (R 2 / R Si) 3} / {1- (R 1 / R Si) 3} ... (3)
(Where N _{1 is} the concentration of the first dopant, N _{2 is} the concentration of the second dopant, R _{1 is} the atomic radius of the first dopant, R _{2 is} the atomic radius of the second dopant, and R _{Si is} silicon. Represents the atomic radius of.

As described above, the lattice distortion is canceled based on the concentration ratio based on the above formula (3).
However, when the dopants are, for example, P and Sb (see the examples), as shown in FIG. 2, the concentration ratio derived from the above formula (3) is actually 3.02 ≦ N _P / N, as shown in FIG. It is preferable that _Sb ≦ 3.74. More preferably, it is 3.23 ≦ N _P / N _Sb ≦ 3.57, and it is particularly preferable that 3.23 ≦ N _P / N _Sb ≦ 3.40.

  As described above, in the present invention, two types of dopant elements are diffused on the surface of the low-concentration impurity substrate at a concentration ratio that cancels the lattice distortion on the surface on which the epitaxial layer is formed, so that no misfit dislocation occurs after epitaxial growth. Good crystallinity is obtained.

  In the semiconductor substrate, the depth of the high concentration impurity diffusion layer is preferably at least 5 μm or more from the surface of the diffusion layer from the viewpoint of suppressing the occurrence of misfit dislocations.

  As described above, according to the semiconductor substrate of the present invention, the on-resistance of the transistor can be reduced, and the low resistivity with excellent crystallinity in which the occurrence of misfit dislocations in the epitaxial layer is suppressed. A semiconductor substrate can be obtained.

  The semiconductor substrate as described above has a high-concentration impurity diffusion layer containing a higher concentration of impurities than the low-concentration impurity substrate by diffusing two types of group 15 elements on the surface of the low-concentration impurity substrate. A step of forming a mirror surface of the high-concentration impurity diffusion layer forming surface, and an epitaxial layer containing impurities at a lower concentration than the high-concentration impurity diffusion layer on the surface of the mirror-concentrated high-concentration impurity diffusion layer And a step of forming a layer.

FIG. 1 shows an example of a manufacturing process of a semiconductor substrate according to the present invention.
A fixed amount of P and Sb dissolved in a diffusion coating solution on one side of an N-type silicon single crystal substrate (low-concentration impurity substrate) 10 (FIG. 1 (a)) having both surfaces etched by spin coating. Application is performed to form the N ⁺ diffusion source layer 20 (FIG. 1B).
Next, the substrate is inserted into an electric furnace, a nitrogen gas is introduced into the furnace, and heat treatment is performed to form a deposition diffusion layer 21 (FIG. 1C).
Further, this substrate is heat-treated in an argon gas atmosphere containing a small amount of oxygen, and the impurities are diffused to a deeper position, thereby forming a high concentration impurity diffusion layer 22 (FIG. 1D).
Note that the thickness and resistivity of the silicon single crystal substrate 10 and the high-concentration impurity diffusion layer 22 are various in order to optimize the transistor characteristics required in device characteristic design. In general, the diffusion layer depth is The surface resistivity is preferably about 50 to 200 μm, and the surface resistivity of the diffusion layer is preferably 0.005 Ω · cm or less.

As described above, the amount of dopant at the time of diffusion is preferably 3.02 ≦ N _P / N _Sb ≦ 3.74 in the case of a combination of P and Sb from the viewpoint of suppressing the occurrence of misfit dislocations. More preferably, it is 3.23 ≦ N _P / N _Sb ≦ 3.57, and it is particularly preferable that 3.23 ≦ N _P / N _Sb ≦ 3.40.

Next, after the high concentration impurity diffusion layer 22 is formed, the applied N ⁺ diffusion source layer 20 is removed, and then mirror finishing is performed. In the mirror surface machining, machining allowance is required to remove the machining residual distortion. In general, the etching allowance is about 10 to 20 μm.
And it wash | cleans after a mirror surface process. In this cleaning process, sufficient cleanliness is ensured so that no defects are induced in the heat treatment in the subsequent process.

Next, an epitaxial layer 30 is grown on the surface of the high-concentration impurity diffusion layer 22 that has been subjected to the mirror finishing and cleaning (FIG. 1E).
The thickness and resistivity of the epitaxial layer 30 are optimized in consideration of the thickness of the entire substrate in accordance with transistor characteristics and IC processes required for device characteristic design.

In the epitaxial growth step, it is preferable to keep the substrate surface clean by a vapor phase etching process in order to suppress defects generated near the interface between the epitaxial layer 30 and the high concentration impurity diffusion layer 22.
Thereby, a substrate with fewer defects can be formed.
Then, after the epitaxial layer 30 is formed, the semiconductor substrate according to the present invention is completed by washing.
Also in this cleaning step, it is preferable to ensure a sufficient degree of cleaning so that no defects are induced in the subsequent heat treatment or the like.

EXAMPLES Hereinafter, although this invention is demonstrated more concretely based on an Example, this invention is not restrict | limited by the following Example.
[Example]
An N-type silicon single crystal substrate having a diameter of 150 mm, a thickness of 625 μm, and a substrate resistivity of 20 to 25 Ω · cm is etched on one side, and P and Sb are dissolved in a diffusion coating solution by spin coating. A fixed amount was applied to form an N ⁺ diffusion source layer.
Next, the substrate was inserted into an electric furnace at 1200 ° C., nitrogen gas was introduced into the furnace, and heat treatment was performed for 180 minutes to form a deposition diffusion layer.
Further, this substrate was heat-treated at 1290 ° C. for 100 hours in an argon gas atmosphere containing a small amount of oxygen, and the impurities were diffused to a deeper depth, thereby forming a high concentration impurity diffusion layer.
At this time, the P concentration N _{P on} the substrate surface is 7.4 · 10 ¹⁹ atoms / cm ³ , and the Sb concentration N _{Sb on the} substrate surface is N _P / N _Sb = 2.90, 3.02, 3.23. It was diffused at 7 levels so as to be 3.40, 3.57, 3.74, 3.91.
The depth of the diffusion layer was 80.0 ± 3.0 μm from the surface, and the surface resistivity of the diffusion layer was about 0.001 Ω · cm.
After forming the high-concentration impurity diffusion layer, the applied N ⁺ diffusion source layer was removed, and a mirror finish was applied to the diffusion surface side.
The machining allowance in the mirror surface processing was 20 μm.
Next, a silicon epitaxial layer to which an N-type impurity having a thickness of 7.3 μm and a specific resistance of 10 Ω · cm was added was formed on the surface of the high concentration impurity diffusion layer.
The epitaxial growth conditions at this time are as follows: SiHCl ₃ 15 g / min. , H ₂ 200 l / min. Then, H ₂ gas containing 1 ppm of PH ₃ as an impurity addition gas is introduced at a flow rate at which a desired specific resistance value is obtained, a growth temperature of 1180 ° C., an epitaxial growth rate of 0.47 μm / min. It was.

About the epitaxial wafer obtained by the above, generation | occurrence | production of the misfit dislocation accompanying the formation of an epitaxial layer was evaluated by optical microscope observation.
In the evaluation of the misfit dislocation, the number of misfit dislocations in the center 5 mm square of the substrate was measured and converted per unit area.
These results are shown in FIG.

[Comparative example]
One side of an N-type silicon single crystal substrate having a diameter of 150 mm, a thickness of 625 μm, and a substrate specific resistance of 20 to 25 Ω · cm etched on one side, a solution in which only P is dissolved in a diffusion coating solution is constant by spin coating. The N ⁺ diffusion source layer was formed by applying a large amount. Other than that, the epitaxial wafer was produced like the Example.
When the obtained epitaxial wafer was evaluated for misfit dislocations in the same manner as in the example, the number of misfit dislocations generated was 3640 / cm ² .

As shown in FIG. 2, in the case where P and Sb are diffused as dopants (Example), the number of misfit dislocations generated is drastically reduced compared to the case where only P is diffused (Comparative Example). It was acknowledged.
Further, in the range of 3.02 ≦ N _P / N _Sb ≦ 3.74, it was confirmed that the number of misfit dislocations was 10 standard / cm ² or less, which is the standard value.

  In the above description, the case of an N-type silicon single crystal substrate has been mainly described. However, the present invention can also be applied to a case of a P-type silicon single crystal substrate.

It is sectional drawing which showed typically the manufacturing process of the silicon single crystal substrate which concerns on this invention. Is a diagram showing the relationship between the N _P / N _Sb and generating the number of misfit dislocations in the embodiment.

Explanation of symbols

10 N-type silicon single crystal substrate (low concentration impurity substrate)
20 N ⁺ diffusion source layer 21 Depot diffusion layer 21 High-concentration impurity diffusion layer 30 Epitaxial layer

Claims (6)

  On the surface of the low concentration impurity substrate, a high concentration impurity diffusion layer containing a higher concentration impurity than the low concentration impurity substrate in which two kinds of elements of Group 15 elements are diffused is formed, and the high concentration impurity diffusion layer An epitaxial layer containing impurities at a lower concentration than the high concentration impurity diffusion layer is formed on the surface of the semiconductor substrate.   2. The semiconductor substrate according to claim 1, wherein the two kinds of elements are phosphorus and antimony. 3. The phosphorus and antimony are diffused at a ratio of 3.02 ≦ N _P / N _Sb ≦ 3.74 (N _P : concentration of phosphorus, N _Sb : concentration of antimony). Semiconductor substrate. A step of diffusing two kinds of group 15 elements on the surface of the low-concentration impurity substrate to form a high-concentration impurity diffusion layer containing impurities at a concentration higher than that of the low-concentration impurity substrate;
Mirroring the high concentration impurity diffusion layer forming surface;
And a step of forming an epitaxial layer containing impurities at a lower concentration than the high-concentration impurity diffusion layer on the surface of the mirror-concentrated high-concentration impurity diffusion layer. .   5. The method of manufacturing a semiconductor substrate according to claim 4, wherein the two kinds of elements are phosphorus and antimony. 6. The phosphorus and antimony are diffused at a ratio of 3.02 ≦ N _P / N _Sb ≦ 3.74 (N _P : concentration of phosphorus, N _Sb : concentration of antimony). A method for manufacturing a semiconductor substrate.

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