JP6432879B2 - Epitaxial wafer manufacturing method - Google Patents

Description

The present invention also relates to the production how of the epitaxial wafer.

  For example, an epitaxial wafer is used for a semiconductor device having a MOS (Metal Oxide Semiconductor) structure used for a standby power supply (mobile power supply) used by connecting to a mobile terminal. From the viewpoint of power saving in recent years, it is required to make the resistivity of a substrate used for such an epitaxial wafer extremely low.

  When growing a silicon single crystal ingot having a very low resistivity, for example, an n-type substrate (silicon single crystal substrate), a high concentration of phosphorus having a low volatility among n-type dopant species as a dopant. Added. By adjusting the added phosphorus, the resistivity of the silicon substrate obtained from the silicon single crystal ingot is adjusted. For example, when an epitaxial layer is grown on a silicon substrate having a resistivity of 0.8 mΩ · cm or less by adjusting the added phosphorus, stacking faults (stacking faults) are likely to occur during the growth of the epitaxial layer. When a semiconductor device is manufactured using an epitaxial wafer in which such a stacking fault has occurred, the characteristics of the semiconductor device are adversely affected. Therefore, it is necessary to control the quality of the epitaxial wafer so that the number of stacking faults generated in the epitaxial wafer used for the semiconductor device is a certain number or less.

  For example, Patent Document 1 discloses a method of suppressing stacking faults that occur when an epitaxial layer is grown on a silicon single crystal substrate to which phosphorus is added at a high concentration. However, in the invention described in Patent Document 1, it is necessary to form a polysilicon layer on the back surface of the silicon single crystal substrate in order to suppress stacking faults.

  Further, Patent Document 2 discloses an epitaxial wafer in which an epitaxial layer is grown on a silicon single crystal substrate to which phosphorus is added at a high concentration.

JP 2011-9613 A JP 2011-187651 A

  However, the invention described in Patent Document 2 prevents misfit dislocations by adjusting the layer thickness of an epitaxial layer grown on a silicon single crystal substrate to which phosphorus and germanium are added.

An object of the present invention is to provide a manufacturing how an epitaxial wafer that can suppress the stacking faults caused in growing a phosphorous only epitaxial layer the added resistivity 0.8mΩ · cm or less in the silicon single crystal substrate is there.

Means for Solving the Problems and Effects of the Invention

The method for producing an epitaxial wafer of the present invention includes:
A step of growing a silicon single crystal ingot having a resistivity of 0.8 mΩ · cm or less to which only a phosphorus is added as a dopant at a pulling rate of 0.5 mm / min or less;
Growing an epitaxial layer on the surface of the silicon single crystal substrate cut out from the silicon single crystal ingot;
It is characterized by providing.

  The epitaxial wafer manufacturing method of the present invention grows an epitaxial layer on a silicon single crystal substrate cut out from the ingot grown in the above-described growing step, and therefore can suppress stacking faults that occur during epitaxial growth.

  When the pulling rate in the growing step is 0.4 mm / min or less, stacking faults that occur when growing an epitaxial layer on a silicon single crystal substrate can be effectively suppressed. The lower limit of the pulling rate in the growing step is preferably, for example, 0.35 mm / min or more from the viewpoint of productivity.

The graph which showed the relationship between the pulling speed of a silicon single crystal ingot, and the number of the stacking faults formed in the surface of the epitaxial wafer which made the epitaxial layer grow on the board | substrate cut out from the ingot corresponding to the pulling speed.

  Hereinafter, as an example of an epitaxial wafer manufacturing method of the present invention, a manufacturing method for manufacturing a silicon epitaxial wafer by growing a silicon epitaxial layer on a silicon single crystal substrate (hereinafter referred to as “substrate W”) will be described. In this embodiment, a known pulling apparatus that grows a silicon single crystal ingot that is a base of the substrate W and a known vapor phase growth apparatus that performs epitaxial growth on the substrate W cut out from the ingot grown by the pulling apparatus are used.

  First, a silicon single crystal ingot that is a base of the substrate W is manufactured using a known pulling apparatus. The lifting device has, for example, a quartz crucible. First, when polycrystalline silicon and a dopant (only phosphorus) for adjusting the resistivity are put into the quartz crucible and melted, the melt is stored in the quartz crucible. Then, a seed crystal silicon rod is immersed in the liquid surface of the stored melt, and the seed crystal silicon rod is pulled up at a pulling speed of 0.35 mm / min to 0.5 mm / mm to produce a silicon single crystal ingot. .

  Next, after cutting the produced silicon single crystal ingot to a predetermined thickness, the cut wafer is subjected to rough polishing, etching, polishing, etc., and the surface is mirror-finished (polished wafer state) W is produced. The substrate W is adjusted so that the resistivity becomes 0.8 mΩ · cm or less by phosphorus added when the silicon single crystal ingot is manufactured.

  The manufactured substrate W is transferred to a known vapor phase growth apparatus and subjected to epitaxial growth. When the substrate W is transferred into the furnace of the vapor phase growth apparatus, the furnace is subjected to a heat treatment at 1100 to 1140 ° C. for about 60 seconds, for example, in an atmosphere containing hydrogen and hydrochloric acid. Then, an epitaxial layer is grown on the substrate W, for example, by 4 μm in the same temperature zone as in the heat treatment, and a silicon epitaxial wafer is manufactured.

In the epitaxial wafer manufactured as described above, a silicon epitaxial layer is formed on a silicon single crystal substrate having a resistivity of 0.8 mΩ · cm or less in which only phosphorus is added as a dopant. In general, the resistivity is grown an epitaxial layer on a silicon substrate became less 0.8mΩ · cm, stacking faults are easily generated in the growth of the epitaxial layer, stacking faults LPD on the surface of the epitaxial wafer (Light Observed as Point Defect) .

  However, the embodiment of the present invention suppresses stacking faults that occur when an epitaxial layer is grown on the substrate W because the silicon single crystal ingot that is the base of the substrate W is grown at a pulling rate of 0.5 mm / min or less. it can. When the LDP on the surface of the epitaxial wafer manufactured according to the embodiment of the present invention is measured by, for example, a defect inspection apparatus, the number of LDP per wafer is 1000 or less (preferably 100 or less, more preferably 10). The following can be suppressed. Therefore, a high quality epitaxial wafer can be provided.

  EXAMPLES Hereinafter, although an Example and a comparative example are given and this invention is demonstrated concretely, these do not limit this invention.

  First, a plurality of silicon single crystal ingots were prepared by adding only phosphorus as a dopant. Specifically, four silicon single crystal ingot pulling speeds are selected from a range of 0.35 to 0.62 mm / min, silicon single crystal ingots are grown at the selected pulling speeds, and ingots having different pulling speeds are selected. Four were produced. A wafer having a diameter of 200 mm and a plane orientation (100) was cut out from each ingot produced, and the cut wafer was subjected to rough polishing, etching, polishing, etc., and one substrate W was produced from each ingot. The produced substrate W was adjusted to have the same resistivity (0.75 to 0.78 mΩ · cm). Then, each of the produced substrates W was transferred into a furnace of a known vapor phase growth apparatus, and the atmosphere in the furnace was changed to an atmosphere containing hydrogen and hydrochloric acid at 1100 to 1140 ° C. and subjected to heat treatment for about 60 seconds. Thereafter, an N-type silicon epitaxial layer having a thickness of 4 μm was grown on the substrate W at the same temperature range as that during the heat treatment, so that four silicon epitaxial wafers were produced. And it obtained by counting the number of the stacking faults (LPD) which arose on the surface of the produced wafer on the image of a defect inspection apparatus (MAGICS by Lasertec).

(Comparative example)
In the comparative example, the number of stacking faults on the surface of the epitaxial wafer on which the epitaxial layer was grown on the substrate W cut out from the ingot having a pulling rate of 0.62 mm / min was measured.

(Example)
In the first example, the number of stacking faults on the surface of an epitaxial wafer on which an epitaxial layer was grown on a substrate W cut out from an ingot having a pulling rate of 0.35 mm / min was measured. In the remaining two examples, a pulling speed in the range of 0.4 to 0.5 mm / min was selected as a pulling speed in the vicinity of 0.4 mm / min and a pulling speed in the vicinity of 0.5 mm / min. Then, the number of stacking faults on the surface of the epitaxial wafer on which the epitaxial layer was grown on each substrate W cut out from the ingot grown at each pulling speed was measured.

  FIG. 1 shows the number of stacking faults generated on the surfaces of the silicon epitaxial wafers produced in the comparative example and the example, and the pulling speed of the silicon single crystal ingot that is the basis of the substrate W of the produced epitaxial wafer. In the comparative example in which the pulling speed exceeds 0.6 mm / min, the number of stacking faults is well over 1000, whereas in the example in which the pulling speed is 0.5 mm / min or less, the number of stacking faults is large. Decreased. In particular, when the pulling speed was 0.4 mm / min or less, the number of stacking faults was 10 or less, and the number of stacking faults could be effectively suppressed.

  The embodiments of the present invention have been described above. However, the present invention is not limited to the specific description, and the illustrated configurations and the like can be appropriately combined within a technically consistent range. In addition, certain elements and processes may be replaced with known forms.

  W substrate (silicon single crystal substrate)

Claims (2)

A step of growing a silicon single crystal ingot having a resistivity of 0.8 mΩ · cm or less in which only a phosphorus is added as a dopant at a pulling rate of 0.4 mm / min or less;
A step of growing an epitaxial layer on the surface of the silicon single crystal substrate cut out from the silicon single crystal ingot having a pulling rate of 0.4 mm / min or less ;
Equipped with a,
The number of LPD produced in the said epitaxial layer grown in the said process to grow is 10 or less, The manufacturing method of the epitaxial wafer characterized by the above-mentioned . The silicon single crystal substrate cut out from the silicon single crystal ingot further includes a step of performing heat treatment at 1100 to 1140 ° C. in an atmosphere containing hydrogen and hydrochloric acid,
2. The method for producing an epitaxial wafer according to claim 1, wherein in the growing step, the epitaxial layer is grown on the silicon single crystal substrate after the heat treatment in the same temperature zone as the heat treatment .

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