CN108511317B - Method for manufacturing epitaxial wafer and epitaxial wafer - Google Patents

Method for manufacturing epitaxial wafer and epitaxial wafer Download PDF

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CN108511317B
CN108511317B CN201710113141.8A CN201710113141A CN108511317B CN 108511317 B CN108511317 B CN 108511317B CN 201710113141 A CN201710113141 A CN 201710113141A CN 108511317 B CN108511317 B CN 108511317B
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silicon
single crystal
atoms
wafer
epitaxial wafer
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CN108511317A (en
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浅山英一
宝来正隆
村上浩纪
久保高行
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Sumco Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Abstract

The invention provides a method for producing a semiconductor device which can exhibit gettering ability due to crystal defects and has a defect density on the surface of an epitaxial layerIs 102Per cm2The following method for manufacturing an epitaxial wafer. The method for manufacturing an epitaxial wafer is characterized by comprising the following steps: a single crystal silicon growth step of growing a silicon single crystal doped with 10 by Czochralski method11atoms/cm3~4.5×1015atoms/cm3The nitrogen single crystal silicon of (1); a single crystal silicon cutting step of cutting a silicon wafer from the single crystal silicon; and an epitaxial layer forming step of forming an epitaxial layer, which is a single crystal silicon layer, on the substrate by vapor phase growth using the silicon wafer as a substrate, wherein the epitaxial layer is formed in a range of 1050 ℃ to 1200 ℃.

Description

Method for manufacturing epitaxial wafer and epitaxial wafer
Technical Field
The present invention relates to a method for manufacturing an epitaxial wafer, which is a high-quality wafer having a low surface defect density, and an epitaxial wafer.
Background
With the popularization of portable communication terminals including smart phones and the like, the integration density of integrated circuit elements (power supply devices) of silicon semiconductors has been increasing year by year, and the requirements for the quality of silicon wafers forming the power supply devices have become more and more stringent. That is, as the integrated circuit becomes finer and finer, in a so-called power device active region where a power device is formed from a wafer, crystal defects such as displacement, which cause an increase in leakage current and a reduction in the lifetime of carriers, and impurities of metal-based elements other than dopants are more strictly limited than in the past.
Conventionally, a substrate (wafer) cut from a silicon single crystal by a CZ method (czochralski single crystal pulling method) using a power device has been used. The wafer generally includes 1018atoms/cm3Left and right oxygen. It is known that oxygen has an effective effect of improving wafer strength and gettering by preventing displacement, but on the other hand, oxygen precipitates as an oxide and causes crystal defects such as displacement and stacking faults due to a thermal history in forming a power supply device. However, in the process of manufacturing the power supply device, LOCOS (local oxidation of silicon) is passed through the field oxide filmn) forming and forming the well diffusion layer, the wafer surface is kept at a high temperature of 1100 to 1200 ℃ for several hours, so that a DZ layer (denuded zone) having a thickness of about several tens of μm is formed near the wafer surface due to oxygen out-diffusion. The DZ layer becomes an active region of the power device, and thus naturally causes a state with fewer crystal defects.
However, as integration density increases, a high-energy ion implantation method is used for well formation, and when the power supply device is manufactured at 1000 ℃ or lower and processed, oxygen diffusion becomes slow, and thus the DZ layer cannot be formed sufficiently. Therefore, although the low oxidation of the substrate is promoted, the crystal defects cannot be sufficiently suppressed, and the performance of the wafer is deteriorated due to the reduction of oxygen, and satisfactory results cannot be obtained. Therefore, epitaxial wafers in which an epitaxial layer of Si containing almost no crystal defects is grown on a silicon wafer serving as a wafer substrate have been developed and widely used for highly integrated power supply devices.
In this way, the use of the epitaxial wafer can improve the possibility of completely eliminating the crystal defects in the active region of the power device on the wafer surface. However, as integration becomes more dense, the process becomes more complicated, the chance of contamination by impurities of metal-based elements increases, and the influence thereof becomes larger. The countermeasures for eliminating contamination are basically based on cleaning of the process environment and the materials used, but complete elimination is difficult in the process of manufacturing the power device, and gettering is known as a countermeasure. This is a method for making the impurity elements, which have entered through contamination, gather in a place outside the active region of the power device and thereby make the impurity elements harmless.
The metal-based impurity element enters and is dissolved in the Si crystal at a relatively low temperature, and the diffusion rate of the metal-based impurity element into Si is generally high. Further, if there are crystal defects such as displacement and distortion due to fine precipitates, the crystal is more stable in energy than when present in the crystal lattice, and therefore the metal-based impurity element tends to aggregate in the defects of the crystal. Therefore, by utilizing this property, crystal defects are intentionally introduced, and the metallic impurity elements can be trapped and blocked therefrom. The place where the impurity is to be captured is calledIs a slot. The method of forming the grooves includes both external gettering and internal gettering. External gettering by sand blasting, grinding, laser irradiation, ion implantation or Si3N4External factors such as growth of a film and a polycrystalline Si film impart distortion to the back surface side of the surface of the power supply device forming the wafer and introduce crystal defects. In contrast, in intrinsic gettering, when a heat treatment at a low temperature and a high temperature is repeatedly performed on a wafer made of a CZ method single crystal containing oxygen, many minute defects possibly caused by oxygen are generated, and the defects are used as grooves.
However, in the case of external gettering, there are problems as follows: the cost increases with the increase in the number of steps, and particles appear from the portion to which distortion is applied, and the wafer warps due to the processing. On the other hand, intrinsic gettering needs to contain oxygen to some extent, but this may cause defects that are detrimental to the formation of power supply devices. Furthermore, a heat treatment for efficiently manufacturing the grooves is required, which also increases the workload. In the case of epitaxial wafers, the temperature is increased to 1050 to 1200 ℃ in the step of forming an epitaxial layer, so that oxide precipitates which are nuclei of minute defects in the wafer substrate are reduced and eliminated, and it is difficult to form grooves in the wafer substrate by a subsequent heat treatment. Therefore, the conventional intrinsic gettering method cannot be effectively utilized.
Disclosure of Invention
The present invention relates to a method for manufacturing an epitaxial wafer for a high-density integrated power supply device and an epitaxial wafer, and an object of the present invention is to provide a method for manufacturing an epitaxial wafer and an epitaxial wafer, which are capable of manufacturing an epitaxial wafer that exhibits sufficient gettering capability in a short process.
Among the fine defects of the crystal caused by oxygen, there are Oxidation-induced stacking faults (hereinafter, abbreviated as "OSF"). This is a stacking fault generated in the base crystal of the oxide film when high-temperature oxidation treatment is performed in the power device manufacturing process, the generation of OSF has a positive correlation with the amount of oxygen in the Si crystal, and this defect causes oxygen precipitates to develop into nuclei. When a wafer of a Si single crystal produced by the CZ method is subjected to thermal oxidation treatment at 1000 to 1200 ℃ for 1 to 20 hours, an annular OSF (hereinafter referred to as "OSF ring") centered on the pulling axis of the single crystal is generated. It is understood that when an epitaxial layer of Si is formed on a substrate including an OSF ring, oxygen precipitate nuclei in the ring region do not disappear, and function as effective gettering sites in the power device manufacturing process after epitaxial formation.
Generally, the width of the OSF ring is several mm to several tens mm, and the boundary with other regions is extremely clear. Further, when the pulling rate is increased, the diameter of the ring becomes larger and approaches the outer periphery of the wafer, and when the pulling rate is decreased, the ring shrinks and disappears.
The present inventors have focused on the gettering effect due to the crystal defects in the OSF ring region, and have made various studies on conditions for enlarging the width of the ring. As a result, it was found that the width of the ring can be increased by doping nitrogen when single crystal growth is performed by the CZ method.
And, in addition to the OSF defect, one of the surface defects of the silicon wafer is cop (crystal aligned particle). The COP defects are octahedral void defects having a size of about 0.1 μm or less, which are generated in a single crystal due to aggregation of voids. SiO is formed on the inner surface of COP defect2
The present inventors have also focused on the gettering effect due to COP defects, and have made various studies on conditions for generating COP defects of an appropriate size and density. As a result, it was found that when single crystal growth is performed by the CZ method, a COP region in which vacancies predominate during pulling in accordance with imparting sufficient gettering ability can be formed by doping nitrogen and appropriately adjusting the pulling rate.
Conventionally, as an effect of doping nitrogen into a single crystal by the CZ method, there have been known crystal strengthening (jp 7-76151 a), suppression of displacement and movement of displacement caused by thermal stress (jp 60-251190 a), suppression of generation of etch pits generated in a wafer, prevention of deterioration of the withstand voltage of an oxide film of a power device (jp 5-294780 a), and the like. However, as for the effect on gettering, the effect on the shape of the OSF ring and the effect on the formed COP region are not known at all.
Therefore, the temperature of the molten metal is controlled,the conditions under which the width of the OSF ring was increased and the crystal defects generated thereby were uniformly generated on the entire wafer were investigated, and the effectiveness of the gettering effect was also investigated. As a result, it was found that the amount of doped nitrogen was 1013atoms/cm3As described above, the nuclei of OSFs effective for gettering can be uniformly dispersed throughout the crystal, and when a Si epitaxial layer is formed on the surface of a sliced piece obtained from the single crystal as a substrate, a wafer having few surface defects and an effective gettering effect in the power device manufacturing process can be manufactured.
Also, it is known that even if the amount of doped nitrogen is set to 1011atoms/cm3To 4.5X 1015atoms/cm3Similarly, if the pulling rate of the single crystal, the heat treatment conditions of the silicon wafer, and the like are controlled more precisely, a wafer having few surface defects and an effective gettering effect in the power device manufacturing process can be manufactured.
The gettering method is effective particularly for a p-, n-, or n + power device wafer in which precipitation nuclei formed by groove formation are easily eliminated, and is a p + wafer doped with boron at a high concentration (for example, 10 added with boron) in which boron is doped and Fe is gettered by boron19cm-3The above (wafer of 9m Ω cm or less), the present invention is also effective for elements other than Fe. Since the gettering effect of Fe and Cu elements due to high boron concentration is strong in a p + wafer doped with high boron concentration, it is considered that the effect cannot be clearly distinguished from the effect due to the gettering method disclosed in the present invention, but the present gettering effect of Fe and Cu at least also exists.
In the present invention, the concentration of boron (B) is P + type, which means a concentration having a resistivity of 5 m.OMEGA.cm to 100 m.OMEGA.cm, P type or P-type, which means a concentration having a resistivity of 0.1 to 100. OMEGA.cm, the concentration of phosphorus (P) or antimony (Sb) is n-type, which means a concentration having a resistivity of 0.1 to 100. OMEGA.cm, and n + is a concentration having a resistivity of 10 to 100 m.OMEGA.cm. Also, for example, p/p-type refers to a wafer having a p-type epitaxial layer stacked over a p-type substrate. The gettering method is suitable for a method for manufacturing an epitaxial wafer of n/n-, n/n + structure, and is also effective for a method for manufacturing an epitaxial wafer of p/p + structure having a substrate specific resistance of 8 to 100m Ω cm.
Further, this gettering method is effective not only when a conventional silicon wafer having a diameter of 150mm is used as a substrate, but also when a silicon wafer having a diameter of 200mm to 450mm (for example, a diameter of 200mm, 300mm, or 450mm) is used as a substrate, without causing warpage or the like in the epitaxial wafer to be manufactured.
The gettering effect of the wafer on which the epitaxial layer was formed was evaluated by the generation lifetime of MOS. As a result of further detailed investigation of the wafers having excellent effects obtained by doping nitrogen in this manner, it was found that 10 was generated on the surface after the thermal oxidation treatment2Per cm2The above OSF is generated by 10 pieces/cm2The above COP (in the case of COP, the oxidation heat treatment is not necessarily performed). That is, in the case of OSF, it is considered that there are defect nuclei in which OSF is generated to some extent or more by thermal oxidation treatment in a single crystal state, which brings about an excellent gettering effect. In the case of COP, it is considered that, although the strain field generated by COP alone is small, in the state of a nitrogen-doped single crystal, there are voids of a silicon lattice in which COP is generated to some extent or more, which brings about an excellent gettering effect.
The epitaxial layer is preferably formed by heating the wafer at 1000 ℃ or higher in a hydrogen atmosphere. More preferably in the range of 1050 to 1200 ℃. Thus, for the secondary doping with 1013atoms/cm3The wafer obtained by slicing the nitrogen single crystal was subjected to a heat treatment of 1100 ℃ or higher as in the case of the formation of an epitaxial layer, and as a result, a cross section of 5X 10 was observed3/cm2The above drawbacks. Such defects function as gettering grooves, improve the gettering effect of the wafer, and are obtained by defect nuclei in the single crystal generated by doping nitrogen.
Also, a pre-annealing treatment may be performed before the epitaxial layer is formed.
The invention of the present application has the following modes.
(1) A method for manufacturing an epitaxial wafer which can exhibit gettering capability due to crystal defects and has a defect density of 10 in the surface of the epitaxial layer2Per cm2The method for manufacturing an epitaxial wafer is characterized by comprising: single crystalA silicon growth step of growing a silicon single crystal doped with 10 by Czochralski method11atoms/cm3~4.5×1015atoms/cm3The nitrogen single crystal silicon of (1); a single crystal silicon cutting step of cutting a silicon wafer from the single crystal silicon; and an epitaxial layer forming step of forming an epitaxial layer, which is a single crystal silicon layer, on the substrate by vapor phase growth using the silicon wafer as a substrate, wherein the epitaxial layer is formed in a range of 1050 ℃ to 1200 ℃.
(2) The method for producing an epitaxial wafer according to item (1), wherein an amount of nitrogen doped into the silicon single crystal grown in the silicon single crystal growing step is 1013atoms/cm3~4.5×1015atoms/cm3The method for manufacturing an epitaxial wafer further includes a step of performing thermal oxidation treatment on the silicon wafer at 700 to 1200 ℃ for 30 minutes to 20 hours, the crystal defects are oxidation-induced stacking faults formed by oxidizing interstitial silicon introduced into the single crystal silicon by the thermal oxidation treatment, and the density of the oxidation-induced stacking faults on the substrate is 10 in the entire substrate2Per cm2The above.
(3) The method for producing an epitaxial wafer according to item (2), wherein the single-crystal silicon is further doped with 0.01 × 10 impurities in the single-crystal silicon growth step16atoms/cm3~5×1016atoms/cm3Carbon (c) of (a).
(4) The method for producing an epitaxial wafer according to the above (2) or (3), wherein the monocrystalline silicon has an oxygen concentration of 2X 1017atoms/cm3~15×1017atoms/cm3Within the range of (1).
(5) The method for producing an epitaxial wafer according to item (1), wherein an amount of nitrogen doped into the silicon single crystal grown in the silicon single crystal growing step is 1011atoms/cm3~1013atoms/cm3The crystal defects are silicon crystal-induced surface defects (COP defects) caused by voids introduced into the silicon single crystal, and the density of the COP defects on the substrate is 1 in the entire substrate0 pieces/cm2The above.
(6) The method for producing an epitaxial wafer according to item (5), wherein the single-crystal silicon is further doped with 0.01 × 1016atoms/cm3~5×1016atoms/cm3Carbon (c) of (a).
(7) The method for producing an epitaxial wafer according to the above (5) or (6), wherein the monocrystalline silicon has an oxygen concentration of 11X 1017atoms/cm3~13.5×1017atoms/cm3Within the range of (1).
(8) An epitaxial wafer produced by the method for producing an epitaxial wafer according to any one of (1) to (7), wherein the epitaxial wafer has a diameter of 200mm to 450 mm.
(9) The epitaxial wafer according to item (8) above, wherein the epitaxial wafer has a diameter of 300mm to 450 mm.
Effects of the invention
According to the present invention, a single crystal silicon which is a base material for an epitaxial wafer having defect nuclei that are not easily lost in a high-temperature processing step such as epitaxial layer formation can be obtained without an external or internal gettering effect increasing process that increases the number of steps and costs, and a high-density integrated epitaxial wafer for a power supply device having no defects in a power supply device active region and having an extremely high gettering effect can be obtained by producing the single crystal silicon using the single crystal.
Drawings
Fig. 1 is a graph showing the change in the density profile in the wafer of the OSF with an increase in the amount of nitrogen doping.
Fig. 2 is a graph showing that the distribution of the OSF density in the single crystal axis direction becomes uniform as the amount of nitrogen doping increases.
Fig. 3 is a diagram showing the distribution of crystal defects on the surface and inside (cross section) of the obtained epitaxial wafer.
Fig. 4 is a graph corresponding to a temperature change law in a power device manufacturing process used for evaluating gettering capability of a wafer.
Fig. 5 is a graph showing the results of measuring the change in the manufacturing process due to the existence period by wafers having different amounts of nitrogen doping.
Detailed Description
When gettering ability due to OSF defects is imparted to an epitaxial wafer, the nitrogen doping amount of the single crystal silicon is set to 1013atoms/cm3This is because if the amount of nitrogen is less than the above amount, the width of the OSF ring is not sufficiently widened, and uniform dispersion in the wafer in the gettering sink is not achieved. The upper limit of the doping amount is not particularly limited, and if it is too large, the crystal tends to be polycrystalline, so that it is preferably 4.5 × 1015atoms/cm3Left and right.
When the gettering capability due to COP defects is provided to the epitaxial wafer, the nitrogen doping amount of the monocrystalline silicon is set to 1011atoms/cm3Above 1013atoms/cm3If the range is outside this range, defects do not occur on the epitaxial surface even if voids of the silicon lattice exist in the single crystal silicon, and sufficient COP defects cannot be formed as sites effective for gettering.
As a method of doping, any method may be used as long as it can dope nitrogen at a desired concentration, and examples thereof include mixing nitride in a raw material or a melt, mixing an FZ silicon crystal to which nitrogen is added and a wafer having a silicon nitride film formed on the surface thereof into a raw material, growing a single crystal while introducing nitrogen or a nitrogen compound gas into a furnace, blowing nitrogen or a nitrogen compound gas into polycrystalline silicon at a high temperature before melting, and using a crucible made of nitride.
In addition to nitrogen, the single crystal silicon can be doped with carbon, boron, and/or phosphorus as needed. By doping these carbon, boron and/or phosphorus, it is possible to adjust the specific resistivity of the obtained silicon wafer substrate, or further enhance the gettering ability, for example.
The preferred range for carbon doping is 1.0X 1014atoms/cm3~1.0×1016atoms/cm3More preferably, the amount of the surfactant is less than 1X 1014atoms/cm3above-1X 1015atoms/cm3Trace amounts of carbon. Carbon measurement methods include SIMS and GFA, and PL or DLTS based on trace carbonA method.
The preferred range of boron doping is 3X 1017atoms/cm3~1×1019atoms/cm3(8.9 m.OMEGA.cm to 93 m.OMEGA.cm in specific resistance in accordance with ASTM).
The preferred range of phosphorus doping is 4X 1014atoms/cm3~5×1015atoms/cm3(0.98. omega. cm to 10.9. omega. cm in specific resistance in terms of ASTM).
The oxygen concentration of the silicon single crystal and the oxygen concentration of the silicon wafer cut from the silicon single crystal (old ASTM specification: 1979) are 11X 1017atoms/cm3~13.5×1017atoms/cm3Within the range of (1).
The wafer is produced by cutting the single crystal doped with nitrogen, polishing and cleaning the surface, and then forming an epitaxial layer, but any method may be used as long as it is a method of forming an epitaxial layer free from crystal defects, such as a thermal decomposition method of a vapor phase growth method. Thus at 1011atoms/cm3~4.5×1015atoms/cm3By doping nitrogen in the range of (1) and setting other conditions according to the type of crystal defects to be finally introduced, stable defects to be gettering sinks can be uniformly dispersed over the entire wafer. The number of such defects is affected by the amount of oxygen and other impurities or the growth conditions of the single crystal. In the epitaxial wafer, since a power device activation region can be secured in the epitaxial layer, it is necessary to secure a sufficient defect density in the wafer substrate. From such a viewpoint, it is found that, as a result of examining the number of defects, in order to obtain a more stable gettering effect, it is preferable to use a method in which, when the gettering capability due to OSF defects is provided, 10 is generated on the surface, for example, in the case of performing thermal oxidation treatment2Per cm2Wafers of the above OSF. In the case of imparting gettering ability due to COP defects, use is made of, for example, 10 pieces/cm at the surface2More than and less than 1 × 105Per cm2Wafer of COPs of (1).
For surface inspection of silicon wafers, for example, surfscan SP1, SP2, and SP3 manufactured by KLA Tencor corporation can be used. When the number of crystal defects on the surface of the substrate is measured, at least one crystal defect having a size of 130nm to 65nm is measured. In addition, when the number of crystal defects on the surface of the epitaxial layer was measured, the number of crystal defects having a size of 130nm or more was 1.
For example, when the number of OSF defects is counted, it is observed that after the epitaxial layer is grown and heat treatment at 1100 ℃ or higher is preferably performed, 5X 103Per cm2The above defect is sufficient.
As another method of detecting the number of defects, a wafer cross section can be observed after the epitaxial layer is formed. Examples of the method of observing the cross section after epitaxial growth include a method of performing selective etching on OSF to 1 μm to 5 μm and then counting defects, and a defect measuring method performed by crystal defect inspection apparatuses MO441 and MO601 manufactured by RAYTEX CORPORATION in COP.
In the method for manufacturing an epitaxial wafer according to the present invention, it is preferable that the silicon wafer is epitaxially grown on a wafer-by-wafer basis in a single wafer furnace, and it is further preferable that the temperature is increased and decreased at a high speed in the process of the epitaxial growth. Specifically, the temperature increase rate from 900 to the growth temperature is set to 450 degrees/minute or more, and the temperature decrease rate from the epitaxial growth temperature to 900 degrees is set to 800 degrees/minute or more, whereby a plurality of precipitation nuclei can be left on the substrate (wafer). The method may further include a low-temperature heat treatment step in the power supply device step, which is performed at a temperature ranging from 700 ℃ to 900 ℃ for 20 minutes to 1 hour before the epitaxial growth step. Alternatively, the method may further include a high-temperature heat treatment step of performing the epitaxial growth at a temperature ranging from 1000 ℃ to 1150 ℃ for 60 minutes or longer.
The epitaxial layer is preferably epitaxially grown to a thickness of 1 to 20 μm, and more preferably a relatively thin epitaxial layer of 1 to 6 μm.
[ examples ]
[ example 1 ]
The following 2 experiments were performed in order to examine the effect of nitrogen doping. The conditions for growing a single crystal were such that 50kg of high-purity polycrystalline silicon was melted in a quartz crucible, boron was used as a dopant, and the pulling rate of the single crystal with a diameter of 150mm and a crystal orientation of < 100 > was set to 0.6 mm/min.
First, in order to highlight the effect of nitrogen addition, in the first step, nitrogen gas flow was discharged into the furnace at 10L/min at a stage where the single crystal was grown to 300mm at the lower right, and growth was continued in this state, and nitrogen in the single crystal was increased. Then, in order to estimate the nitrogen doping amount, a silicon wafer with a definite nitrogen amount for forming a nitride film was melted together with high-purity polysilicon as a raw material without adding nitrogen in a gaseous state during the pulling process, thereby growing a silicon wafer with a nitrogen doping amount of 1012、1013Or 1014atoms/cm3Respectively 3 different single crystals of (2).
A test piece in the form of a wafer was cut out of the grown single crystal in parallel with the plane perpendicular to the crystal axis, and subjected to thermal oxidation treatment at 1100 ℃ for 16 hours in an oxygen atmosphere. Thereafter, selective etching was performed for 5 minutes using a photo-etching solution, and the OSF density was measured using an optical microscope.
Fig. 1 shows the results of an investigation of the distribution of OSF density in the test piece plane at the test piece cut position of a single crystal in which the doping amount was changed by introducing nitrogen gas. This figure shows the density distribution of the OSF on a line drawn from the center to the outer periphery of the single crystal, and the OSF is generally in a substantially annular shape coaxial with the central axis of the single crystal. The nitrogen gas was not introduced into the test piece at the lower right 100mm position, and the amount of nitrogen doping was gradually increased as the lower right position reached 400mm to 700 mm. Accordingly, it is found that when the nitrogen doping amount is increased, the width of the OSF ring is increased, the OSF is distributed over the entire test piece, and the density level is also increased.
The results of measuring the OSF density of a test piece in which a single crystal to be grown by changing the level of nitrogen doping amount was sampled along the crystal growth axis are shown in fig. 2. In this case, the vertical axis represents the average value of the OSF density measured at the center of the test piece and at positions spaced 10mm apart from the center in the outer circumferential direction of the test piece. From this, it can be seen that if the nitrogen doping amount of the single crystal is 1012atoms/cm3Growth in time, resulting in a decrease in OSF density, even if reduced to 1013atoms/cm3Also, a relatively high OSF density of 10 was maintained14atoms/cm3A uniform and higher OSF density is also achieved in the axial direction. And is 1014atoms/cm3When the single crystal is used, OSF is uniformly distributed over the entire test pieceAnd (3) a body.
[ example 2 ]
In example 1, for the secondary doping with 1014atoms/cm3The wafer obtained from the single crystal of nitrogen of (1) formed an epitaxial layer having a thickness of about 5 μm at a deposition temperature of 1150 ℃. The obtained wafer test piece was selectively etched with a photo-etching solution for 5 minutes, and the defect density of the epitaxial layer surface and the defect density of the cross section were measured with an optical microscope.
Fig. 3 shows the measurement results of the density of defects on the surface and the cross section at the position from the center of the test piece in the outer circumferential direction. From this, it is understood that 10 a cross section of the single crystal of the lower layer has been observed after the epitaxial layer is formed on the wafer made of the single crystal doped with nitrogen4Per cm2The left and right defects confirmed that the oxide precipitates were not easily disappeared when the high-temperature epitaxial layer was formed. Further, it was confirmed that no defect was observed on the surface of the epitaxial layer and the cross section of the epitaxial layer, and no penetration of a defect of the lower single crystal portion occurred in the epitaxial layer which becomes the active region of the power device.
[ example 3 ]
Respectively manufacturing a single crystal undoped with nitrogen and doped with 10 Ω cm or 10.008 Ω cm of resistivity, and a high-resistance or low-resistance p-type wafer substrate12、1013Or 1014atoms/cm3A wafer substrate was cut out of each of 8 kinds of single crystals of nitrogen, and an epitaxial layer having a thickness of 5 μm was formed at a deposition temperature of 1150 ℃ to obtain an epitaxial wafer.
Cu (NO) at 3ppm3)2After the surfaces of these wafers were contaminated with an aqueous solution by using a spin coater, a pattern heat treatment assumed in the power device manufacturing process was performed in dry oxygen, and changes in gettering effects accompanying the progress of the heat treatment were examined.
Fig. 4 shows temperature and time conditions of the mode heat treatment. In the step shown in the figure, the wafer was taken out at 3 points shown as A, B, C, and the gettering effect accompanying the progress of the heat treatment was observed. The gettering effect was evaluated by removing the thermal oxide film with hydrofluoric acid, oxidizing the film at 1000 ℃ for 2 hours in a dry oxygen atmosphere to form a gettering oxide film of about 75nm, depositing an Al film of 500nm thickness by evaporation, and then sintering the film at 450 ℃ for 30 minutes to produce a gate electrode having an angle of 1mm with respect to the gate electrode, and measuring the generation lifetime of MOS using the electrode.
The results of the determination of the lifetime are shown in fig. 5. A wafer made of a nitrogen-undoped single crystal is not sufficient, but the lifetime of generation immediately after the formation of an epitaxial layer is short, and gradually becomes longer as the heat treatment progresses. And is made of a material doped with 1013Or 1014atoms/cm3The wafer produced from the nitrogen single crystal according to (1) can have a substantially constant long lifetime from the start to the end of the power device production process. The doping amount is 1012atoms/cm3In the case of (b), a tendency similar to that in the case of undoped is shown. And 1013atoms/cm3Then, as shown in FIG. 2 of example 1, the OSF density and the nitrogen doping amount 1014atoms/cm3Is relatively low, despite the fact that the gettering capability is roughly equivalent to 1014atoms/cm3The case (1). The reason is presumed to be that if the nitrogen doping amount is 1013atoms/cm3As described above, a sufficient groove for gettering is formed. Further, it is considered that the difference between the gettering effects of p/p and p/p + is not so large, and therefore the gettering capability of the epitaxial wafer obtained by the nitrogen-doped single crystal does not greatly depend on the resistivity of the wafer, and a sufficient gettering effect can be obtained at least when the resistivity is 10 Ω cm to 0.008 Ω cm.
[ example 4 ]
In example 4, the amount of nitrogen doped into the single crystal silicon was set to 1012atoms/cm3Setting the oxygen concentration at 12X 1017atoms/cm3(ASTM1979) the silicon wafer type was set to p + type, and the pulling rate of the single crystal silicon was set to 2 times that of example 1, to produce an epitaxial wafer.
As a result, the density of COP defects in the substrate as the obtained single crystal silicon wafer was 10 cm over the entire substrate surface2The above.
Furthermore, the lifetime of MOS generation was measured in the same manner as in examples 1 to 3, and the gettering ability was evaluated.
As a result, in example 4 as well, similarly to the cases of examples 1 to 3, a substantially constant long lifetime was obtained from the start to the end of the power device manufacturing process.
Industrial applicability
An epitaxial wafer which can sufficiently exhibit intrinsic gettering capability due to crystal defects can be efficiently manufactured in a short process.

Claims (8)

1. A method for manufacturing an epitaxial wafer capable of exhibiting gettering capability due to crystal defects and having a defect density of 10 in the surface of the epitaxial layer2Per cm2The method for manufacturing an epitaxial wafer is characterized by comprising:
a single crystal silicon growth step of growing a silicon single crystal doped with 10 by Czochralski method11atoms/cm3~4.5×1015atoms/cm3The nitrogen single crystal silicon of (1);
a single crystal silicon cutting step of cutting a silicon wafer from the single crystal silicon; and
an epitaxial layer forming step of forming an epitaxial layer, which is a single crystal silicon layer, on the substrate by vapor phase growth using the silicon wafer as a substrate,
in the epitaxial layer forming step, the epitaxial layer is formed in a range of 1050 ℃ to 1200 ℃,
the amount of nitrogen doped in the silicon single crystal grown in the silicon single crystal growing step is 1011atoms/cm3~1013atoms/cm3
The crystal defect is a COP defect which is a silicon crystal-induced surface defect caused by a void introduced into the single-crystal silicon,
the density of COP defects on the substrate was 10/cm in the entire substrate2The above.
2. The method of manufacturing an epitaxial wafer according to claim 1,
doped in the monomerThe amount of nitrogen in the silicon single crystal grown in the silicon crystal growth step is 1013atoms/cm3~4.5×1015atoms/cm3
The method for manufacturing an epitaxial wafer further comprises a step of performing thermal oxidation treatment on the silicon wafer at 700-1200 ℃ for 30 minutes-20 hours,
the crystal defects are oxidation-induced stacking faults formed by oxidizing the interstitial silicon introduced into the single crystal silicon by the thermal oxidation treatment,
the density of the oxidation-induced stacking faults on the substrate was 10 in the entire substrate2Per cm2The above.
3. The method of manufacturing an epitaxial wafer according to claim 2,
in the step of growing the silicon single crystal, the silicon single crystal is further doped with 0.01 × 1016atoms/cm3~5×1016atoms/cm3Carbon (c) of (a).
4. Method for manufacturing an epitaxial wafer according to claim 2 or 3,
the oxygen concentration of the monocrystalline silicon is 2 x 1017atoms/cm3~15×1017atoms/cm3Within the range of (1).
5. The method of manufacturing an epitaxial wafer according to claim 1,
in the step of growing the silicon single crystal, the silicon single crystal is further doped with 0.01 × 1016atoms/cm3~5×1016atoms/cm3Carbon (c) of (a).
6. Method for manufacturing an epitaxial wafer according to claim 1 or 5,
the oxygen concentration of the single crystal silicon is 11 x 1017atoms/cm3~13.5×1017atoms/cm3Within the range of (1).
7. An epitaxial wafer manufactured by the method for manufacturing an epitaxial wafer according to any one of claims 1 to 6, characterized in that the diameter of the epitaxial wafer is 200mm to 450 mm.
8. The epitaxial wafer of claim 7,
the diameter of the epitaxial wafer is 300 mm-450 mm.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11189493A (en) * 1997-12-25 1999-07-13 Sumitomo Metal Ind Ltd Silicon single crystal and epitaxial wafer
CN1545725A (en) * 2001-08-23 2004-11-10 信越半导体株式会社 Epitaxial wafer and a method for producing it
JP2007235153A (en) * 2002-04-26 2007-09-13 Sumco Corp High-resistance silicon wafer, and manufacturing method thereof
JP2011222842A (en) * 2010-04-13 2011-11-04 Shin Etsu Handotai Co Ltd Manufacturing method for epitaxial wafer, epitaxial wafer, and manufacturing method for imaging device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11189493A (en) * 1997-12-25 1999-07-13 Sumitomo Metal Ind Ltd Silicon single crystal and epitaxial wafer
CN1545725A (en) * 2001-08-23 2004-11-10 信越半导体株式会社 Epitaxial wafer and a method for producing it
JP2007235153A (en) * 2002-04-26 2007-09-13 Sumco Corp High-resistance silicon wafer, and manufacturing method thereof
JP2011222842A (en) * 2010-04-13 2011-11-04 Shin Etsu Handotai Co Ltd Manufacturing method for epitaxial wafer, epitaxial wafer, and manufacturing method for imaging device

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