Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
  • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
  • H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure

Definitions

• the present invention relates generally to silicon and silicon germanium based semiconductor transistor devices, and more specifically, to a device design including a grown epitaxial field effect transistor structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter- wave and millimeter- wave.
• the epitaxial field effect transistor structure includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve f max in excess of 200GHz.
• SiGe MODFETs when compared to RF bulk Si CMOS device, SiGe MODFETs still have lower noise characteristics, and higher maximum oscillation frequency (f ma ⁇ )- Consequently, Si/SiGe MODFETs are becoming more and more attractive devices for high speed, low noise, and low power communication applications, where low cost and compatibility with CMOS logic technology are required and often essential. Recently, n-channel MODFETs with long channel lengths ranging from 0.2 ⁇ m to 0.5 ⁇ m have demonstrated encouraging device performances.
• a Si/SiGe MODFET device have an undoped, tensile strained silicon (nFET) or a compressively strained SiGe (pFET) quantum well channels whereby the induced strain is used to increase the carrier mobility in the channel, in addition to providing carrier confinement.
• the synergistic addition of modulation doping further improves the carrier mobility in the channel by reducing the ionized impurity scattering from the dopants and further reducing the surface roughness scattering in a buried channel.
• Record high room temperature' mobilities of 2800 cm 2 /Vs have been achieved for electron mobilities in a tensile strained silicon channel grown on a relaxed Sio. 7 Ge 0.3 buffer.
• FIG. 6 illustrates a graph 200 of the Phosphorus (P) doping profile for a Gl (generation) layer structure and the steady- state P doping 201 problem and transient P doping problems 202 associated with the Phosphorus doping in a CVD growth system.
• P Phosphorus
• the invention is directed to a high-electron-mobility n-channel MODFET device that is properly scaled and constructed on a thin SGOI/SOI substrate that exhibits greatly improved RF performance.
• the present invention is directed to a MODFET device and method of manufacture that addresses the prior art limitations and achieves vertical scaling of the nMODFET layer structure and the source/drain junction and lateral scaling of the device structure to unprecedented degrees, resulting in a device exhibiting ultra-high speed performance (i.e. f ⁇ ⁇ f max > 300GHz) with acceptable voltage gain and good turn-off characteristics.
• the MODFET device is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, such that the body is fully depleted. Due to the suppressed short channel effects, the output conductance (gd) may be thus be reduced.
• SGOI ultra-thin SiGe-on-insulator
• the DC voltage gain (gm/gd), the linearity and f max is significantly improved.
• the provision of ultra-thin SiGe buffer layers also reduces the self-heating due to the low thermal conductivity of SiGe, which reduces the drive current.
• a fully-depleted SGOI MODFET exhibits better noise figures and lower soft error rate.
• the epitaxial field effect transistor structure of the invention includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve f max of > 300GHz.
• the invention further is directed to a high-hole-mobility p-channel MODFET that is properly scaled and constructed on a thin SGOI/SOI substrate will also have very high RF performance.
• Figures 1(a)- 1(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structure on thin SGOI substrate (G1-G4) properly scaled in accordance with the invention;
• Figure 1 (f) illustrates a Si/SiGe p-type MODFET structure on thin SGOI substrate; i [0017]
• Figure 2 illustrates a graph providing simulated I d -V gs curves for the devices in
• Figure 3 depicts the simulated Id-Vd S curves for a G4 device of Figures 1(a)- 1(f);
• Figure 4 depicts the simulated gm-V gs curves for a G4 device of Figures 1(a)- 1(f);
• Figure 5 depicts the simulated r and f max vs. V gs curves for a G4 device of Figures l(a)-l(f);
• Figure 6 depicts a SIMS profile of the Phosphorus (P) doping profile for a Gl
• Figure 7 illustrates a graph 160 depicting the steady-state P concentration vs. growth
• Figure 8 depicts the method for calibrating growth rate reduction 170 for a SiGe (Ge content of 30%) according to the invention
• Figure 9 illustrates an example plot indicating the steady state P concentration as a function of reduced growth rate
• Figure 10 is a graph illustrating the profile of transient P incorporation as a function of reduced growth rates
• Figure 11 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G2 layer structure
• Figure 12 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G3 layer structure
• Figure 13 depicts a XTEM for the Gl layer structure on bulk corresponding to the SIMS profiles shown in Figure 6;
• Figure 14 depicts a XTEM for a G2 layer structure on bulk corresponding to the SIMS profiles shown in Figure 11;
• Figure 15 depicts a XTEM for a G3 layer structure on a SGOI substrate with thin re- growth
• Figure 16 depicts a XTEM for a G2 layer structure on a SGOI substrate.
• Figures l(a)-l(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structures on thin SiGe-on-Insulator (SGOI) substrate (generation G1-G4 devices) properly scaled in accordance with the invention.
• Figure 1(f) illustrates a Si/SiGe p- type MODFET structure on thin SGOI substrate properly scaled in accordance with the invention.
• Figure 1(a) particularly depicts a MODFET device according to a first embodiment.
• a top doped nMODFET device 10 comprising a Si substrate layer 5, a buried dielectric layer 8 formed on top of the substrate 5 which may range up to 200 nm in thickness and comprise an oxide, nitride, oxynitride of silicon; and a channel region 25 formed between n+ -type doped source and drain regions 11, 12 respectively, and a gate structure 20 including a gate dielectric layer 22 separating the gate conductor 18 from the channel 25.
• the gate dielectric layer may comprise an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations. It is important to realize that according to the invention, the dimensions of the device including drain, source, gate and channel regions have been scaled.
• the composition of the channel region 25 of device 10 in Figure 1(a) is as follows: A relaxed SiGe layer 30 having a p-type dopant is provided on a buried dielectric layer 8 having Ge content ranging between 30 - 50% and ranging in thickness between 20 nm -30 nm.
• the p-type doping concentration ranges between lel4 cm “ - 5el7cm " using one of: ion implantation or in- situ doping.
• the relaxed SiGe layer may be predoped to a concentration level of lei 4 cm "3 - 5el7 cm “3 .
• the relaxed SiGe layer and other layers comprising the channel 25 is grown according to a UHVCVD technique, however other techniques such as MBE, RTCVD, LPCVD processes may be employed.
• a five percent (5%) SiGe seed layer 31 (Sio. 95 Geo.o 5 ) is then epitaxially grown on top of the relaxed SiGe layer 30 and an intrinsic Si 1-x Ge x regrown buffer layer 32 is formed on top of the formed SiGe seed layer 31.
• the thickness of epitaxially grown SiGe seed layer ranges from 0 nm - 5nm and the thickness of the intrinsic SiGe regrown buffer layer 32 ranges between 20nm - 30nm and having Ge content "x" ranging between 10%- 40%.
• An epitaxial tensile strained Si layer 33 is then grown on top of the SiGe buffer layer 32 and ranges in thickness between 5 nm - 7 nm.
• An epitaxial Si 1-y Ge y spacer layer 34 is then formed on top of the strained Si layer and ranging in thickness between 3 nm - 5nm and having Ge content "y" ranging between 30 - 40%>.
• an epitaxial Si ⁇ -z Ge z supply layer 35 is grown on top of the spacer layer ranging in thickness between 2 mn - 8nm and having a n-type doping concentration ranging between 2el 8cm " - 5el9cm " and having Ge content "z” ranging between 35 - 50%.
• the Si ⁇ -z Ge z supply layer may be grown in a temperature range between 425° C - 550°C and in-situ doped using phosphine gas as a dopant precursor singly or in a mixture including one or more elements including but not limited to: H2, He, Ne, Ar, Kr, Xe, N 2 .
• the flow rate of the phosphine gas dopant precursor is a linear ramp or a graded profile such that said in-situ doping is performed without disrupting an epitaxial growth process. It is understood that a precursor such as AsH 3 or SbH 3 may be used as well.
• a small amount of carbon may be incoiporated during the epitaxial growth of the SiGe supply layer 34, e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably about 1 - 1.5%.
• an epitaxial tensile strained Si cap layer 36 is grown on top of the supply layer 35 ranging in thickness between Onm - 3nm and having a n-type doping concentration ranging between 5el7 cm " - 5el9cm " .
• the gate dielectric layer 22 is formed on top of the strained Si cap layer and is having an equivalent oxide thickness in a range of 0-1 nm.
• the gate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of the gate dielectric layer 22 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30nm-100nm.
• the formed drain region 12 has an n-type doping concentration greater than 5el9cm "3 ; and the formed source region 11 has a n-type doping concentration greater than 5el9cm "3 .
• the distance between the gate conductor 18 and either drain or source region ranges from about 20nm - lOOnm.
• the device may further comprise a passivation layer surrounding the gate electrode 20, the passivation layer having a permittivity ranging between 1-4.
• the depth of the quantum well, d QW of the formed nMODFET includes the spacer layer of intrinsic SiGe 34, the layer of n+ -type doped SiGe 35 and the layer of n+ - type doped Si cap layer 36 totaling approximately 10 nm in depth according to the dimensions depicted in Figure 1(a).
• Figure 1 (a) depicts a high-electron-mobility device 40 that is identical to the top-doped nMODFET of Figure 1(a), however, does not include the seed layer.
• Figure 1 (c) illustrates a second embodiment of the invention drawn to a high-electron-mobility nMODFET device 50 that is bottom doped.
• the device 50 includes a Si substrate layer 5, a buried dielectric layer 8 formed on top of the substrate 5 comprising an oxide, nitride, oxynitride of silicon, for example, and a channel region 55 formed between n+ -type doped source and drain regions 11, 12 respectively, and a gate structure 20.
• the channel structure 55 includes a relaxed SiGe layer 60 on insulator 8 ranging in thickness between 10 nm and 50nm, an epitaxial Sio .95 Ge 0.
• o 5 seed layer 61 grown on top of the SiGe layer 60 and ranging in thickness between 0 nm - 5nm; an epitaxial Si ⁇ -z Ge z supply layer 62 grown on top of the seed layer ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm "3 - 5el9cm "3 ; an epitaxial Si ⁇ -y Ge y spacer layer 63 grown on top of the supply layer and ranging in thickness between 3 nm - 5nm; and, an epitaxial tensile strained Si channel layer 64 grown on top of the spacer layer and ranging in thickness between 3 nm - 10 nm; an epitaxial Si ⁇ _ y Ge y spacer layer 65 grown on top of the strained Si layer and ranging in thickness between 1 nm - 2 nm; and, an epitaxial tensile strained Si cap layer 66 grown on top of the spacer layer ranging in thickness
• a small amount of carbon may be incorporated during the epitaxial growth of the SiGe supply layer 61, e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably' about 1 - 1.5%.
• the SiGe supply layer 61 e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably' about 1 - 1.5%.
• all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition of the gate conductor metal and gate dielectric are the same as in the first embodiment ( Figure 1(a)).
• the depth of the quantum well, d Q of the formed nMODFET includes the layer of n+ -type doped Si cap layer 66 totaling a depth of approximately 2 nm.
• the seed layer may be omitted.
• a resulting structure is a high-electron-mobility device that is identical to the bottom-doped nMODFET of Figure 1(c), however, does not include the seed layer.
• an SGOI substrate comprises: a relaxed SiGe layer on insulator having Ge content ranging between 30 - 40% and ranging in thickness between 20 nm -30 nm; an epitaxial Si ⁇ -z Ge z supply layer grown on top of the relaxed SiGe layer ranging in thickness between 2.5 nm - 8nm and having a n-type doping concentration "z" ranging between 2el8 cm “3 - 2el9cm "3 and having Ge content ranging between 35 - 50%; an epitaxial Si ⁇ -y Ge y spacer layer grown on top of the supply layer and ranging in thickness between 3 nm - 5nm and having Ge content "y" ranging between 30 - 40%; an epitaxial tensile strained Si channel layer grown on top of the spacer layer ranging in thickness between 5 nm - 7 nm and having a doping concentration less than lei 6cm "3 ; an epitaxial Si ⁇ -y Ge y spacer layer grown on
• Figure 1 (d) illustrates a third embodiment of the invention drawn to a high-electron- mobility nMODFET device 70 that is bottom doped and including a doped transferred layer.
• the device 70 includes an SGOI substrate comprising a Si ⁇ -z Ge z supply layer 71 ranging in thickness between 2 nm - 8nm and having a n-type doping concentration ranging between lei 8 cm " - 5el9cm " by ion implantation or in-situ doping; an epitaxial Si ⁇ -y Ge y spacer layer 72 grown on top of the supply layer and ranging in thickness between 3 nm - 5nm; an epitaxial tensile strained Si channel layer 73 grown on top of spacer layer 72 and ranging in thickness between 3 nm - 10 nm; an epitaxial Si ⁇ -y Gey spacer layer 74 grown on top of the strained Si layer 73 and ranging in thickness between 1 nm
• the Si ⁇ -z Ge z supply layer may be predoped to a concentration level of Iel8-5el9 atoms/cm3 before a layer transfer in forming the SGOI substrate.
• all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition and thicknesses of the gate conductor metal and gate dielectric are as depicted in the first embodiment ( Figure 1(a)).
• the depth of the quantum well, dow of the formed nMODFET includes the layer of n+ -type doped Si cap layer 75 and spacer layer 74 having a depth of less than approximately 4 nm.
• Figure 1 (e) illustrates a fourth embodiment of the invention drawn to a high-electron- mobility nMODFET device 80 that is both bottom and top doped and including a SiGe regrown buffer layer.
• the nMODFET device 80 includes an SGOI substrate having: a relaxed SiGe layer 81 on insulator 8 ranging in thickness between 10 nm -50nm, having a n-type doping concentration ranging between lei 7cm " - 5el9cm " and a Ge content ranging between 30-50%; a Si ⁇ -x Ge x regrown buffer layer 82 grown on top of the SiGe layer 81 and ranging in thickness between lOnm - 50nm and serving as a bottom spacer layer and including a Ge content "x" ranging between 10% -35%; an epitaxial tensile strained Si layer 83 grown on top of the regrown buffer layer and ranging in thickness between 3 nm - 10
• the depth of the quantum well, dow of the formed nMODFET includes the layer of n+ -type doped Si cap layer 86, the epitaxial Si ⁇ -z Ge z supply layer 85, and spacer layer 84 for a depth totaling less than or equal to approximately 16 nm.
• Figure 1 (f) illustrates a fifth embodiment of the invention drawn to a high-hole- mobility MODFET device 80 that is bottom doped and including a doped transferred layer.
• the pMODFET device 90 includes an SGOI (SiGe layer 91 on insulator 8) substrate having: a relaxed epitaxial Sii- j G ⁇ j supply layer ranging in thickness between 5 nm -25 nm, and having ion-implanted or in-situ p-type doping of a concentration ranging between lei 8- 5el9cm "3 and serving as a supply layer.
• SGOI SiGe layer 91 on insulator 8
• the relaxed Sii- j G ⁇ j layer may be predoped p-type to a concentration level of Iel8-5el9 boron atoms/cm3 before a layer transfer in forming the SGOI substrate; an epitaxial Sii.
• the Sii. j Ge j supply layer 91 includes a Ge content "j" ranging between 30-70%.
• the Sii- Ge spacer layer 92 includes a Ge content "k” ranging between 30-70% and, the Si ⁇ -m Ge m channel layer 93 includes a Ge content "m” ranging between 60-100% and the strained Si ⁇ -n Ge n cap layer 94 includes a Ge content n ranging between 0% - 30%.
• a gate dielectric layer 95 is formed on top of the strained SiGe cap layer 94 and is having an equivalent oxide thickness in a range of 0-1 nm.
• the gate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of the gate dielectric layer 95 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30nm- lOOnm.
• a formed drain region 97 has a p-type doping concentration greater than 5el9cm "3 ; and the formed source region 96 has a p-type doping concentration greater than 5el9cm "3 .
• the distance between the gate conductor 18 and either drain or source region ranges from about 20rrm - lOOnm.
• the device may further comprise a passivation layer surrounding the gate electrode 20, the passivation layer having a permittivity ranging between 1- 4.
• the depth of the quantum well, dow of the formed pMODFET 90 includes the SiGe cap layer 94 with a range from approximately between 2nm - 1 Onm.
• Completed devices comprising embodiments depicted in Figures 1(a)- 1(e) having the different layer structures and design were grown by UHVCVD under growth temperature conditions ranging between 400-600 °C, and preferably in a range of 500-550 °C and in a pressure ranging from 1 mTorr - 20 mTorr.
• Figure 17 shows the performance (measured fx vs. V gs ) curves 100 with the device scaling (i.e., for Gl and G2 devices).
• the device has to be further scaled, both in the horizontal and vertical dimensions as in the G2 example shown in Figure 17.
• Figures 2-5 depict simulated device characteristics for the properly scaled devices of Figures 1(a)- 1(f).
• Figure 3 depicts the simulated I d -V s curves 110 for the G4 device of Figure 1 and
• Figure 5 there is depicted the simulated fx and f max vs.
• FIG. 7 illustrates a graph 160 depicting the steady-state P concentration 161 vs. growth rate in a UHVCVD 162 system.
• the transient incorporation for P doping depicted by curves 165 is controlled by the Ge content 167 in a SiGe film.
• the steady state P concentration is controlled by the associated growth rate of the SiGe film.
• the key process for achieving the abruptness of P profile is to use high Ge content but at a reduced growth rate, which is difficult since it is well known that high Ge is associated with enhanced or high growth rate.
• the growth rate calibration 170 for a SiGe (Ge content of 30%) is shown in Figure 8, for example, with a Ge concentration profile exhibiting successively smaller peaks 171, 172 as shown in the figure.
• the enhanced steady- state P concentration 175 is shown in Figure 9 as a function of reduced SiGe growth rate depicted as curve 174.
• the transient P incorporation rate is also increased as shown by the profile curve 178 in Figure 10.
• FIG. 15 particularly depicts the XTEM for a G3 layer structure on a SGOI substrate with a transferred SiGe layer of 50nm, where the regrown SiGe on transferred SiGe is thick (e.g., about 134.1nm) in order to minimize the effects of carbon and oxygen at the regrowth interface.
• the regrown SiGe layer is thick (e.g., about 134.1nm) in order to minimize the effects of carbon and oxygen at the regrowth interface.
• MODFETs on thin SGOI one task is to make the regrown SiGe layer as thin as possible.
• a growth process has been developed using a 5% SiGe seed layer as described in the herein incorporated co-pending U.S. Patent Application 10/389,145.
• Figure 16 depicts a XTEM for a G2 layer structure on a SGOI substrate with a thin regrown SiGe layer (e.g., about 19.7nm) on a SGOI substrate with a 73nm thick transferred SiGe layer. It is advantageous to begin with a thin SGOI substrate which can be formed by a wafer bonding and thinning process as described in co-pending U.S. Patent Application 10/389,145.

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