US20050045905A1 - Ultra high-speed si/sige modulation-doped field effect transistors on ultra thin soi/sgoi substrate - Google Patents
Ultra high-speed si/sige modulation-doped field effect transistors on ultra thin soi/sgoi substrate Download PDFInfo
- Publication number
- US20050045905A1 US20050045905A1 US10/652,400 US65240003A US2005045905A1 US 20050045905 A1 US20050045905 A1 US 20050045905A1 US 65240003 A US65240003 A US 65240003A US 2005045905 A1 US2005045905 A1 US 2005045905A1
- Authority
- US
- United States
- Prior art keywords
- layer
- ranging
- mobility
- electron
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 119
- 239000000758 substrate Substances 0.000 title claims abstract description 52
- 230000005669 field effect Effects 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 125000006850 spacer group Chemical group 0.000 claims description 68
- 239000004020 conductor Substances 0.000 claims description 34
- 229910006990 Si1-xGex Inorganic materials 0.000 claims description 26
- 229910007020 Si1−xGex Inorganic materials 0.000 claims description 26
- 239000012212 insulator Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 238000002161 passivation Methods 0.000 claims description 14
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 11
- 239000002019 doping agent Substances 0.000 claims description 10
- 238000011065 in-situ storage Methods 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 229910052741 iridium Inorganic materials 0.000 claims description 7
- 229910052763 palladium Inorganic materials 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 230000001052 transient effect Effects 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 7
- 229910003811 SiGeC Inorganic materials 0.000 claims description 6
- 229910052735 hafnium Inorganic materials 0.000 claims description 6
- 238000010348 incorporation Methods 0.000 claims description 6
- 229910052746 lanthanum Inorganic materials 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 6
- 239000002243 precursor Substances 0.000 claims description 6
- 150000004760 silicates Chemical class 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- 229910052727 yttrium Inorganic materials 0.000 claims description 6
- 229910052726 zirconium Inorganic materials 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000012546 transfer Methods 0.000 claims description 4
- 229910000074 antimony hydride Inorganic materials 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 2
- 229910000070 arsenic hydride Inorganic materials 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052734 helium Inorganic materials 0.000 claims description 2
- 229910052743 krypton Inorganic materials 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 2
- 229910052754 neon Inorganic materials 0.000 claims description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims description 2
- OUULRIDHGPHMNQ-UHFFFAOYSA-N stibane Chemical compound [SbH3] OUULRIDHGPHMNQ-UHFFFAOYSA-N 0.000 claims description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 2
- 238000013461 design Methods 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 abstract description 5
- 238000004891 communication Methods 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 9
- 239000011574 phosphorus Substances 0.000 description 9
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 9
- 230000037230 mobility Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012552 review Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000003917 TEM image Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Definitions
- the present invention relates generally to silicon and silicon germanium based semiconductor transistor devices, and more specifically, to a device design including a grown epitaxial field effect transistor structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave.
- the epitaxial field effect transistor structure includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve f max in excess of 200 GHz.
- Si/SiGe MODFETs are becoming more and more attractive devices for high speed, low noise, and low power communication applications, where low cost and compatibility with CMOS logic technology are required and often essential.
- n-channel MODFETs with long channel lengths ranging from 0.2 ⁇ m to 0.5 ⁇ m have demonstrated encouraging device performances.
- a Si/SiGe MODFET device have an undoped, tensile strained silicon (NFET) or a compressively strained SiGe (PFET) quantum well channels whereby the induced strain is used to increase the carrier mobility in the channel, in addition to providing carrier confinement.
- the synergistic addition of modulation doping further improves the carrier mobility in the channel by reducing the ionized impurity scattering from the dopants and further reducing the surface roughness scattering in a buried channel.
- Record high room temperature mobilities of 2800 cm 2 /Vs have been achieved for electron mobilities in a tensile strained silicon channel grown on a relaxed Si 0.7 Ge 0.3 buffer.
- the MODFET has to be scaled properly, both in the vertical dimensions and the horizontal (or lateral) dimensions.
- the scaling of MODFETs is even more challenging than for CMOS scaling due to the following: 1) the horizontal scaling brings the source and drain closer, and, like the case in the CMOS, short-channel effects and bulk punchthrough become the major hurdles preventing the lateral scaling; and, 2) the vertical scaling of the layer structure turns out to be crucial.
- the lateral scaling alone cannot keep the scaling of the performance.
- FIG. 6 illustrates a graph 200 of the Phosphorus (P) doping profile for a G 1 (generation) layer structure and the steady-state P doping 201 problem and transient P doping problems 202 associated with the Phosphorus doping in a CVD growth system.
- P Phosphorus
- a scaled MODFET device structure that is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, wherein the MODFET device structure exhibits ultra-high speed device performance (e.g., f T , f max >300 GHz) with better noise figures, acceptable voltage gain and good turn-off characteristics.
- SGOI SiGe-on-insulator
- the invention is directed to a high-electron-mobility n-channel MODFET device that is properly scaled and constructed on a thin SGOI/SOI substrate that exhibits greatly improved RF performance.
- the present invention is directed to a MODFET device and method of manufacture that addresses the prior art limitations and achieves vertical scaling of the nMODFET layer structure and the source/drain junction and lateral scaling of the device structure to unprecedented degrees, resulting in a device exhibiting ultra-high speed performance (i.e. f T , f max >300 GHz) with acceptable voltage gain and good turn-off characteristics.
- the MODFET device is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, such that the body is fully depleted. Due to the suppressed short channel effects, the output conductance (gd) may be thus be reduced. Therefore, the DC voltage gain (gm/gd), the linearity and f max is significantly improved.
- the provision of ultra-thin SiGe buffer layers also reduces the self-heating due to the low thermal conductivity of SiGe, which reduces the drive current. Compared to a bulk MODFET, a fully-depleted SGOI MODFET exhibits better noise figures and lower soft error rate.
- the epitaxial field effect transistor structure of the invention includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve f max of >300 GHz.
- a small amount of carbon may be incorporated during the epitaxial growth of the SiGe supply layer in the manner as described in commonly-owned, co-pending U.S. patent application Ser. No. 09/838,892 (Docket YOR920010308US1) entitled “Epitaxial and Polycrystalline Growth of Si 1 ⁇ x ⁇ y Ge x C y and S 1 ⁇ y C y Alloy Layers on Si by UHV-CVD”, the contents and disclosure of which is incorporated by reference as if fully set forth herein.
- the invention further is directed to a high-hole-mobility p-channel MODFET that is properly scaled and constructed on a thin SGOI/SOI substrate will also have very high RF performance.
- FIGS. 1 ( a )- 1 ( e ) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structure on thin SGOI substrate (G1-G4) properly scaled in accordance with the invention;
- FIG. 1 ( f ) illustrates a Si/SiGe p-type MODFET structure on thin SGOI substrate
- FIG. 3 depicts the simulated I d V ds curves for a G 4 device of FIGS. 1 ( a )-i( f );
- FIG. 4 depicts the simulated gm-V gs curves for a G 4 device of FIGS. 1 ( a )- 1 ( f );
- FIG. 5 depicts the simulated f t and f max vs. V gs curves for a G 4 device of FIGS. 1 ( a )- 1 ( f );
- FIG. 6 depicts a SIMS profile of the Phosphorus (P) doping profile for a G 1 (generation) layer structure and the steady-state and transient P doping exhibited in a G 1 layer structure;
- FIG. 7 illustrates a graph 160 depicting the steady-state P concentration vs. growth UHV CVD system according to the invention
- FIG. 8 depicts the method for calibrating growth rate reduction 170 for a SiGe (Ge content of 30%) according to the invention
- FIG. 9 illustrates an example plot indicating the steady state P concentration as a function of reduced growth rate
- FIG. 10 is a graph illustrating the profile of transient P incorporation as a function of reduced growth rates
- FIG. 11 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G 2 layer structure
- FIG. 12 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G 3 layer structure
- FIG. 13 depicts a XTEM for the G 1 layer structure on bulk corresponding to the SIMS profiles shown in FIG. 6 ;
- FIG. 14 depicts a XTEM for a G 2 layer structure on bulk corresponding to the SIMS profiles shown in FIG. 11 ;
- FIG. 15 depicts a XTEM for a G 3 layer structure on a SGOI substrate with thin re-growth
- FIG. 16 depicts a XTEM for a G 2 layer structure on a SGOI substrate.
- FIGS. 1 ( a )- 1 ( e ) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structures on thin SiGe-on-Insulator (SGOI) substrate (generation G1-G4 devices) properly scaled in accordance with the invention.
- FIG. 1 ( f ) illustrates a Si/SiGe p-type MODFET structure on thin SGOI substrate properly scaled in accordance with the invention.
- FIG. 1 ( a ) particularly depicts a MODFET device according to a first embodiment.
- a top doped nMODFET device 10 comprising a Si substrate layer 5 , a buried dielectric layer 8 formed on top of the substrate 5 which may range up to 200 nm in thickness and comprise an oxide, nitride, oxynitride of silicon; and a channel region 25 formed between n+-type doped source and drain regions 11 , 12 respectively, and a gate structure 20 including a gate dielectric layer 22 separating the gate conductor 18 from the channel 25 .
- the gate dielectric layer may comprise an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations. It is important to realize that according to the invention, the dimensions of the device including drain, source, gate and channel regions have been scaled.
- the composition of the channel region 25 of device 10 in FIG. 1 ( a ) is as follows: A relaxed SiGe layer 30 having a p-type dopant is provided on a buried dielectric layer 8 having Ge content ranging between 30-50% and ranging in thickness between 20 nm-30 nm.
- the p-type doping concentration ranges between 1e14 cm ⁇ 3 -5e17 cm ⁇ 3 using one of: ion implantation or in-situ doping.
- the relaxed SiGe layer may be predoped to a concentration level of 1e14 cm ⁇ 3 -5e17 cm ⁇ 3 .
- the relaxed SiGe layer and other layers comprising the channel 25 is grown according to a UHVCVD technique, however other techniques such as MBE, RTCVD, LPCVD processes may be employed.
- a five percent (5%) SiGe seed layer 31 (Si 0.95 Ge 0.05 ) is then epitaxially grown on top of the relaxed SiGe layer 30 and an intrinsic Si 1 ⁇ x Ge x regrown buffer layer 32 is formed on top of the formed SiGe seed layer 31 .
- the thickness of epitaxially grown SiGe seed layer ranges from 0 nm-5 nm and the thickness of the intrinsic SiGe regrown buffer layer 32 ranges between 20 nm-30 nm and having Ge content “x” ranging between 10%-40%.
- An epitaxial tensile strained Si layer 33 is then grown on top of the SiGe buffer layer 32 and ranges in thickness between 5 nm-7 nm.
- An epitaxial Si 1 ⁇ y Ge y spacer layer 34 is then formed on top of the strained Si layer and ranging in thickness between 3 nm-5 nm and having Ge content “y” ranging between 30-40%.
- an epitaxial Si 1 ⁇ z Ge z supply layer 35 is grown on top of the spacer layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 2e18 cm ⁇ 3 -5e19 cm ⁇ 3 and having Ge content “z” ranging between 35-50%.
- the Si 1 ⁇ z Ge z supply layer may be grown in a temperature range between 425° C.-550° C. and in-situ doped using phosphine gas as a dopant precursor singly or in a mixture including one or more elements including but not limited to: H2, He, Ne, Ar, Kr, Xe, N 2 .
- the flow rate of the phosphine gas dopant precursor is a linear ramp or a graded profile such that said in-situ doping is performed without disrupting an epitaxial growth process. It is understood that a precursor such as AsH 3 or SbH 3 may be used as well.
- a small amount of carbon may be incorporated during the epitaxial growth of the SiGe supply layer 34 , e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably about 1-1.5%.
- an epitaxial tensile strained Si cap layer 36 is grown on top of the supply layer 35 ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm ⁇ 3 -5e19 cm ⁇ 3 .
- the gate dielectric layer 22 is formed on top of the strained Si cap layer and is having an equivalent oxide thickness in a range of 0-1 nm.
- the gate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of the gate dielectric layer 22 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30 nm-100 nm.
- the formed drain region 12 has an n-type doping concentration greater than 5e19 cm ⁇ 3 ; and the formed source region 11 has a n-type doping concentration greater than 5e19 cm ⁇ 3 .
- the distance between the gate conductor 18 and either drain or source region ranges from about 20 nm-100 nm.
- the device may further comprise a passivation layer surrounding the gate electrode 20 , the passivation layer having a permittivity ranging between 1-4.
- the depth of the quantum well, d QW of the formed nMODFET includes the spacer layer of intrinsic SiGe 34 , the layer of n+-type doped SiGe 35 and the layer of n+-type doped Si cap layer 36 totaling approximately 10 nm in depth according to the dimensions depicted in FIG. 1 ( a ).
- FIG. 1 ( b ) depicts a high-electron-mobility device 40 that is identical to the top-doped nMODFET of FIG. 1 ( a ), however, does not include the seed layer.
- FIG. 1 ( c ) illustrates a second embodiment of the invention drawn to a high-electron-mobility nMODFET device 50 that is bottom doped. As shown in FIG.
- the device 50 includes a Si substrate layer 5 , a buried dielectric layer 8 formed on top of the substrate 5 comprising an oxide, nitride, oxynitride of silicon, for example, and a channel region 55 formed between n+-type doped source and drain regions 11 , 12 respectively, and a gate structure 20 .
- the channel structure 55 includes a relaxed SiGe layer 60 on insulator 8 ranging in thickness between 10 nm and 50 nm, an epitaxial Si 0.95 Ge 0.05 seed layer 61 grown on top of the SiGe layer 60 and ranging in thickness between 0 nm-5 nm; an epitaxial Si 1 ⁇ z Ge z supply layer 62 grown on top of the seed layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm ⁇ 3 -5e19 cm ⁇ 3 ; an epitaxial Si 1 ⁇ y Ge y spacer layer 63 grown on top of the supply layer and ranging in thickness between 3 nm-5 nm; and, an epitaxial tensile strained Si channel layer 64 grown on top of the spacer layer and ranging in thickness between 3 nm-10 nm; an epitaxial Si 1 ⁇ y Ge y spacer layer 65 grown on top of the strained Si layer and ranging in thickness between 1 nm-2 nm
- a small amount of carbon may be incorporated during the epitaxial growth of the SiGe supply layer 61 , e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably about 1-1.5%.
- the second embodiment of FIG. 1 c all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition of the gate conductor metal and gate dielectric are the same as in the first embodiment ( FIG. 1 ( a )).
- the depth of the quantum well, d QW of the formed nMODFET includes the layer of n+-type doped Si cap layer 66 totaling a depth of approximately 2 nm.
- the seed layer may be omitted.
- a resulting structure is a high-electron-mobility device that is identical to the bottom-doped nMODFET of FIG. 1 ( c ), however, does not include the seed layer.
- an SGOI substrate comprises: a relaxed SiGe layer on insulator having Ge content ranging between 30-40% and ranging in thickness between 20 nm-30 nm; an epitaxial Si 1 ⁇ z Ge z supply layer grown on top of the relaxed SiGe layer ranging in thickness between 2.5 nm-8 nm and having a n-type doping concentration “z” ranging between 2e18 cm ⁇ 3 -2e19 cm ⁇ 3 and having Ge content ranging between 35-50%; an epitaxial Si 1 ⁇ y Ge y spacer layer grown on top of the supply layer and ranging in thickness between 3 nm-5 nm and having Ge content “y” ranging between 30-40%; an epitaxial tensile strained Si channel layer grown on top of the spacer layer ranging in thickness between 5 nm-7 nm and having a doping concentration less than 1e16 cm ⁇ 3 ; an epitaxial Si 1 ⁇ y Ge y spacer layer grown on top of the Si channel layer and ranging in thickness between
- FIG. 1 ( d ) illustrates a third embodiment of the invention drawn to a high-electron-mobility nMODFET device 70 that is bottom doped and including a doped transferred layer.
- the device 70 includes an SGOI substrate comprising a Si 1 ⁇ z Ge z supply layer 71 ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm ⁇ 3 -5e19 cm ⁇ 3 by ion implantation or in-situ doping; an epitaxial Si 1 ⁇ y Ge y spacer layer 72 grown on top of the supply layer and ranging in thickness between 3 nm-5 nm; an epitaxial tensile strained Si channel layer 73 grown on top of spacer layer 72 and ranging in thickness between 3 nm-10 nm; an epitaxial Si 1 ⁇ y Ge y spacer layer 74 grown on top of the strained Si layer 73 and ranging in thickness between 1 nm-2
- the Si 1 ⁇ z Ge z supply layer may be predoped to a concentration level of 1e18-5e19 atoms/cm3 before a layer transfer in forming the SGOI substrate.
- all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition and thicknesses of the gate conductor metal and gate dielectric are as depicted in the first embodiment ( FIG. 1 ( a )).
- the depth of the quantum well, d QW of the formed nMODFET includes the layer of n+-type doped Si cap layer 75 and spacer layer 74 having a depth of less than approximately 4 nm.
- FIG. 1 ( e ) illustrates a fourth embodiment of the invention drawn to a high-electron-mobility nMODFET device 80 that is both bottom and top doped and including a SiGe regrown buffer layer.
- the nMODFET device 80 includes an SGOI substrate having: a relaxed SiGe layer 81 on insulator 8 ranging in thickness between 10 nm-50 nm, having a n-type doping concentration ranging between 1e17 cm ⁇ 3 -5e19 cm ⁇ 3 and a Ge content ranging between 30-50%; a Si 1 ⁇ x Ge x regrown buffer layer 82 grown on top of the SiGe layer 81 and ranging in thickness between 10 nm-50 nm and serving as a bottom spacer layer and including a Ge content “x” ranging between 10%-35%; an epitaxial tensile strained Si layer 83 grown on top of the regrown buffer layer and ranging in thickness between 3 nm-10 n
- the depth of the quantum well, d QW of the formed nMODFET includes the layer of n+-type doped Si cap layer 86 , the epitaxial Si 1 ⁇ z Ge z supply layer 85 , and spacer layer 84 for a depth totaling less than or equal to approximately 16 nm.
- FIG. 1 ( f ) illustrates a fifth embodiment of the invention drawn to a high-hole-mobility MODFET device 80 that is bottom doped and including a doped transferred layer.
- the pMODFET device 90 includes an SGOI (SiGe layer 91 on insulator 8 ) substrate having: a relaxed epitaxial Si 1 ⁇ j Ge j supply layer ranging in thickness between 5 nm-25 nm, and having ion-implanted or in-situ p-type doping of a concentration ranging between 1e18-5e19 cm ⁇ 3 and serving as a supply layer.
- SGOI SiGe layer 91 on insulator 8
- the relaxed Si 1 ⁇ j Ge j layer may be predoped p-type to a concentration level of 1e18-5e19 boron atoms/cm3 before a layer transfer in forming the SGOI substrate; an epitaxial Si 1 ⁇ k Ge k spacer layer 92 grown on top of the supply layer 91 and ranging in thickness between 3 nm-7 nm; an epitaxial compressively strained Si 1 ⁇ m Ge m channel layer 93 grown on top of the spacer layer and ranging in thickness between 5 nm-20 nm; and, an epitaxial strained Si 1 ⁇ n Ge n cap layer 94 grown on top of the strained Si 1 ⁇ m Ge m channel layer and ranging in thickness between 2 nm-10 nm.
- the Si 1 ⁇ j Ge j supply layer 91 includes a Ge content “j” ranging between 30-70%.
- the Si 1 ⁇ k Ge k spacer layer 92 includes a Ge content “k” ranging between 30-70% and, the Si 1 ⁇ m Ge m channel layer 93 includes a Ge content “m” ranging between 60-100% and the strained Si 1 ⁇ n Ge n cap layer 94 includes a Ge content n ranging between 0%-30%.
- a gate dielectric layer 95 is formed on top of the strained SiGe cap layer 94 and is having an equivalent oxide thickness in a range of 0-1 nm.
- the gate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of the gate dielectric layer 95 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30 nm-100 nm.
- a formed drain region 97 has a p-type doping concentration greater than 5e19 cm ⁇ 3 ; and the formed source region 96 has a p-type doping concentration greater than 5e19 cm ⁇ 3 .
- the distance between the gate conductor 18 and either drain or source region ranges from about 20 nm-100 nm.
- the device may further comprise a passivation layer surrounding the gate electrode 20 , the passivation layer having a permittivity ranging between 1-4.
- the depth of the quantum well, d QW of the formed pMODFET 90 includes the SiGe cap layer 94 with a range from approximately between 2 nm-10 nm.
- Completed devices comprising embodiments depicted in FIGS. 1 ( a )- 1 ( e ) having the different layer structures and design were grown by UHVCVD under growth temperature conditions ranging between 400-600° C., and preferably in a range of 500-550° C. and in a pressure ranging from 1 mTorr-20 mTorr.
- FIG. 17 shows the performance (measured f T vs. V gs ) curves 100 with the device scaling (i.e., for G 1 and G 2 devices).
- the device has to be further scaled, both in the horizontal and vertical dimensions as in the G 2 example shown in FIG. 17 .
- FIGS. 2-5 depict simulated device characteristics for the properly scaled devices of FIGS. 1 ( a )- 1 ( f ).
- FIG. 3 depicts the simulated I d -V ds curves 110 for the G 4 device of FIG. 1 and
- FIG. 7 illustrates a graph 160 depicting the steady-state P concentration 161 vs. growth rate in a UHVCVD 162 system.
- the transient incorporation for P doping depicted by curves 165 is controlled by the Ge content 167 in a SiGe film.
- the steady state P concentration is controlled by the associated growth rate of the SiGe film.
- the key process for achieving the abruptness of P profile is to use high Ge content but at a reduced growth rate, which is difficult since it is well known that high Ge is associated with enhanced or high growth rate.
- the growth rate calibration 170 for a SiGe (Ge content of 30%) is shown in FIG. 8 , for example, with a Ge concentration profile exhibiting successively smaller peaks 171 , 172 as shown in the figure.
- the enhanced steady-state P concentration 175 is shown in FIG. 9 as a function of reduced SiGe growth rate depicted as curve 174 .
- the transient P incorporation rate is also increased as shown by the profile curve 178 in FIG. 10 .
- FIG. 15 particularly depicts the XTEM for a G3 layer structure on a SGOI substrate with a transferred SiGe layer of 50 nm, where the regrown SiGe on transferred SiGe is thick (e.g., about 134.1 nm) in order to minimize the effects of carbon and oxygen at the regrowth interface.
- a transfer SiGe layer of 50 nm
- the regrown SiGe on transferred SiGe is thick (e.g., about 134.1 nm) in order to minimize the effects of carbon and oxygen at the regrowth interface.
- MODFETs on thin SGOI one task is to make the regrown SiGe layer as thin as possible.
- a growth process has been developed using a 5% SiGe seed layer as described in the herein incorporated co-pending U.S. patent application Ser. No. 10/389,145.
- FIG. 16 depicts a XTEM for a G2 layer structure on a SGOI substrate with a thin regrown SiGe layer (e.g., about 19.7 nm) on a SGOI substrate with a 73 nm thick transferred SiGe layer. It is advantageous to begin with a thin SGOI substrate which can be formed by a wafer bonding and thinning process as described in co-pending U.S. patent application Ser. No. 10/389,145.
Abstract
Description
- 1. Field of the Invention
- The present invention relates generally to silicon and silicon germanium based semiconductor transistor devices, and more specifically, to a device design including a grown epitaxial field effect transistor structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave, sub-millimeter-wave and millimeter-wave. Preferably, the epitaxial field effect transistor structure includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve fmax in excess of 200 GHz.
- 2. Description of the Prior Art
- The attractiveness of substantial electron mobility enhancement (i.e. 3-5 times over bulk silicon) in modulation-doped tensile-strained Si quantum wells has inspired a long history of device development on Si/SiGe n-channel modulation doped filed-effect transistors (MODFETs). Subsequently, it has been demonstrated that SiGe MODFETs consume lower power and have lower noise characteristics compared to SiGe Heterojunction Bipolar Transistors (HBTs). Similarly, when compared to RF bulk Si CMOS device, SiGe MODFETs still have lower noise characteristics, and higher maximum oscillation frequency (fmax). Consequently, Si/SiGe MODFETs are becoming more and more attractive devices for high speed, low noise, and low power communication applications, where low cost and compatibility with CMOS logic technology are required and often essential. Recently, n-channel MODFETs with long channel lengths ranging from 0.2 μm to 0.5 μm have demonstrated encouraging device performances.
- Typically, a Si/SiGe MODFET device have an undoped, tensile strained silicon (NFET) or a compressively strained SiGe (PFET) quantum well channels whereby the induced strain is used to increase the carrier mobility in the channel, in addition to providing carrier confinement. The synergistic addition of modulation doping further improves the carrier mobility in the channel by reducing the ionized impurity scattering from the dopants and further reducing the surface roughness scattering in a buried channel. Record high room temperature mobilities of 2800 cm2/Vs have been achieved for electron mobilities in a tensile strained silicon channel grown on a relaxed Si0.7Ge0.3 buffer. Conversely, very high hole mobility of 1750 cm2V-s in a pure Ge channel grown on a Si0.35Ge0.65 buffer has been achieved [R. Hammond, et al, DRC, 1999]. The highest fT that has been achieved for a strained silicon nMODFET is 90 GHz [M. Zeuner, 2002], and the highest fmax is 190 GHz [Koester, et al to be published]. So far, neither fT nor fmax has reached 200 GHz with Si/SiGe MODFETs.
- As described in a simulation study conducted by the inventors, in order to achieve higher speed, the MODFET has to be scaled properly, both in the vertical dimensions and the horizontal (or lateral) dimensions. However, it turns out that the scaling of MODFETs is even more challenging than for CMOS scaling due to the following: 1) the horizontal scaling brings the source and drain closer, and, like the case in the CMOS, short-channel effects and bulk punchthrough become the major hurdles preventing the lateral scaling; and, 2) the vertical scaling of the layer structure turns out to be crucial. The lateral scaling alone cannot keep the scaling of the performance. However, the vertical scaling of the MODFET structures to reduce the depth of the quantum well (dQW) is quite challenging, particularly due to the scaling and abruptness of the n+ supply layer, which is typically doped with Phosphorus as explained in the Annual Review of Materials Science, vol. 30, 2000, pp. 348-355.
FIG. 6 illustrates agraph 200 of the Phosphorus (P) doping profile for a G1 (generation) layer structure and the steady-state P doping 201 problem and transientP doping problems 202 associated with the Phosphorus doping in a CVD growth system. - It would be highly desirable to provide a scaling technique for MODFET device structures that overcomes the lateral and vertical scaling challenges in the manufacture of MODFET device structures.
- It has been further been demonstrated in commonly-owned, co-pending U.S. patent application Ser. No. 10/389,145 entitled “Dual Strain State SiGe Layers for Microelectronics” by J. Chu, et al, filed Mar. 15, 2003, the contents and disclosure of which is incorporated by reference as if fully set forth herein, that MODFETs on a thick Silicon-Germanium-on-Insulator (SGOI) substrate will behave like MODFET on a bulk substrate. Co-pending U.S. patent application Ser. No. 10/389,145 particularly describes a generic MODFET layer structure on a SGOI substrate without specifying the critical layer structure for high performance.
- It would be further highly desirable to provide a scaled MODFET device structure that is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, wherein the MODFET device structure exhibits ultra-high speed device performance (e.g., fT, fmax>300 GHz) with better noise figures, acceptable voltage gain and good turn-off characteristics.
- The invention is directed to a high-electron-mobility n-channel MODFET device that is properly scaled and constructed on a thin SGOI/SOI substrate that exhibits greatly improved RF performance.
- The present invention is directed to a MODFET device and method of manufacture that addresses the prior art limitations and achieves vertical scaling of the nMODFET layer structure and the source/drain junction and lateral scaling of the device structure to unprecedented degrees, resulting in a device exhibiting ultra-high speed performance (i.e. fT, fmax>300 GHz) with acceptable voltage gain and good turn-off characteristics.
- In the method of manufacturing the MODFET device of the invention, the MODFET device is built on an ultra-thin SiGe-on-insulator (SGOI) substrate, such that the body is fully depleted. Due to the suppressed short channel effects, the output conductance (gd) may be thus be reduced. Therefore, the DC voltage gain (gm/gd), the linearity and fmax is significantly improved. In addition, the provision of ultra-thin SiGe buffer layers also reduces the self-heating due to the low thermal conductivity of SiGe, which reduces the drive current. Compared to a bulk MODFET, a fully-depleted SGOI MODFET exhibits better noise figures and lower soft error rate. Preferably, the epitaxial field effect transistor structure of the invention includes the critical device scaling and layer structure design for a high mobility strained n-channel transistor incorporating silicon and silicon germanium layers to form the optimum modulation-doped heterostructure on an ultra thin SOI or SGOI substrate in order to achieve fmax of >300 GHz.
- As studies have shown that the Phosphorus incorporation rate can be controlled by the growth rate (See aforementioned Annual Review of Materials Science, vol. 30, 2000, pp. 348-355), it is thus a further object of the present invention to provide a novel MODFET device structure method of achieving thin SiGe epitaxial layer with an abrupt P doping. In this objective, a novel low temperature growth technique is implemented for achieving abrupt phosphorous doping profiles in order to accommodate and to match the proper vertical scaling or design of the MODFET layer structure required for ultra-high speed performances.
- In order to prevent the Phosphorus diffusion during the fabrication process, a small amount of carbon may be incorporated during the epitaxial growth of the SiGe supply layer in the manner as described in commonly-owned, co-pending U.S. patent application Ser. No. 09/838,892 (Docket YOR920010308US1) entitled “Epitaxial and Polycrystalline Growth of Si1−x−yGexCy and S1−yCy Alloy Layers on Si by UHV-CVD”, the contents and disclosure of which is incorporated by reference as if fully set forth herein.
- The invention further is directed to a high-hole-mobility p-channel MODFET that is properly scaled and constructed on a thin SGOI/SOI substrate will also have very high RF performance.
- Further features, aspects and advantages of the apparatus and methods of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
- FIGS. 1(a)-1(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structure on thin SGOI substrate (G1-G4) properly scaled in accordance with the invention;
-
FIG. 1 (f) illustrates a Si/SiGe p-type MODFET structure on thin SGOI substrate; -
FIG. 2 illustrates a graph providing simulated Id-Vgs curves for the devices in FIGS. 1(a)-1(f) (Lgs=Lg=Lgd=50 nm); -
FIG. 3 depicts the simulated IdVds curves for a G4 device of FIGS. 1(a)-i(f); -
FIG. 4 depicts the simulated gm-Vgs curves for a G4 device of FIGS. 1(a)-1(f); -
FIG. 5 depicts the simulated ft and fmax vs. Vgs curves for a G4 device of FIGS. 1(a)-1(f); -
FIG. 6 depicts a SIMS profile of the Phosphorus (P) doping profile for a G1 (generation) layer structure and the steady-state and transient P doping exhibited in a G1 layer structure; -
FIG. 7 illustrates agraph 160 depicting the steady-state P concentration vs. growth UHV CVD system according to the invention;FIG. 8 depicts the method for calibratinggrowth rate reduction 170 for a SiGe (Ge content of 30%) according to the invention;FIG. 9 illustrates an example plot indicating the steady state P concentration as a function of reduced growth rate;FIG. 10 is a graph illustrating the profile of transient P incorporation as a function of reduced growth rates; -
FIG. 11 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G2 layer structure; -
FIG. 12 depicts a SIMS profile of the Phosphorus P doping and Ge concentration exhibited in a G3 layer structure; -
FIG. 13 depicts a XTEM for the G1 layer structure on bulk corresponding to the SIMS profiles shown inFIG. 6 ; -
FIG. 14 depicts a XTEM for a G2 layer structure on bulk corresponding to the SIMS profiles shown inFIG. 11 ; -
FIG. 15 depicts a XTEM for a G3 layer structure on a SGOI substrate with thin re-growth; -
FIG. 16 depicts a XTEM for a G2 layer structure on a SGOI substrate; and, -
FIG. 17 illustrates a measured fT vs. Vgs for a G1 device with dQW=25 nm, Lg=250 nm and a G2 device with dQW=15 nm, Lg=70 nm. - FIGS. 1(a)-1(e) are schematic cross-sectional views showing the inventive Si/SiGe n-type MODFET structures on thin SiGe-on-Insulator (SGOI) substrate (generation G1-G4 devices) properly scaled in accordance with the invention.
FIG. 1 (f) illustrates a Si/SiGe p-type MODFET structure on thin SGOI substrate properly scaled in accordance with the invention. -
FIG. 1 (a) particularly depicts a MODFET device according to a first embodiment. As shown inFIG. 1 (a), there is depicted a top dopednMODFET device 10 comprising aSi substrate layer 5, a burieddielectric layer 8 formed on top of thesubstrate 5 which may range up to 200 nm in thickness and comprise an oxide, nitride, oxynitride of silicon; and achannel region 25 formed between n+-type doped source anddrain regions gate structure 20 including a gatedielectric layer 22 separating thegate conductor 18 from thechannel 25. As shown in the figure, the gate dielectric layer may comprise an oxide, nitride, oxynitride of silicon, and oxides and silicates of Hf, Al, Zr, La, Y, Ta, singly or in combinations. It is important to realize that according to the invention, the dimensions of the device including drain, source, gate and channel regions have been scaled. - The composition of the
channel region 25 ofdevice 10 inFIG. 1 (a) is as follows: Arelaxed SiGe layer 30 having a p-type dopant is provided on a burieddielectric layer 8 having Ge content ranging between 30-50% and ranging in thickness between 20 nm-30 nm. The p-type doping concentration ranges between 1e14 cm−3-5e17 cm−3 using one of: ion implantation or in-situ doping. The relaxed SiGe layer may be predoped to a concentration level of 1e14 cm−3-5e17 cm−3. Preferably, the relaxed SiGe layer and other layers comprising thechannel 25 is grown according to a UHVCVD technique, however other techniques such as MBE, RTCVD, LPCVD processes may be employed. A five percent (5%) SiGe seed layer 31 (Si0.95Ge0.05) is then epitaxially grown on top of therelaxed SiGe layer 30 and an intrinsic Si1−xGex regrownbuffer layer 32 is formed on top of the formedSiGe seed layer 31. The thickness of epitaxially grown SiGe seed layer ranges from 0 nm-5 nm and the thickness of the intrinsic SiGe regrownbuffer layer 32 ranges between 20 nm-30 nm and having Ge content “x” ranging between 10%-40%. An epitaxial tensilestrained Si layer 33 is then grown on top of theSiGe buffer layer 32 and ranges in thickness between 5 nm-7 nm. An epitaxial Si1−yGey spacer layer 34 is then formed on top of the strained Si layer and ranging in thickness between 3 nm-5 nm and having Ge content “y” ranging between 30-40%. Then, an epitaxial Si1−zGez supply layer 35 is grown on top of the spacer layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 2e18 cm−3-5e19 cm−3 and having Ge content “z” ranging between 35-50%. The Si1−zGez supply layer may be grown in a temperature range between 425° C.-550° C. and in-situ doped using phosphine gas as a dopant precursor singly or in a mixture including one or more elements including but not limited to: H2, He, Ne, Ar, Kr, Xe, N2. Preferably, the flow rate of the phosphine gas dopant precursor is a linear ramp or a graded profile such that said in-situ doping is performed without disrupting an epitaxial growth process. It is understood that a precursor such as AsH3 or SbH3 may be used as well. As mentioned herein, in order to prevent the P diffusion during the fabrication process, a small amount of carbon may be incorporated during the epitaxial growth of theSiGe supply layer 34, e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably about 1-1.5%. Finally, an epitaxial tensile strainedSi cap layer 36 is grown on top of thesupply layer 35 ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm−3-5e19 cm−3. - To form the transistor device of
FIG. 1 (a), thegate dielectric layer 22 is formed on top of the strained Si cap layer and is having an equivalent oxide thickness in a range of 0-1 nm. Thegate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of thegate dielectric layer 22 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30 nm-100 nm. The formeddrain region 12 has an n-type doping concentration greater than 5e19 cm−3; and the formedsource region 11 has a n-type doping concentration greater than 5e19 cm−3. The distance between thegate conductor 18 and either drain or source region ranges from about 20 nm-100 nm. Although not shown, the device may further comprise a passivation layer surrounding thegate electrode 20, the passivation layer having a permittivity ranging between 1-4. As indicated inFIG. 1 (a), the depth of the quantum well, dQW of the formed nMODFET includes the spacer layer ofintrinsic SiGe 34, the layer of n+-type dopedSiGe 35 and the layer of n+-type dopedSi cap layer 36 totaling approximately 10 nm in depth according to the dimensions depicted inFIG. 1 (a). - In an alternate embodiment the
seed layer 31 ofFIG. 1 (a) may be omitted.FIG. 1 (b) depicts a high-electron-mobility device 40 that is identical to the top-doped nMODFET ofFIG. 1 (a), however, does not include the seed layer.FIG. 1 (c) illustrates a second embodiment of the invention drawn to a high-electron-mobility nMODFET device 50 that is bottom doped. As shown inFIG. 1 c), thedevice 50 includes aSi substrate layer 5, a burieddielectric layer 8 formed on top of thesubstrate 5 comprising an oxide, nitride, oxynitride of silicon, for example, and achannel region 55 formed between n+-type doped source and drainregions gate structure 20. Thechannel structure 55 includes arelaxed SiGe layer 60 oninsulator 8 ranging in thickness between 10 nm and 50 nm, an epitaxial Si0.95Ge0.05 seed layer 61 grown on top of theSiGe layer 60 and ranging in thickness between 0 nm-5 nm; an epitaxial Si1−zGez supply layer 62 grown on top of the seed layer ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm−3-5e19 cm−3; an epitaxial Si1−yGey spacer layer 63 grown on top of the supply layer and ranging in thickness between 3 nm-5 nm; and, an epitaxial tensile strainedSi channel layer 64 grown on top of the spacer layer and ranging in thickness between 3 nm-10 nm; an epitaxial Si1−yGey spacer layer 65 grown on top of the strained Si layer and ranging in thickness between 1 nm-2 nm; and, an epitaxial tensile strainedSi cap layer 66 grown on top of the spacer layer ranging in thickness between 0 nm-2 nm. As in the first embodiment, a small amount of carbon may be incorporated during the epitaxial growth of theSiGe supply layer 61, e.g., a SiGeC layer, having a C content of about 0.1-2%, preferably about 1-1.5%. Further, with respect to the second embodiment ofFIG. 1 c) all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition of the gate conductor metal and gate dielectric are the same as in the first embodiment (FIG. 1 (a)). As indicated inFIG. 1 (c), the depth of the quantum well, dQW of the formed nMODFET includes the layer of n+-type dopedSi cap layer 66 totaling a depth of approximately 2 nm. - In an alternate embodiment of the
structure 50 ofFIG. 1 (c), the seed layer may be omitted. Thus a resulting structure is a high-electron-mobility device that is identical to the bottom-doped nMODFET ofFIG. 1 (c), however, does not include the seed layer. In this alternate embodiment, an SGOI substrate comprises: a relaxed SiGe layer on insulator having Ge content ranging between 30-40% and ranging in thickness between 20 nm-30 nm; an epitaxial Si1−zGez supply layer grown on top of the relaxed SiGe layer ranging in thickness between 2.5 nm-8 nm and having a n-type doping concentration “z” ranging between 2e18 cm−3-2e19 cm−3 and having Ge content ranging between 35-50%; an epitaxial Si1−yGey spacer layer grown on top of the supply layer and ranging in thickness between 3 nm-5 nm and having Ge content “y” ranging between 30-40%; an epitaxial tensile strained Si channel layer grown on top of the spacer layer ranging in thickness between 5 nm-7 nm and having a doping concentration less than 1e16 cm−3; an epitaxial Si1−yGey spacer layer grown on top of the Si channel layer and ranging in thickness between 1 nm-2 nm and having Ge content ranging between 30-40%; and, an epitaxial tensile strained Si cap layer grown on top of the spacer layer ranging in thickness between 0 nm-2 nm. A transistor device is completed with the drain source and gate conductor regions as shown and explained with respect toFIG. 1 (c). -
FIG. 1 (d) illustrates a third embodiment of the invention drawn to a high-electron-mobility nMODFET device 70 that is bottom doped and including a doped transferred layer. As shown inFIG. 1 (d), thedevice 70 includes an SGOI substrate comprising a Si1−zGez supply layer 71 ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm−3-5e19 cm−3by ion implantation or in-situ doping; an epitaxial Si1−yGey spacer layer 72 grown on top of the supply layer and ranging in thickness between 3 nm-5 nm; an epitaxial tensile strainedSi channel layer 73 grown on top ofspacer layer 72 and ranging in thickness between 3 nm-10 nm; an epitaxial Si1−yGey spacer layer 74 grown on top of thestrained Si layer 73 and ranging in thickness between 1 nm-2 nm; and, an epitaxial tensile strainedSi cap layer 75 grown on top of the spacer layer ranging in thickness between 0 nm-2 nm. Preferably, the doped transferred Si1−zGez supply layer 71 has a Ge content z=x+a, where “a” ranges between about 0-30%, “x” ranges between 30-50%, and may be formed by a wafer bonding and smart-cut process. Alternatively, the Si1−zGez supply layer may be predoped to a concentration level of 1e18-5e19 atoms/cm3 before a layer transfer in forming the SGOI substrate. The doped transferred Si1−zGez supply layer may further comprise a Si1−m−nGemCn layer, where m=x+b, and “b” ranges between 0-30%, and “n” ranges between 0.1-2%. The Si1−yGey spacer layers 72, 74 includes a Ge content y=x+c, where “c” ranges between 0-20%. Further, with respect to the third embodiment ofFIG. 1 (d), all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition and thicknesses of the gate conductor metal and gate dielectric are as depicted in the first embodiment (FIG. 1 (a)). As indicated inFIG. 1 (d), the depth of the quantum well, dQW of the formed nMODFET includes the layer of n+-type dopedSi cap layer 75 andspacer layer 74 having a depth of less than approximately 4 nm. -
FIG. 1 (e) illustrates a fourth embodiment of the invention drawn to a high-electron-mobility nMODFET device 80 that is both bottom and top doped and including a SiGe regrown buffer layer. As shown inFIG. 1 (e), thenMODFET device 80 includes an SGOI substrate having: a relaxed SiGe layer 81 oninsulator 8 ranging in thickness between 10 nm-50 nm, having a n-type doping concentration ranging between 1e17 cm−3-5e19 cm−3 and a Ge content ranging between 30-50%; a Si1−xGex regrown buffer layer 82 grown on top of the SiGe layer 81 and ranging in thickness between 10 nm-50 nm and serving as a bottom spacer layer and including a Ge content “x” ranging between 10%-35%; an epitaxial tensile strained Si layer 83 grown on top of the regrown buffer layer and ranging in thickness between 3 nm-10 nm; an epitaxial Si1−yGey spacer layer 84 grown on top of the strained Si layer 83 and ranging in thickness between 3 nm-5 nm; an epitaxial Si1−zGez supply layer 85 grown on top of thespacer layer 84 ranging in thickness between 2 nm-8 nm and having a n-type doping concentration ranging between 1e18 cm−3-5e19 cm−3; and, an epitaxial tensile strainedSi cap layer 86 grown on top of thesupply layer 85 ranging in thickness between 0 nm-3 nm and having a n-type doping concentration ranging between 5e17 cm−3-5e19 cm−3. The Si1−yGey spacer layer 84 includes a Ge content y=x+a, where “a” ranges between 0-20% and the Si1−zGe, supply layer includes a Ge content z=x+b, where “b” ranges between 0-30%. As in the other embodiments, the Si1−zGez supply layer comprises a Si1−m−nGemCn layer, where m=x+c, and “c” ranges between 0-20%, and “n” ranges between 0.1-2%. Further, with respect to the fourth embodiment ofFIG. 1 (e), all the gate conductor geometries and distances to respective source/drain regions, the dopant concentrations of the source/drain regions, and the composition and thicknesses of the gate conductor metal and gate dielectric are as depicted in the first embodiment (FIG. 1 (a)). As indicated inFIG. 1 (e), the depth of the quantum well, dQW of the formed nMODFET includes the layer of n+-type dopedSi cap layer 86, the epitaxial Si1−zGez supply layer 85, andspacer layer 84 for a depth totaling less than or equal to approximately 16 nm. -
FIG. 1 (f) illustrates a fifth embodiment of the invention drawn to a high-hole-mobility MODFET device 80 that is bottom doped and including a doped transferred layer. As shown inFIG. 1 (f), thepMODFET device 90 includes an SGOI (SiGe layer 91 on insulator 8) substrate having: a relaxed epitaxial Si1−jGej supply layer ranging in thickness between 5 nm-25 nm, and having ion-implanted or in-situ p-type doping of a concentration ranging between 1e18-5e19 cm−3 and serving as a supply layer. Alternately, the relaxed Si1−jGej layer may be predoped p-type to a concentration level of 1e18-5e19 boron atoms/cm3 before a layer transfer in forming the SGOI substrate; an epitaxial Si1−kGek spacer layer 92 grown on top of thesupply layer 91 and ranging in thickness between 3 nm-7 nm; an epitaxial compressively strained Si1−mGem channel layer 93 grown on top of the spacer layer and ranging in thickness between 5 nm-20 nm; and, an epitaxial strained Si1−nGen cap layer 94 grown on top of the strained Si1−mGem channel layer and ranging in thickness between 2 nm-10 nm. In the high-hole-mobilitylayer semiconductor structure 90 the Si1−jGej supply layer 91 includes a Ge content “j” ranging between 30-70%. The Si1−kGek spacer layer 92 includes a Ge content “k” ranging between 30-70% and, the Si1−mGem channel layer 93 includes a Ge content “m” ranging between 60-100% and the strained Si1−nGen cap layer 94 includes a Ge content n ranging between 0%-30%. - To form the pMODFET transistor device of
FIG. 1 (f), agate dielectric layer 95 is formed on top of the strainedSiGe cap layer 94 and is having an equivalent oxide thickness in a range of 0-1 nm. Thegate conductor 18 may have a T-gate geometry, rectangular geometry or a multi-finger geometry formed on top of thegate dielectric layer 95 and may comprise Pt, Ir, W, Pd, Al, Au, Cu, Ti, Co either, singly or in combinations, at lengths ranging between 30 nm-100 nm. A formeddrain region 97 has a p-type doping concentration greater than 5e19 cm−3; and the formedsource region 96 has a p-type doping concentration greater than 5e19 cm−3. The distance between thegate conductor 18 and either drain or source region ranges from about 20 nm-100 nm. Although not shown, the device may further comprise a passivation layer surrounding thegate electrode 20, the passivation layer having a permittivity ranging between 1-4. As indicated inFIG. 1 (f), the depth of the quantum well, dQW of the formedpMODFET 90 includes theSiGe cap layer 94 with a range from approximately between 2 nm-10 nm. - Completed devices comprising embodiments depicted in FIGS. 1(a)-1(e) having the different layer structures and design were grown by UHVCVD under growth temperature conditions ranging between 400-600° C., and preferably in a range of 500-550° C. and in a pressure ranging from 1 mTorr-20 mTorr.
-
FIG. 17 shows the performance (measured fT vs. Vgs) curves 100 with the device scaling (i.e., for G1 and G2 devices). For example,FIG. 17 shows the fT curve for a G1 device with dQW=25 nm, Lg=250 nm as compared to a G2 device with dQW=15 nm, Lg=70 nm. As shown, in order to further improve the performance, the device has to be further scaled, both in the horizontal and vertical dimensions as in the G2 example shown inFIG. 17 . -
FIGS. 2-5 depict simulated device characteristics for the properly scaled devices of FIGS. 1(a)-1(f).FIG. 2 depicts the simulated Id-Vgs curves 105 for the G4 device ofFIG. 1 where Lgs=Lg=Lgd=50 nm.FIG. 3 depicts the simulated Id-Vds curves 110 for the G4 device ofFIG. 1 andFIG. 4 depicts the simulated gm-Vgs curves 120 for the G4 device inFIG. 1 (Lgs=Lg=Lgd=50 nm). As shown inFIG. 5 , there is depicted the simulated fT and fmax vs. Vgs curves 130 for the device inFIG. 1 where fT=230 GHz and fmax=370 GHz can be achieved according to device simulations. - As mentioned hereinabove, experimentally it has been found that Phosphorus (P) doping can be controlled by the Ge content and its associated growth rate in a UHV CVD system.
FIG. 7 illustrates agraph 160 depicting the steady-state P concentration 161 vs. growth rate in aUHVCVD 162 system. - As shown in the steady-state P concentration vs. growth rate graph of
FIG. 7 , in particular, the transient incorporation for P doping depicted bycurves 165 is controlled by theGe content 167 in a SiGe film. Likewise, the steady state P concentration is controlled by the associated growth rate of the SiGe film. The key process for achieving the abruptness of P profile is to use high Ge content but at a reduced growth rate, which is difficult since it is well known that high Ge is associated with enhanced or high growth rate. - The
growth rate calibration 170 for a SiGe (Ge content of 30%) is shown inFIG. 8 , for example, with a Ge concentration profile exhibiting successivelysmaller peaks state P concentration 175 is shown inFIG. 9 as a function of reduced SiGe growth rate depicted ascurve 174. Similarly, as shown in the graph depicting transient P incorporation vs. reduced growth rates inFIG. 10 , for the higher Ge content 177, the transient P incorporation rate is also increased as shown by theprofile curve 178 inFIG. 10 . - Using a reduced flow combination of SiH4 to GeH4 of (15 sccm/17 sccm), a G1 doping profile has been obtained just like secondary ion mass spectroscopy (SIMS) profiles 201, 202 as shown in
FIG. 6 . The corresponding cross-sectional transmission electron micrograph (XTEM) is shown inFIG. 13 . - Using a lower flow combination SiH4 to GeH4 of (10/17), a G2 doping profile has been achieved as shown in the SIMS profiles P doping and Ge concentration profiles shown in
FIG. 11 . The corresponding XTEM is shown inFIG. 14 . - Using an even lower flow combination SiH4 to GeH4 of (8/10), a G3 doping profile has been achieved as shown in the SIMS profiles P doping and Ge concentration profiles shown in
FIG. 12 . The corresponding XTEM is shown inFIG. 15 .FIG. 15 particularly depicts the XTEM for a G3 layer structure on a SGOI substrate with a transferred SiGe layer of 50 nm, where the regrown SiGe on transferred SiGe is thick (e.g., about 134.1 nm) in order to minimize the effects of carbon and oxygen at the regrowth interface. However, in order to make MODFETs on thin SGOI, one task is to make the regrown SiGe layer as thin as possible. A growth process has been developed using a 5% SiGe seed layer as described in the herein incorporated co-pending U.S. patent application Ser. No. 10/389,145. -
FIG. 16 depicts a XTEM for a G2 layer structure on a SGOI substrate with a thin regrown SiGe layer (e.g., about 19.7 nm) on a SGOI substrate with a 73 nm thick transferred SiGe layer. It is advantageous to begin with a thin SGOI substrate which can be formed by a wafer bonding and thinning process as described in co-pending U.S. patent application Ser. No. 10/389,145. - While the invention has been particularly shown and described with respect to illustrative and preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention that should be limited only by the scope of the appended claims.
Claims (96)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/652,400 US6855963B1 (en) | 2003-08-29 | 2003-08-29 | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate |
EP04809631A EP1685590A2 (en) | 2003-08-29 | 2004-08-27 | Ultra high-speed si/sige modulation-doped field effect transistors on ultra thin soi/sgoi substrate |
KR1020067003534A KR100826838B1 (en) | 2003-08-29 | 2004-08-27 | Ultra high-speed si/sige modulation-doped field effect transistor on ultra thin soi/sgoi substrate |
JP2006524911A JP5159107B2 (en) | 2003-08-29 | 2004-08-27 | Ultra-fast SI / SIGE modulation doped field effect transistor on ultra-thin SOI / SGOI substrate |
CNB2004800247846A CN100517614C (en) | 2003-08-29 | 2004-08-27 | Uhigh electron mobility layer structure and manufacturing method thereof |
PCT/US2004/028045 WO2005036613A2 (en) | 2003-08-29 | 2004-08-27 | Ultra high-speed si/sige modulation-doped field effect transistors on ultra thin soi/sgoi substrate |
US10/983,488 US7098057B2 (en) | 2003-08-29 | 2004-11-08 | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/652,400 US6855963B1 (en) | 2003-08-29 | 2003-08-29 | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/983,488 Division US7098057B2 (en) | 2003-08-29 | 2004-11-08 | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
US6855963B1 US6855963B1 (en) | 2005-02-15 |
US20050045905A1 true US20050045905A1 (en) | 2005-03-03 |
Family
ID=34116792
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/652,400 Expired - Lifetime US6855963B1 (en) | 2003-08-29 | 2003-08-29 | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate |
US10/983,488 Expired - Fee Related US7098057B2 (en) | 2003-08-29 | 2004-11-08 | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/983,488 Expired - Fee Related US7098057B2 (en) | 2003-08-29 | 2004-11-08 | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate |
Country Status (6)
Country | Link |
---|---|
US (2) | US6855963B1 (en) |
EP (1) | EP1685590A2 (en) |
JP (1) | JP5159107B2 (en) |
KR (1) | KR100826838B1 (en) |
CN (1) | CN100517614C (en) |
WO (1) | WO2005036613A2 (en) |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050079691A1 (en) * | 2003-10-10 | 2005-04-14 | Applied Materials, Inc. | Methods of selective deposition of heavily doped epitaxial SiGe |
US20060163672A1 (en) * | 2005-01-21 | 2006-07-27 | Chih-Hao Wang | High performance CMOS device design |
US20060292809A1 (en) * | 2005-06-23 | 2006-12-28 | Enicks Darwin G | Method for growth and optimization of heterojunction bipolar transistor film stacks by remote injection |
US7176504B1 (en) * | 2005-09-28 | 2007-02-13 | United Microelectronics Corp. | SiGe MOSFET with an erosion preventing Six1Gey1 layer |
US20070054460A1 (en) * | 2005-06-23 | 2007-03-08 | Atmel Corporation | System and method for providing a nanoscale, highly selective, and thermally resilient silicon, germanium, or silicon-germanium etch-stop |
US20070082451A1 (en) * | 2003-10-10 | 2007-04-12 | Samoilov Arkadii V | Methods to fabricate mosfet devices using a selective deposition process |
US20070102834A1 (en) * | 2005-11-07 | 2007-05-10 | Enicks Darwin G | Strain-compensated metastable compound base heterojunction bipolar transistor |
US7224007B1 (en) * | 2004-01-12 | 2007-05-29 | Advanced Micro Devices, Inc. | Multi-channel transistor with tunable hot carrier effect |
US20070148890A1 (en) * | 2005-12-27 | 2007-06-28 | Enicks Darwin G | Oxygen enhanced metastable silicon germanium film layer |
US20070262295A1 (en) * | 2006-05-11 | 2007-11-15 | Atmel Corporation | A method for manipulation of oxygen within semiconductor materials |
US20080050883A1 (en) * | 2006-08-25 | 2008-02-28 | Atmel Corporation | Hetrojunction bipolar transistor (hbt) with periodic multilayer base |
US20080087892A1 (en) * | 2006-03-28 | 2008-04-17 | Chih-Hao Wang | High Performance Transistor with a Highly Stressed Channel |
US20080099840A1 (en) * | 2006-10-26 | 2008-05-01 | Atmel Corporation | System and method for providing a nanoscale, highly selective, and thermally resilient boron etch-stop |
US20080099882A1 (en) * | 2006-10-26 | 2008-05-01 | Atmel Corporation | System and method for providing a nanoscale, highly selective, and thermally resilient carbon etch-stop |
US20090075445A1 (en) * | 2005-03-11 | 2009-03-19 | Jack Kavalieros | Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress |
US8173526B2 (en) | 2006-10-31 | 2012-05-08 | Atmel Corporation | Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator |
CN102623487A (en) * | 2011-01-26 | 2012-08-01 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
WO2013082592A1 (en) * | 2011-12-03 | 2013-06-06 | Sensor Electronic Technology, Inc. | Epitaxy technique for growing semiconductor compounds |
US8530934B2 (en) | 2005-11-07 | 2013-09-10 | Atmel Corporation | Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto |
US10158044B2 (en) | 2011-12-03 | 2018-12-18 | Sensor Electronic Technology, Inc. | Epitaxy technique for growing semiconductor compounds |
US10211048B2 (en) | 2012-02-01 | 2019-02-19 | Sensor Electronic Technology, Inc. | Epitaxy technique for reducing threading dislocations in stressed semiconductor compounds |
US10490697B2 (en) | 2011-12-03 | 2019-11-26 | Sensor Electronic Technology, Inc. | Epitaxy technique for growing semiconductor compounds |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060151787A1 (en) * | 2005-01-12 | 2006-07-13 | International Business Machines Corporation | LOW CONCENTRATION SiGe BUFFER DURING STRAINED Si GROWTH OF SSGOI MATERIAL FOR DOPANT DIFFUSION CONTROL AND DEFECT REDUCTION |
US8039880B2 (en) * | 2005-09-13 | 2011-10-18 | Raytheon Company | High performance microwave switching devices and circuits |
US7772060B2 (en) * | 2006-06-21 | 2010-08-10 | Texas Instruments Deutschland Gmbh | Integrated SiGe NMOS and PMOS transistors |
US7893475B2 (en) * | 2007-01-24 | 2011-02-22 | Macronix International Co., Ltd. | Dynamic random access memory cell and manufacturing method thereof |
US7791063B2 (en) * | 2007-08-30 | 2010-09-07 | Intel Corporation | High hole mobility p-channel Ge transistor structure on Si substrate |
CN100570823C (en) * | 2007-11-06 | 2009-12-16 | 清华大学 | A kind of method of using the necking down extension to obtain the low-dislocation-density epitaxial film |
US8293608B2 (en) * | 2008-02-08 | 2012-10-23 | Freescale Semiconductor, Inc. | Intermediate product for a multichannel FET and process for obtaining an intermediate product |
US8222657B2 (en) * | 2009-02-23 | 2012-07-17 | The Penn State Research Foundation | Light emitting apparatus |
KR101087939B1 (en) | 2009-06-17 | 2011-11-28 | 주식회사 하이닉스반도체 | Semiconductor Device and Method for Manufacturing the same |
US8648388B2 (en) | 2012-02-15 | 2014-02-11 | International Business Machines Corporation | High performance multi-finger strained silicon germanium channel PFET and method of fabrication |
US8891573B2 (en) | 2012-05-14 | 2014-11-18 | Arizona Board Of Regents | 6.1 angstrom III-V and II-VI semiconductor platform |
US9525053B2 (en) | 2013-11-01 | 2016-12-20 | Samsung Electronics Co., Ltd. | Integrated circuit devices including strained channel regions and methods of forming the same |
US9419082B2 (en) * | 2014-04-23 | 2016-08-16 | Globalfoundries Inc. | Source/drain profile engineering for enhanced p-MOSFET |
KR102155327B1 (en) | 2014-07-07 | 2020-09-11 | 삼성전자주식회사 | Field effect transistor and methods for manufacturing the same |
US9570590B1 (en) | 2015-12-10 | 2017-02-14 | International Business Machines Corporation | Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs |
US9917154B2 (en) | 2016-06-29 | 2018-03-13 | International Business Machines Corporation | Strained and unstrained semiconductor device features formed on the same substrate |
KR102551812B1 (en) * | 2016-08-23 | 2023-07-04 | 큐로미스, 인크 | Electronic power devices integrated with an engineered substrat |
CN106549039A (en) * | 2016-11-03 | 2017-03-29 | 浙江大学 | A kind of Low Power High Performance germanium raceway groove quantum well field effect transistor |
CN107221583B (en) * | 2017-05-17 | 2019-01-29 | 福建海佳彩亮光电科技有限公司 | A kind of vertical structure LED and its preparation process |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6737670B2 (en) * | 2000-08-16 | 2004-05-18 | Massachusetts Institute Of Technology | Semiconductor substrate structure |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000031491A (en) * | 1998-07-14 | 2000-01-28 | Hitachi Ltd | Semiconductor device, its manufacture, semiconductor substrate and its manufacture |
US6350993B1 (en) * | 1999-03-12 | 2002-02-26 | International Business Machines Corporation | High speed composite p-channel Si/SiGe heterostructure for field effect devices |
KR100441469B1 (en) * | 1999-03-12 | 2004-07-23 | 인터내셔널 비지네스 머신즈 코포레이션 | High speed ge channel heterostructures for field effect devices |
US6890835B1 (en) * | 2000-10-19 | 2005-05-10 | International Business Machines Corporation | Layer transfer of low defect SiGe using an etch-back process |
EP1399970A2 (en) * | 2000-12-04 | 2004-03-24 | Amberwave Systems Corporation | Cmos inverter circuits utilizing strained silicon surface channel mosfets |
US6593625B2 (en) | 2001-06-12 | 2003-07-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US6515335B1 (en) * | 2002-01-04 | 2003-02-04 | International Business Machines Corporation | Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same |
US6953736B2 (en) * | 2002-07-09 | 2005-10-11 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
-
2003
- 2003-08-29 US US10/652,400 patent/US6855963B1/en not_active Expired - Lifetime
-
2004
- 2004-08-27 JP JP2006524911A patent/JP5159107B2/en not_active Expired - Fee Related
- 2004-08-27 KR KR1020067003534A patent/KR100826838B1/en not_active IP Right Cessation
- 2004-08-27 CN CNB2004800247846A patent/CN100517614C/en not_active Expired - Fee Related
- 2004-08-27 WO PCT/US2004/028045 patent/WO2005036613A2/en active Search and Examination
- 2004-08-27 EP EP04809631A patent/EP1685590A2/en not_active Ceased
- 2004-11-08 US US10/983,488 patent/US7098057B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6737670B2 (en) * | 2000-08-16 | 2004-05-18 | Massachusetts Institute Of Technology | Semiconductor substrate structure |
Cited By (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070082451A1 (en) * | 2003-10-10 | 2007-04-12 | Samoilov Arkadii V | Methods to fabricate mosfet devices using a selective deposition process |
US7737007B2 (en) | 2003-10-10 | 2010-06-15 | Applied Materials, Inc. | Methods to fabricate MOSFET devices using a selective deposition process |
US20060234488A1 (en) * | 2003-10-10 | 2006-10-19 | Yihwan Kim | METHODS OF SELECTIVE DEPOSITION OF HEAVILY DOPED EPITAXIAL SiGe |
US20050079691A1 (en) * | 2003-10-10 | 2005-04-14 | Applied Materials, Inc. | Methods of selective deposition of heavily doped epitaxial SiGe |
US7166528B2 (en) * | 2003-10-10 | 2007-01-23 | Applied Materials, Inc. | Methods of selective deposition of heavily doped epitaxial SiGe |
US7439142B2 (en) | 2003-10-10 | 2008-10-21 | Applied Materials, Inc. | Methods to fabricate MOSFET devices using a selective deposition process |
US7224007B1 (en) * | 2004-01-12 | 2007-05-29 | Advanced Micro Devices, Inc. | Multi-channel transistor with tunable hot carrier effect |
US7465972B2 (en) * | 2005-01-21 | 2008-12-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance CMOS device design |
US9711413B2 (en) | 2005-01-21 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance CMOS device design |
US20060163672A1 (en) * | 2005-01-21 | 2006-07-27 | Chih-Hao Wang | High performance CMOS device design |
US20090090935A1 (en) * | 2005-01-21 | 2009-04-09 | Taiwan Semiconductor Manufacturing Company Ltd. | High Performance CMOS Device Design |
US8507951B2 (en) | 2005-01-21 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance CMOS device design |
US9159629B2 (en) | 2005-01-21 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company Ltd. | High performance CMOS device design |
US20090075445A1 (en) * | 2005-03-11 | 2009-03-19 | Jack Kavalieros | Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress |
US20060292809A1 (en) * | 2005-06-23 | 2006-12-28 | Enicks Darwin G | Method for growth and optimization of heterojunction bipolar transistor film stacks by remote injection |
US20070054460A1 (en) * | 2005-06-23 | 2007-03-08 | Atmel Corporation | System and method for providing a nanoscale, highly selective, and thermally resilient silicon, germanium, or silicon-germanium etch-stop |
US7176504B1 (en) * | 2005-09-28 | 2007-02-13 | United Microelectronics Corp. | SiGe MOSFET with an erosion preventing Six1Gey1 layer |
US20070102834A1 (en) * | 2005-11-07 | 2007-05-10 | Enicks Darwin G | Strain-compensated metastable compound base heterojunction bipolar transistor |
US9012308B2 (en) | 2005-11-07 | 2015-04-21 | Atmel Corporation | Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto |
US8530934B2 (en) | 2005-11-07 | 2013-09-10 | Atmel Corporation | Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto |
US20070148890A1 (en) * | 2005-12-27 | 2007-06-28 | Enicks Darwin G | Oxygen enhanced metastable silicon germanium film layer |
US20080087892A1 (en) * | 2006-03-28 | 2008-04-17 | Chih-Hao Wang | High Performance Transistor with a Highly Stressed Channel |
US7649233B2 (en) | 2006-03-28 | 2010-01-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | High performance transistor with a highly stressed channel |
US20070262295A1 (en) * | 2006-05-11 | 2007-11-15 | Atmel Corporation | A method for manipulation of oxygen within semiconductor materials |
US20080050883A1 (en) * | 2006-08-25 | 2008-02-28 | Atmel Corporation | Hetrojunction bipolar transistor (hbt) with periodic multilayer base |
US20080099882A1 (en) * | 2006-10-26 | 2008-05-01 | Atmel Corporation | System and method for providing a nanoscale, highly selective, and thermally resilient carbon etch-stop |
US7569913B2 (en) | 2006-10-26 | 2009-08-04 | Atmel Corporation | Boron etch-stop layer and methods related thereto |
US7495250B2 (en) | 2006-10-26 | 2009-02-24 | Atmel Corporation | Integrated circuit structures having a boron- and carbon-doped etch-stop and methods, devices and systems related thereto |
US20080237716A1 (en) * | 2006-10-26 | 2008-10-02 | Atmel Corporation | Integrated circuit structures having a boron etch-stop layer and methods, devices and systems related thereto |
US20080099840A1 (en) * | 2006-10-26 | 2008-05-01 | Atmel Corporation | System and method for providing a nanoscale, highly selective, and thermally resilient boron etch-stop |
US8173526B2 (en) | 2006-10-31 | 2012-05-08 | Atmel Corporation | Method for providing a nanoscale, high electron mobility transistor (HEMT) on insulator |
CN102623487A (en) * | 2011-01-26 | 2012-08-01 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
US20130037821A1 (en) * | 2011-01-26 | 2013-02-14 | Institute of Microelectronics, Chinese Academy of Science | Semiconductor Device and Manufacturing Method thereof |
WO2013082592A1 (en) * | 2011-12-03 | 2013-06-06 | Sensor Electronic Technology, Inc. | Epitaxy technique for growing semiconductor compounds |
US9831382B2 (en) | 2011-12-03 | 2017-11-28 | Sensor Electronic Technology, Inc. | Epitaxy technique for growing semiconductor compounds |
US10158044B2 (en) | 2011-12-03 | 2018-12-18 | Sensor Electronic Technology, Inc. | Epitaxy technique for growing semiconductor compounds |
US10490697B2 (en) | 2011-12-03 | 2019-11-26 | Sensor Electronic Technology, Inc. | Epitaxy technique for growing semiconductor compounds |
US10211048B2 (en) | 2012-02-01 | 2019-02-19 | Sensor Electronic Technology, Inc. | Epitaxy technique for reducing threading dislocations in stressed semiconductor compounds |
Also Published As
Publication number | Publication date |
---|---|
KR100826838B1 (en) | 2008-05-06 |
US7098057B2 (en) | 2006-08-29 |
WO2005036613A2 (en) | 2005-04-21 |
JP2007519223A (en) | 2007-07-12 |
US20050127392A1 (en) | 2005-06-16 |
JP5159107B2 (en) | 2013-03-06 |
CN1894782A (en) | 2007-01-10 |
WO2005036613A3 (en) | 2005-07-07 |
US6855963B1 (en) | 2005-02-15 |
CN100517614C (en) | 2009-07-22 |
KR20060118407A (en) | 2006-11-23 |
EP1685590A2 (en) | 2006-08-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6855963B1 (en) | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate | |
US7057216B2 (en) | High mobility heterojunction complementary field effect transistors and methods thereof | |
JP5255396B2 (en) | Multifaceted gate MOSFET devices | |
US6943407B2 (en) | Low leakage heterojunction vertical transistors and high performance devices thereof | |
US7393735B2 (en) | Structure for and method of fabricating a high-mobility field-effect transistor | |
US6900502B2 (en) | Strained channel on insulator device | |
US6927414B2 (en) | High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof | |
US6995054B2 (en) | Method of manufacturing a semiconductor device | |
US7679121B2 (en) | Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof | |
US6767793B2 (en) | Strained fin FETs structure and method | |
US20070148939A1 (en) | Low leakage heterojunction vertical transistors and high performance devices thereof | |
US20040157353A1 (en) | Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof | |
US20030057439A1 (en) | Dual layer CMOS devices | |
US7791107B2 (en) | Strained tri-channel layer for semiconductor-based electronic devices | |
JP2000286418A (en) | Semiconductor device and semiconductor substrate | |
JPH07321222A (en) | Cmos transistor logic circuit using distortion si/sige hetero structure layer | |
Hokazono et al. | 25-nm gate length nMOSFET with steep channel profiles utilizing carbon-doped silicon layers (a P-type dopant confinement layer) | |
US6984844B2 (en) | Semiconductor device having heterojunction type MIS transistor which can operate at reduced voltage while maintaining high operation speed | |
US20080026540A1 (en) | Integration for buried epitaxial stressor | |
JPH0590517A (en) | Semiconductor device and manufacture thereof | |
Vandooren | Physics and Integration of Fully-Depleted Silicon-On-Insulator Devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHU, JACK O.;OUYANG, QIQING C.;REEL/FRAME:014471/0139 Effective date: 20030829 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: NAVY, UNITED STATES OF AMERICA AS REPRESENTED BY T Free format text: CONFIRMATORY LICENSE;ASSIGNOR:IBM;REEL/FRAME:025189/0421 Effective date: 20040326 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 8 |
|
SULP | Surcharge for late payment |
Year of fee payment: 7 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION, DELAWARE Free format text: SECURITY AGREEMENT;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:049490/0001 Effective date: 20181127 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GLOBALFOUNDRIES INC.;REEL/FRAME:054633/0001 Effective date: 20201022 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:054636/0001 Effective date: 20201117 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |