Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
  • H10D30/0245—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/62—Fin field-effect transistors [FinFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/687—Floating-gate IGFETs having more than two programming levels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/691—IGFETs having charge trapping gate insulators, e.g. MNOS transistors having more than two programming levels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
  • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
  • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
  • G11C2216/02—Structural aspects of erasable programmable read-only memories
  • G11C2216/06—Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/62—Fin field-effect transistors [FinFET]
  • H10D30/6215—Fin field-effect transistors [FinFET] having multiple independently-addressable gate electrodes

Definitions

• This invention relates in general to a memory and specifically to a memory with charge storage locations.
• Some memories utilize charge storage locations of transistors for storing data. Examples of such memories include thin film memories and floating gate memories. These type of memories may be implemented with planar CMOS transistors. The density of charge storage locations in a memory implementing planar transistors may be limited due to limitations in scalability such as e.g. contact area requirements. Furthermore, it may be difficult to implement a memory with planar transistors in an integrated circuit with non planar transistors.
• Figure 1 is a partial side cross sectional view of one embodiment of a semiconductor wafer during a stage in the manufacture of a transistor according to the present invention.
• Figure 2 is a partial side cross sectional view of one embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 3 is a partial isometric view of one embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 4 is a partial side cross sectional view of one embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 5 is a partial side cross sectional view of one embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 6 is a partial side cross sectional view of one embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 7 is a partial side cross sectional view of one embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 8 is a partial side cross sectional view of one embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 9 is a partial isometric view of one embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 10 is a partial side cross sectional view of one embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 11 is a partial side cross sectional view of another embodiment of a semiconductor wafer during a stage in the manufacture of a transistor according to the present invention.
• Figure 12 is a partial side cross sectional view of another embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 13 is a partial side cross sectional view of another embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 14 is a partial side cross sectional view of another embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 15 is a partial side cross sectional view of another embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 16 is a partial isometric view of another embodiment of a semiconductor wafer during another stage in the manufacture of a transistor according to the present invention.
• Figure 17 is a partial cut away top view of another embodiment of a transistor according to the present invention.
• Figure 18 is a schematic of one embodiment of a memory array according to the present invention.
• Figure 19 sets forth a table of one embodiment of a set of voltages applied to bitlines and word lines of a memory array for programming, erasing, and reading a charge storage location of the memory array according to the present invention.
• Figure 20 sets forth a table of one embodiment of a set of voltages applied to bitlines and word lines of a memory array for programming, erasing, and reading another charge storage location of the memory array according to the present invention.
• Figure 21 sets forth a table of another embodiment of a set of voltages applied to bitlines and word lines of another memory array for programming, erasing, and reading a charge storage location of the memory array according to the present invention.
• Figure 22 sets forth a table of another embodiment of a set of voltages applied to bitlines and word lines of another memory array for programming, erasing, and reading another charge storage location of the memory array according to the present invention.
• Figure 1 shows a partial side cross sectional view of one embodiment of a semiconductor wafer during a stage in the manufacture of a transistor with independent gate structures according to the present invention.
• Wafer 101 includes a substrate with an insulating layer 103.
• a structure 104 has been formed over insulating layer 103.
• Structure 104 includes a semiconductor structure portion 105 formed over insulating layer 103, a dielectric portion 111 (e.g. silicon dioxide) formed over semiconductor structure portion 105 and layer 103, and a nitride portion 109 located over portion 111 and portion 105.
• structure 104 is formed by depositing a layer of semiconductor material over layer 103, forming a dielectric layer over the semiconductor layer (e.g.
• semiconductor structure portion 105 is made of epitaxial silicon bonded on insulating layer 103.
• portion 105 may be made of polysilicon or other semiconductor material.
• structure 104 is a fin structure of a FinFET.
• portion 109 may be made of other materials (e.g. other dielectrics) that can be utilized as a hard etch mask.
• a conformal polysilicon layer 203 is deposited over wafer 101 including over structure 104.
• polysilicon layer 203 is utilized to form independent gate structures of a FinFET transistor.
• layer 203 may be made of other gate materials such as e.g. tungsten, titanium, tantalum silicon nitride, suicides such as cobalt or nickel suicides, germanium, silicon germanium, other metals, or combinations thereof.
• a conformal nitride layer 205 is then deposited over layer 203.
• layer 205 is used both as an antireflective coating and as a hard mask for etching layer 203. Layer 205 may not be included in some embodiments.
• layer 203 may be doped prior to the deposition of layer 205.
• layer 205 may be doped with single or multiple implants at various energies, angles, and/or species.
• the left side of layer 203, relative to the view shown in Figure 2 may doped with a first dopant at a first angle to provide that portion with a first conductivity type
• the right side of the layer 203, relative to the view shown in Figure 2 may be doped at a second angle relative to the view shown in Figure 2 to provide that portion with a second conductivity type.
• Figure 3 is a partial isometric view of wafer 101 after layers 205 and 203 have been patterned to form gate structure 301.
• layers 205 and 203 are patterned by the utilization of conventional photolithographic techniques.
• the portion of nitride portion 109 located over structure 104 but not located under gate structure 301 is removed. In other embodiments, this portion of nitride portion 109 may be removed at a later stage during manufacture.
• Structure 104 includes current terminal regions 303 and 305 located in each end of portion 105 of structure 104.
• regions 303 and 305 serve as the source and drain regions, respectively.
• Regions 303 and 305 may be doped at this time by e.g. ion implantation or plasma doping.
• Figure 4 shows a partial cross sectional view of wafer 101 after a deposition of a planar layer 403 over wafer 101.
• layer 403 may be made of e.g., photo resist, spin on glass, or organic antireflective coating material.
• Layer 403 may be formed by spin on techniques or by chemical vapor deposition techniques followed by chemical mechanical polish or reflow.
• Figure 5 shows wafer 101 after layer 403 has been etched back to a level below the top of portion 505 of nitride layer 203 located over structure 104 to expose portion 505.
• layer 403 may be etched back, e.g., by a conventional dry or wet etch techniques.
• layer 403 is at least thick enough to cover portion 503 of layer 205 such that portion 505 of layer 205 may be removed by etching without removing portion 503.
• the resultant structure of layer 403 as shown in Figure 5 may be formed by the planar deposition of the material of layer 403 to the level shown in Figure 5, or other desired level.
• Figure 6 shows the same view as Figure 5 after portion 505 of nitride layer 205 located over structure 104 has been removed by etching.
• Layer 403 (along with the remaining portions of layer 205) protects portions 707 and 709 of layer 203 from being removed during the etching of layer 203.
• Gate structures 701 and 703 each have a vertical portion located along a sidewall of structure 104.
• Utilizing a planar layer for the formation of independent gate structures may allow a portion of the gate material to be removed to form separate gate structures for a transistor without extra masking steps.
• the planar layer allows for the portion of the gate structure located over structure 104 to be removed without removing the portions of the gate structure used to form the independent gate structures.
• portions of the conformal layers including the gate material located over structure 104 are exposed from the planar layer, those portions can be removed e.g. by etching to isolate the gate structures without use of an extra mask step. Accordingly, alignment problems in forming separate gate previously described may be avoided.
• Figure 8 shows the same view as Figure 7 after the removal of the remaining portions of layers 403 and 205.
• these layers may be removed by wet or dry etches. In other embodiments, the remaining portions of layers 403 and 205 are not removed.
• Figure 9 shows an isometric view of the transistor shown in Figure 8.
• spacers and suicide layers of the transistor are formed by conventional semiconductor techniques.
• Regions 903 and 905 serve as current terminal contacts (e.g. as source/drain contacts for FETs).
• regions 907 and 909 serve as gate contacts for gate structures 701 and 703, respectively.
• Figure 10 shows the same view as Figure 8 after the formation of gate vias 1003 and 1005 over regions 907 and 909, respectively.
• a low K dielectric material 1009 is shown deposited over the resultant transistor structure.
• Other conventional processing stages not shown or described herein may be performed on wafer 101 to form other conventional structures (such as e.g. interconnects and passivation layers) of a semiconductor device. Afterwards, the wafer is singulated to separate the integrated circuits of the wafer.
• Transistors with independent gate structures may be made by other processes.
• the formation of the planar layer 403 and the removal of the portion of gate material (e.g. in layer 203) located over structure 104 may be performed after the formation of spacers and/or silicides as described above with respect to Figure 10.
• transistors with independent gate structures maybe made with out utilizing conformal nitride layer 205. With these embodiments, the planar layer 403 would be formed such that the top portion of the layer of gate material (e.g. 203) located over structure 104 would be exposed for etching.
• independent gate structures may be coupled together either by hardwiring (e.g. conductive material extending between the gate structures) or by other transistors which would allow for the gate structures to be selectively coupled together.
• FIGS 11-17 set forth views of a semiconductor wafer during various stages in the manufacture of another embodiment of a transistor with independent gate structures according to the present invention.
• the transistor formed also includes charge storage locations located between the gates and the channel region of the transistor. As will be describe later, such a transistor may be utilized as a non volatile memory device for storing data in the charge storage locations.
• Wafer 1101 includes a substrate having an insulating layer 1103.
• a structure 1104 has been formed over insulating layer 1103.
• structure 1104 is a "fin" structure for a FinFET transistor having charge storage locations.
• Structure 1104 includes a semiconductor structure portion 1105 formed over the insulating layer 1103, a dielectric portion 1111 (e.g. silicon dioxide) formed over semiconductor structure portion 1105 and layer 1103, and a nitride portion 1109 located over portion 1111 and portion 1105.
• structure 1104 is formed by depositing a layer of semiconductor material over layer 1103, forming a dielectric layer over the semiconductor material layer (e.g.
• the semiconductor layer, the dielectric layer, and the nitride layer are then patterned to form a structure wherein the sidewalls of the semiconductor layer, the dielectric portion 1111, and nitride portion 1109 are flush with each other.
• the remaining portion of the semiconductor layer is then trimmed (e.g. with a dry etch having an isotropic component) to recess the sidewalls of remaining semiconductor layer to form portion 1105 as shown in Figure 11.
• structure portion 1105 is not trimmed.
• structure portion 1105 may be doped prior to the patterning of the layer of semiconductor material by conventional semiconductor processing techniques to provide the channel region of portion 105 with a specific conductivity type.
• a dielectric layer 1107 is formed on the sidewalls of semiconductor structure portion 1105. As will be shown later, the channel region and current terminal regions are formed in portion 1105.
• semiconductor structure portion 1105 is made of epitaxial silicon bonded on insulating layer 1103. In other embodiments, portion 1105 may be made of polysilicon or other semiconductor material, hi one embodiment, structure 1104 is a fin structure of a FinFET.
• layer 1203 of charge storage material is then deposited over wafer 1101 including structure 1104.
• layer 1203 includes a layer of conductive material such as polysilicon (e.g. as with a floating gate transistor).
• layer 1203 may include other types of charge storage material including material having a plurality of charge trapping elements (e.g. silicon nitride as with a thin film transistor).
• layer 1203 may include discrete charge storage material (e.g. silicon nanocrystals embedded in a layer of dielectric). In some embodiments, the nanocrystals are 2-10 nm in diameter and have a density of 3-10e ⁇ l l/cm ⁇ 2.
• layer 1203 may be made of multiple layers such as e.g. a layer of silicon nanocrystals and a layer of silicon nitride deposited over the layer of silicon nanocrystals or a layer of silicon nanocrystals embedded between two layers of dielectric material.
• Figure 13 shows a partial cross sectional view of wafer 1101 after layer 1203 has been etched to remove the portion of layer 1203 located over nitride portion 1109 and located on insulating layer 1103. Portions of layer 1203 remaining will later be etched to form isolated charge storages structures 1307 and 1305 located on the opposite sidewalls of structure 1104.
• layer 1203 is etched with anisotropic dry etch to form storage structures 1307 and 1305.
• the charge storage material is made of a high resistivity material such that there would be little to no leakage current, layer 1203 is not etched. In such embodiments, the charge storage structures having charge storage locations would be part of a contiguous layer 1203.
• Figure 14 shows a partial cross sectional view of wafer 1101 after a conformal layer 1403 of control dielectric has been deposited over wafer 1101 and after a conformal layer 1407 of gate material has been deposited over layer 1403.
• gate material layer 1407 After the deposition of gate material layer 1407, the wafer is further processed to form to two gate structures as per a similar process describe above with respect to Figures 2-8.
• a nitride layer (not shown), similar to nitride layer 205 in Figure 2, is deposited over layer 1407.
• the nitride layer and layer 1407 is then patterned to form a gate structure similar to gate structure 301 shown in Figure 3.
• a portion of charge storage layer 1203 located on the side of dielectric layer 1107 and not underneath the gate structure is etched after the layer 1407 has been etched.
• a planar layer (similar to layer 403 in Figure 5) is formed wherein the portion of the nitride layer located above structure 1104 is exposed (See Figure 5 and the text discussing thereof).
• the gate material located above structure 1104 is then etched to form gate structures 1505 and 1503 (See Figure 15) in a manner similar to that set forth in Figures 6-8 and the discussion thereof.
• Figure 15 shows a partial side view of wafer 1101 after the formation of gate structures 1505 and 1503.
• Figure 16 is a partial isometric view of the transistor structure shown in Figure 15. Regions 1607 and 1605 serve as current terminal regions with 1611 and 1613 serving as current terminal contacts (e.g. as source/drain contacts for FETs) for those regions. Also, regions 1620 and 1617 serve as gate contacts for gate structures, 1505 and 1503 respectively.
• gate structures 1503 and 1505 are doped.
• the material of these gate structures is doped, in one embodiment, prior to the deposition of the nitride layer (e.g. 205) over the layer of gate material.
• the current terminal regions 1607 and 1605 are doped after the formation of gate structures 1505 and 1503 to provide a conductivity type that is different from the conductivity type of the channel region of semiconductor structure portion 1105.
• suicide layers, spacers, gate vias, and current terminal vias are formed over transistor structure 1621 by conventional semiconductor techniques.
• a low K dielectric material e.g. 1009 may also deposited over the resultant transistor structure 1621.
• Other conventional processing stages not shown or described herein may be performed on wafer 1101 to form other conventional structures (such as e.g. interconnects and passivation layers) of an integrated circuit.
• the resultant transistor structure 1621 shown in Figure 16 can be utilized as a non volatile memory cell having four isolated charge storage locations (two each in charge storage structure 1305 and 1307, respectively) that can each store one of bit of data.
• FIG 17 is a partial cutaway top view of transistor structure 1621 shown in Figure 16.
• Charge storage structure 1305 includes two charge storage locations 1709 and 1711, and charge structure 1307 includes two charge storage locations 1713 and 1715. These four charge storage locations may be programmed, read, and or erased by applying voltages to current terminal regions 1605 and 1607 and gate structures 1503 and 1505.
• the transistor structure 1621 functions as two functional MOSFET transistors that share source/drain regions and each have two charge storage locations.
• Gate structure 1503 serves as the gate for one of the functional transistors, and gate structure 1505 serves as the gate of the other functional transistors.
• Charge storage locations 1709 and 1711 serve as charge storage locations for the functional transistor having gate structure 1503 as its gate.
• Charge storage locations 1713 and 1715 server as charge storage locations for the functional transistor having gate structure 1505 as its gate.
• semiconductor structure portion 1105 includes a channel region 1725 (approximately differentiated by the dashed lines) located between current terminal regions 1605 and 1607.
• Channel region 1725 is doped to provide a first conductivity type and current terminal regions 1605 and 1607 are doped to provide a second conductivity type.
• transistor structure 1621 when a voltage is applied to gate structure 1503 that exceeds a voltage threshold of the functional transistor associated with gate structure 1503, an inversion region forms along the sidewall of the channel region 1725 adjacent to gate structure 1503.
• an inversion layer forms along the sidewall of channel region 1725 adjacent to gate structure 1505.
• portion 1105 is relatively thin between gate structures 1503 and 1505, the regions where the inversion layers occur may overlap.
• Charge may be injected into each of the charge storage locations (e.g. by hot carrier injection) to increase the threshold voltage of the functional transistor associated with that charge storage location.
• a positive voltage (Npp) is applied to gate structure 1503
• V2 Npp is applied to current terminal region 1605
• a ground potential is applied to current terminal region 1607 and gate structure 1505.
• Each of the charge storage locations may be read independently of each other.
• Application of a positive voltage (Ndd) to the gate structure adjacent to a charge storage location and a positive voltage (Ndd) to the current terminal on the opposite side of the charge storage location will effectively read the charge stored in the charge storage location without being affected by the charge stored in the other charge storage locations.
• a positive charge is applied to gate structure 1503 and to current terminal region 1607, with a ground potential (VSS) being applied to gate structure 1505 and current terminal region 1605.
• the voltage applied to current terminal region 1607 is sufficiently positive so that it effectively masks or shadows any charge present in charge storage location 1711. Li this way, the current through the channel region is primarily affected by the charge stored in location 1709 and not by the charge stored in any other charge storage location.
• a hot hole injection technique may be utilized. For example, to erase the charge stored in charge storage location 1709, a negative voltage (-Npp) is applied to gate structure 1503 and a positive voltage (Npp) is applied to current terminal region 1605, the current terminal adjacent to charge storage location 1709. A ground potential (Nss) is applied to current terminal region 1605 and gate structure 1505.
• the charge storage locations of structure 1621 may be erased at the same time by applying a negative voltage (-Npp) to gate structures 1503 and 1505 and a positive voltage (Npp) to current terminal regions 1605 and 1607.
• program, read, and/or erase techniques may be utilized for programming, reading and/or erasing the charge in the charge storage location of transistor structure 1621.
• other conventional techniques for reading a non volatile memory cells having two storage locations may be used.
• transistor structure 1621 may be utilized such that it implements only two charge storage locations.
• the first charge storage location is located in charge storage structure 1305 and the second charge storage location is located in charge storage structure 1307.
• transistor structure 1621 is utilized as two functional transistors with each functional transistor including a charge storage location.
• the charge storage layer would be made of conducting material (e.g. polysilicon) e.g. as with a floating gate transistor.
• each charge storage structure (1305 and 1307) would independently be able to store a charge, but transistor structure 1621 would be read as a single functional transistor having 4 voltage threshold levels.
• the voltage threshold would be a function of the charge stored in both the charge storage structures.
• the charge storage structures would be programmed with different voltages applied to the gates structures.
• the transistor structure would be read with a single voltage applied to both gate structures.
• the gate structures would be preferably of different conductivity types or would have different work functions.
• a transistor structure having gate structures adjacent to the sidewalls of the channel region may have other configurations.
• the width, length, and/or height of the channel region 1725 may be of other dimensions.
• multiple transistor structures may be linked together wherein each transistor structure shares a current terminal region (e.g. 1607) with the adjacent transistor structure.
• the channel regions (e.g. 1725) and the gate structures (e.g. 1503 and 1505) would be located between the shared current terminal regions (e.g. 1607 and 1605).
• An example of such an implementation may be represented by the array shown in Figure 18 wherein the current terminal region of one transistor structure is serves as the current terminal of another transistor structure.
• a second intermediate structure (not shown) would extend from end structure 1630 in the opposite direction (to the left relative to the view shown in Figure 17) as intermediate structure 1631 of structure 1104 extends from end structure 1630.
• a third intermediate structure (not shown) would extend from end structure 1629 in the opposite direction (to the right relative to the view shown in Figure 17) as intermediate structure 1631 extends from end structure 1629.
• a pair of gate structures similar to gate structures 1503 and 1505 would be adjacent to each sidewall of the second intermediate structure and third intermediate structure, similar to the position of gate structures 1503 and 1505 with respect to intermediate structure 1631.
• the gate structures 1503 and 1505 may have different conductivity types. This may be accomplished in one embodiment by angled implantation of different dopant species. For example gate structure 1505 may be implanted with a P+ dopant and gate structure 1503 may be implanted with an N+ dopant.
• Figure 18 is a circuit diagram of a non volatile memory array implementing the transistor structure 1621 as a memory cell including four storage locations (1713, 1709, 1715, and 1711).
• array 1801 is a non volatile memory array of an integrated circuit device.
• Array 1801 includes a number of memory cells with each cell (e.g. 1809, 1805, 1807) implementing a transistor structure similar to transistor structure 1621.
• Each cell includes four storage locations similar to storage locations 1713, 1709, 1715, and 1711.
• the gate structures (e.g. 1505 and 1503) of each cell are coupled to a word line.
• gate structure 1505 is couple to word line WL0 and gate structure 1503 is coupled to word line WLl.
• Each current terminal region of a memory cell is coupled to a bitline.
• terminal contact 1611 of terminal region is coupled to bitline BL1 and current terminal contact 1613 is coupled to bitline BL2.
• the bitlines (BL0, BL1, BL2, and BL3) and the word lines (WL0, WLl, WL2, and WL3) of array 1801 are couple to conventional memory array control circuitry (not shown) for controlling the voltages of the lines.
• the memory cells are arranged in array 1801 in rows and columns.
• cells 1809 and the cell of transistor structure 1621 are in the same row, and cells, 1809 and 1807 are in the same column.
• SA sense amplifier
• BLl is coupled to a sense amplifier (not shown), as designated by "SA" in the table of Figure 19, to determine whether the transistor has been turned on or not. Whether a transistor has been turned on or not is dependent upon whether a charge is stored at the charge storage location (e.g. 1713) being read.
• bitline BLl a voltage of VPP/2 is applied to bitline BLl and all bitlines located before BLl (e.g. BL0) so that locations having a gate coupled to word line WLO located before bitline BLl (e.g. charge storage location 1821) are not programmed.
• a ground voltage VSS is applied to all bitlines located after BLl (e.g. BL2 and BL3) so that no charge storage locations located after bitline BL2 (e.g. 1823) are inadvertently programmed.
• the charge storage locations of array 1801 may be erased in a block erase function. In these embodiments, a positive voltage is applied to all bitlines and a negative voltage is applied to all word lines.
• Figure 20 sets forth voltages applied to the bitlines and word lines shown in Figure 18 for programming, erasing, and reading storage location 1711.
• the gate of a cell opposite of the charge storage location being programmed, erased, or read is biased at ground (VSS) during these operations.
• gate structure 1503, which is opposite of charge storage location 1713, is biased at VSS during program, erase, and read operations of location 1713.
• Figures 21 and 22 set forth voltages that are applied to the bitlines and word lines of array 1801 in another embodiment for programming, erasing, and reading the charge storage locations of 1801.
• the opposing gate to the charge storage location of a cell being programmed is biased at the opposite voltage of the gate of the cell associated with that location.
• a positive voltage VPP is applied to the word line (WLO), which is coupled to gate structure 1505 and is associated with charge storage location 1713
• -VPP is applied to word line WLl, which is coupled gate structure 1503 and is opposite to charge storage location 1713.
• the width and conductivity of the channel regions of the transistor structures are such that the potential of the channel region adjacent to a gate structure is influenced by the opposing gate structure. Because a negative program voltage can be applied to the opposing gate of a charge storage location being programmed, the voltage applied to the gate associated with the cell being programmed may be reduced accordingly.
• VPP may be 6.0 volts. Accordingly, because this embodiment allows for a reduction in the program voltage, lower programming voltages may be utilized. In some embodiments, reducing the programming voltage may allow for a reduction in the area required for circuitry to provide the program voltage.
• the opposite gate of a charge storage location can provide a transistor such as e.g. a FinFET with a voltage control circuit that effectively acts like as a well voltage control circuit for a planar CMOS transistor.
• a transistor such as e.g. a FinFET
• the voltage of the opposing gate can be controlled independently of gates in other rows of the array. This may allow for the use of more advanced program and erase techniques for an array than would be possible with other types of charge storage transistors.
• One advantage that may occur with the array shown in Figure 18 is that more charge storage locations may be implemented in a given area than with planar CMOS NVM cells. Furthermore, with the array of Figure 18, because 4 independent storage locations are programmable utilizing just two current terminal contacts, the transistors may be more closely placed in an array. In some embodiments, a transistor structure similar to transistor structure 1621 may be easily implemented in an integrated circuit having devices implementing FinFET technology or other types of silicon on insulator technology.
• transistor structure 1261 may be modified to have only one charge storage structure between a gate and the sidewall of the channel region.
• the opposing sidewall would not have a charge storage structure between it and the opposing gate.
• the opposing gate would serve as an effective well bias voltage control circuit.
• transistor structures such as those describe above may be implemented in memory arrays having other configurations.
• a memory cell having two independent gate structures adjacent to opposing sidewalls of a semiconductor structure and having charge storage locations located between the gate structures and the sidewalls maybe made by other semiconductor processes other than that set forth in this specification, including other conventional processes for forming independent gate structures.
• a memory device in one aspect of the invention, includes a substrate and a semiconductor structure over the substrate.
• the semiconductor structure includes a channel region between a first current region and a second current region.
• the semiconductor structure has a first sidewall and a second sidewall. The second sidewall opposes the first sidewall.
• the memory device also includes a gate structure adjacent to the first sidewall.
• the channel region includes a portion located along the first sidewall adjacent to the gate structure.
• the memory device further includes a charge storage location including at least a portion located between the first sidewall and the gate structure.
• a memory in another aspect of the invention, includes a plurality of memory cells each having a first gate structure, a second gate structure, first doped region, a second doped region, and a channel region adjacent to the first gate structure and the second gate structure and between the first doped region and the second doped region.
• Each of the plurality of memory cells includes four storage locations.
• the memory includes a first row of the plurality of memory cells having the first gate structure coupled to a first word line and the second gate structure coupled to a second word line.
• the memory also includes a second row of the plurality of memory cells having the first gate structure coupled to a third word line and the second gate structure coupled to a fourth word line.
• the memory further includes a first column of the plurality of memory cells that includes a first portion of the first row and the second row, having the first doped region coupled to a first bit line and the second doped region coupled to a second bit line.
• the memory still further includes a second column of the plurality of memory cells that includes a second portion of the first row and the second row, having the first doped region coupled to the second bit line and the second doped region coupled to a third bit line.
• a method of making a semiconductor device includes providing a substrate and providing a semiconductor structure over the substrate.
• the semiconductor structure has a first sidewall, a second sidewall, and a top surface.
• the method also includes forming a first region in the semiconductor structure being of a first conductivity type, forming a second region in the semiconductor structure being of the first conductivity type, and forming a channel region in the semiconductor structure between the first region and the second region being of a second conductivity type.
• the method further includes forming a first gate structure adjacent to the first sidewall and forming a first charge storage location including at least a portion located between the first sidewall and the first gate structure.

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