WO2004061951A1 - Structure d'agencement de circuit - Google Patents

Structure d'agencement de circuit Download PDF

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Publication number
WO2004061951A1
WO2004061951A1 PCT/JP2003/016644 JP0316644W WO2004061951A1 WO 2004061951 A1 WO2004061951 A1 WO 2004061951A1 JP 0316644 W JP0316644 W JP 0316644W WO 2004061951 A1 WO2004061951 A1 WO 2004061951A1
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WO
WIPO (PCT)
Prior art keywords
transistor
row
column
sub
transistors
Prior art date
Application number
PCT/JP2003/016644
Other languages
English (en)
Japanese (ja)
Inventor
Aggarwal Sachin
Original Assignee
Sanyo Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co., Ltd. filed Critical Sanyo Electric Co., Ltd.
Priority to AU2003296101A priority Critical patent/AU2003296101A1/en
Publication of WO2004061951A1 publication Critical patent/WO2004061951A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Definitions

  • the present invention relates to a circuit layout structure, and more particularly to a circuit layout structure with improved transistor pair matching characteristics.
  • Precise matching between transistors is important for the construction of current mirror circuits and differential amplifiers. In particular, this precise matching helps to obtain a low offset op amp.
  • FIG. 5 is a diagram showing a common center point type layout scheme.
  • FIG. 6 is a diagram showing an equivalent circuit of FIG. Ml and M2 are MOS field-effect transistors to be matched. You. Transistor Ml is divided into sub-transistors MS11 and MS21, and transistor M2 is similarly divided into sub-transistors MS21 and MS22.
  • these sub-transistors have a common center point P, they are called a common center point type layout structure.
  • the gates, drains, and sources of the sub-transistors MS 11 and MS 21 are connected in common to form a transistor Ml.
  • the sub-transistor MS 21 And each gate, each drain, and each source of M 2 S 2 are connected in common to form a transistor M
  • transistors of various layouts are modeled.
  • the active area means the active region of the sub-transistor, that is, the channel region through which current flows.
  • V T (X, y) is a local threshold voltage depending on the x and y coordinates, and this is set as the active region! : The average value is calculated for each area.
  • the threshold voltage varies depending on the location in the plane of the wafer for process reasons, and the change in the threshold voltage is represented by the gradient amplitude a from the origin O shown in FIG.
  • the model can be modeled by humiliating the three-dimensional ⁇ angle (gradient directory) 0. -Therefore, such a threshold voltage model is applied to the above sub-transistors MS 11, MS 12, MS 21, and MS 22, and the corresponding thresholds V T 1 1 ,
  • Ru is given by the following equation for the threshold V T ii sub transistor MS 1 1. a cos 0)] x ⁇ dW] x [dL]
  • V Tn V T + — cos0 + —asm0
  • the threshold value V T 21 of the sub-transistor MS 21 is given by the following equation.
  • V T22 V T +-a cosO + a ⁇
  • d 1 is the distance between the drains (sources) of adjacent sub-transistors
  • d 2 is the distance between the gates of adjacent sub-transistors
  • W s is the sub-total Gate width of the transistor
  • L s is the gate length of the sub-transistors.
  • I M1 is a current flowing through the transistor M 1
  • I M2 is a current flowing through the transistor M 2. Disclosure of the invention
  • mismatch percentage error [PM 2] mosquitoes definition.
  • I M1 is the current flowing through the transistors M 1
  • I M2 is a current flowing the transistor M 2.
  • I M3 is the current flowing through transistor M 3
  • I M4 is the current flowing through transistor M 4.
  • the present invention provides a circuit layout that reduces the mismatch percentage error [PM 2 ] and also reduces the mismatch percentage error [ ⁇ ].
  • the mismatch of the transistor 'pair (Ml, M2) is matched with the mismatch of the transistor' pair (M3, M4).
  • transistor Ml is matched to transistor M2 and transistor M3 is connected to transistor M2.
  • the transistor M3 is matched with the transistor Ml as much as possible
  • the transistor M4 is matched with the transistor M2 as much as possible.
  • the present invention is characterized in that a first transistor, a second transistor, a third transistor, and a fourth transistor are arranged in a matrix of four rows and four columns as a whole.
  • a circuit layout structure comprising:
  • the first transistor includes sub-transistors arranged in a first row and a second column, a second row and a first column, a third row and a fourth column, and a fourth row and a third column.
  • the second transistor includes sub transistors arranged in a first row and a first column, a second row and a second column, a third row and a third column, and a fourth row and a fourth column,
  • the third transistor includes sub-transistors arranged in a first row and a fourth column, a second row and a third column, a third row and a second column, and a fourth row and a first column.
  • the fourth transistor is composed of sub-transistors arranged in a first row and third column, a second row and fourth column, a third row and first column, and a fourth row and second column.
  • FIG. 1 is a plan view showing a multiple-pair 'matching' layout structure according to an embodiment of the present invention
  • FIG. 2 is an equivalent circuit of a multiple-pair matching.
  • Layout structure according to an embodiment of the present invention.
  • Fig. 3 is a circuit diagram of the circuit used for the simulation
  • Fig. 4 is a diagram showing the result of the simulation
  • Fig. 5 is a common center point type layout scheme.
  • FIG. 6 is a plan view, and FIG. 6 is an equivalent circuit diagram of a common center-point type rate scheme.
  • FIG. 2 is a diagram showing an equivalent circuit of FIG. M 1, M 2, M 3, and M 4 are the MOS field effect transistors to be matched.
  • Each of the transistors M l, M 2, M 3, and M 4 is composed of four sub-transistors described below, and as shown in FIG. 1, a matrix having a total of 4 rows and 4 columns is formed. Make up.
  • the first transistor Ml which is the main transistor, is divided into four sub transistors Mil, MS12, MS13, and MS14.
  • the sub-transistor M 11 is arranged in the first row and the second column
  • the sub-transistor MS 12 is arranged in the second row and the first column
  • the sub-transistor MS 13 is arranged in the third row and the fourth column
  • Transistor MS14 is arranged in the fourth row and the third column.
  • the second transistor, M 2 which is the main transistor, is also divided into four sub-transistors, M S 21, M S 22, M S 23, and M S 24.
  • the sub-transistor M 21 is arranged in the first row and first column
  • the sub-transistor MS 22 is arranged in the second row and second column
  • the sub-transistor MS 23 is arranged in the third row and third column
  • the transistor MS24 is arranged in the fourth row and the fourth column.
  • the third transistor M 3 which is the main transistor, is also divided into four sub-transistors MS 31, MS 32, MS 33, and MS 34.
  • the sub-transistor M 31 is arranged in the first row and the fourth column
  • the sub-transistor MS 32 is arranged in the second row and the third column
  • the sub-transistor MS 23 is arranged in the third row and the second column
  • Transistor MS34 is arranged in the fourth row and the first column.
  • the fourth transistor M4 which is the main transistor, is also divided into four sub-transistors MS41, MS42, MS43, and MS44.
  • the sub-transistor M 41 is arranged in the first row and third column
  • the sub-transistor MS 42 is arranged in the second row and fourth column
  • the sub-transistor MS 43 is arranged in the third row and first column
  • Transistor MS44 is arranged in the fourth row and the second column.
  • These sub-transistors have their gates, drains, and sources connected in common to form a second transistor M2.
  • These 16 sub-transistors are all N-channel MOS transistors (or all P-channel MOS transistors).
  • the 16 sub-transistors can be seen as belonging to the following four cells.
  • the first cell C 1 is composed of sub-transistors MS 21, MS 11, M 12, and MS 22.
  • the second cell C 2 is constituted by sub-transistors MS 41, MS 31, MS 32, MS 42.
  • the third cell C3 is composed of sub-transistors MS43, MS33, MS34, and MS44.
  • the fourth cell C4 is composed of sub-transistors MS23, MS13, MS14, MS24.
  • the threshold value of each sub-transistor is given by the following equation.
  • the origin 0, the gradient amplitude 0, and the gradient azimuth 0 are defined.
  • V T2l V T +- ⁇ -cos0 + a-+ 2d 2 + d 3 sin ⁇
  • V T23 V T + + 2d, cosO + sm0
  • d 1 is the distance between the drains (sources) of adjacent sub transistors
  • d 2 and d 3 are the distances between the gates of adjacent sub transistors
  • W s is the gate width of the sub transistor
  • L s is the gate length of the sub-transistor.
  • Fig. 4 shows the results of this simulation.
  • the horizontal axis indicates the gradient azimuth angle of 0, and the vertical axis indicates the mismatch percentage error.
  • the main transistors M 1 and M 2 having a multiple pair matching layout structure are matched as close as the main transistors M 1 and M 2 having a common center point layout structure. Is clearly shown.
  • the sizes of the main transistors Ml and M2 are the same for the two simulations. The same description holds for the main transistors M 3 and M 4. Therefore, the multiple-pair 'matching' layout structure of the present invention, compared with the common center point layout structure, matches the main transistor Ml with the main transistor M2 and the main transistor M3 with the main transistor M4. There is no deterioration in the matching with.
  • matching between two transistor pairs i.e., matching between a transistor pair (Ml, M2) and a transistor pair (M3, M4), is a single transistor pair pair match. (Matching between the main transistor Ml and the main transistor M2).
  • one transistor pair can be favorably matched to another transistor pair.
  • the matching characteristic of the present invention is superior to a common center point type late structure in which one transistor is matched with another transistor. ⁇ .

Abstract

L'invention concerne chaque transistor principal (M1, M2, M3, M4) constitué de quatre sous-transistors. Le transistor principal (M1) est constitué de sous-transistors disposés dans la première rangée, deuxième colonne, dans la deuxième rangée, première colonne, dans la troisième rangée, quatrième colonne, et dans la quatrième rangée, la troisième colonne. Le transistor principal (M2) est constitué de sous-transistors disposés dans la première rangée, première colonne, dans la deuxième rangée, deuxième colonne, dans la troisième rangée, troisième colonne, et dans la quatrième rangée, quatrième colonne. Le transistor principal (M3) est constitué de sous-transistors disposés dans la première rangée, quatrième colonne, dans la deuxième rangée, troisième colonne, dans la troisième rangée, deuxième colonne, et dans la quatrième rangée, première colonne. Le transistor principal (M4) est constitué de sous-transistors disposés dans la première rangée, troisième colonne, dans la deuxième rangée, quatrième colonne, dans la troisième rangée, première colonne, et dans la quatrième rangée, deuxième colonne. Ainsi, une paire de transistors peut être compatible avec d'autres paires de transistors.
PCT/JP2003/016644 2003-01-06 2003-12-24 Structure d'agencement de circuit WO2004061951A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003296101A AU2003296101A1 (en) 2003-01-06 2003-12-24 Circuit layout structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003000095 2003-01-06
JP2003-000095 2003-01-06

Publications (1)

Publication Number Publication Date
WO2004061951A1 true WO2004061951A1 (fr) 2004-07-22

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AU (1) AU2003296101A1 (fr)
TW (1) TWI228315B (fr)
WO (1) WO2004061951A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI387095B (zh) * 2009-09-08 2013-02-21 Xilinx Inc 積體電路之輸出驅動器的共享靜電放電保護

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274259A (ja) * 1995-03-29 1996-10-18 Nissan Motor Co Ltd 演算増幅器回路
JP2000091504A (ja) * 1998-09-16 2000-03-31 Nec Ic Microcomput Syst Ltd 半導体集積回路及びそのレイアウト方法
JP2000164814A (ja) * 1998-11-20 2000-06-16 Nec Ic Microcomput Syst Ltd 回路素子レイアウト方法及び半導体装置
JP2001168197A (ja) * 1999-12-08 2001-06-22 Sony Corp 半導体集積回路の素子配置構造
US6552402B1 (en) * 1998-04-09 2003-04-22 Matsushita Electric Industrial Co., Ltd. Composite MOS transistor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274259A (ja) * 1995-03-29 1996-10-18 Nissan Motor Co Ltd 演算増幅器回路
US6552402B1 (en) * 1998-04-09 2003-04-22 Matsushita Electric Industrial Co., Ltd. Composite MOS transistor device
JP2000091504A (ja) * 1998-09-16 2000-03-31 Nec Ic Microcomput Syst Ltd 半導体集積回路及びそのレイアウト方法
JP2000164814A (ja) * 1998-11-20 2000-06-16 Nec Ic Microcomput Syst Ltd 回路素子レイアウト方法及び半導体装置
JP2001168197A (ja) * 1999-12-08 2001-06-22 Sony Corp 半導体集積回路の素子配置構造

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI387095B (zh) * 2009-09-08 2013-02-21 Xilinx Inc 積體電路之輸出驅動器的共享靜電放電保護

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Publication number Publication date
TWI228315B (en) 2005-02-21
TW200414531A (en) 2004-08-01
AU2003296101A1 (en) 2004-07-29

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