WO2004061951A1

WO2004061951A1 - Circuit layout structure

Info

Publication number: WO2004061951A1
Application number: PCT/JP2003/016644
Authority: WO
Inventors: Aggarwal Sachin
Original assignee: Sanyo Electric Co., Ltd.
Priority date: 2003-01-06
Filing date: 2003-12-24
Publication date: 2004-07-22
Also published as: TWI228315B; AU2003296101A1; TW200414531A

Abstract

Each of main transistors M1, M2, M3, and M4 consists of four sub-transistors. The main transistor M1 consists of sub-transistors arranged in the first row, second column, in the second row, first column, in the third row, fourth column, and in the fourth row, third column. The main transistor M2 consists of sub-transistors arranged in the first row, first column, in the second row, second column, in the third row, third column, and the fourth row, fourth column. The main transistor M3 consists of sub-transistors arranged in the first row, fourth column, in the second row, third column, in the third row, second column, and the fourth row, first column. The main transistor M4 consists of sub-transistors arranged in the first row, third column, in the second row, fourth column, in the third row, first column, and the fourth row, second column. Thus, one transistor pair can be matched with other transistor pairs.

Description

Description Circuit layout structure Technical field

The present invention relates to a circuit layout structure, and more particularly to a circuit layout structure with improved transistor pair matching characteristics. Background art

Precise matching between transistors is important for the construction of current mirror circuits and differential amplifiers. In particular, this precise matching helps to obtain a low offset op amp.

The most commonly used matching technique is the Common-Centroid Layout Configuration. This is described in the following document.

Mao Feng Lang, Ayuruku Marta Minedy and Landar Gaia “Current Mirror Layout Strategy for Improving Matching Characteristics” Analog Integrated Circuit Signal Processing Vol. 28, pp. 9-126, 200 July

(Mao-Feng Lan, Anikumar Tammineedi and Randal 1 Geiger, Current Mirror Layout Strategies for Enhanced Matching Performance, Analog Integrated Circuits and Siganl Processing, Vol. 28, PP. 9-26, July 2001)

Hereinafter, the common center point type layout structure will be described. FIG. 5 is a diagram showing a common center point type layout scheme. FIG. 6 is a diagram showing an equivalent circuit of FIG. Ml and M2 are MOS field-effect transistors to be matched. You. Transistor Ml is divided into sub-transistors MS11 and MS21, and transistor M2 is similarly divided into sub-transistors MS21 and MS22.

As shown in FIG. 5, since these sub-transistors have a common center point P, they are called a common center point type layout structure. As shown in FIG. 6, the gates, drains, and sources of the sub-transistors MS 11 and MS 21 are connected in common to form a transistor Ml. Similarly, the sub-transistor MS 21 And each gate, each drain, and each source of M 2 S 2 are connected in common to form a transistor M

Make up two.

By the way, referring to the following literature on transistor matching and a layout structure depending on a process, transistors of various layouts are modeled.

E. M. J., E. M. Perglom, A. S. 'J. D. Win-Meijer and A.P.'. G. Welvers. Matching Characteristics of S Transistors "I.G.G.S.S.S.S.C. 2 4 volumes, 1 4 3 3 1 1 4 3 9 pages, 1 9 8 9 years

(M.J.M.Pelgrom, A.C.J.Duinmai jer and A.P.G.Welbers, Matching properties of MOS transistors "IEEE JSSC, Vol.sc-24, PP.1433-1439, 1989.

Its good UNA equivalent threshold voltage of Depaisu is given by: According to the literature _c

'' ActiveArea

Here, the active area means the active region of the sub-transistor, that is, the channel region through which current flows. V _T (X, y) is a local threshold voltage depending on the x and y coordinates, and this is set as the active region! : The average value is calculated for each area. In addition, the threshold voltage varies depending on the location in the plane of the wafer for process reasons, and the change in the threshold voltage is represented by the gradient amplitude a from the origin O shown in FIG. And the model can be modeled by humiliating the three-dimensional 酉 angle (gradient directory) 0. -Therefore, such a threshold voltage model is applied to the above sub-transistors MS 11, MS 12, MS 21, and MS 22, and the corresponding thresholds V _{T 1 1} ,

V _T α 2, V _T 2! , V _T 22.

First, Ru is given by the following equation for the threshold V _T ii sub transistor MS 1 1. a cos 0)] x \ dW] x [dL]

MS11:] = (+ M)

W xL.

W _s L _s

VT, U

3W _s ί 4 £ + d + 4L _s d ₂ -L 'd ₂ 1 2L _s d ₂

V _T L _S + acos9 \ ^s + d,

Two

TU

3W _V 3

cos0 + '+ d one sin0 similarly, Erareru given by the following equation for the threshold V _{T 1 2} of the supplicant transistor MS 1 2.

MS12: V _Tn = V _T + — cos0 + —asm0

Similarly, the threshold value V _T 21 of the sub-transistor MS 21 is given by the following equation.

_MS21 : ν _Τ2 = Ϋ _Τ + \ GOSO + — ύηθ

2 In the same manner, the sub-transistors MS 2 2 threshold V _{T 2 2} is given by the following equation Erareru.

3L _C

MS22: V _T22 = V _T +-a cosO + a \

2 In the above equation, d 1 is the distance between the drains (sources) of adjacent sub-transistors, d 2 is the distance between the gates of adjacent sub-transistors, and W _s is the sub-total Gate width of the transistor, L _s is the gate length of the sub-transistors.

Two preparative La Njisu motor M l, the Mi Suma pitch percentage error M 2 (mismatch percentage error) [ Ρ Μ α] is defined by the following equation.

ΡΜ _λ = ^Ιμ2-1 ^M1 xlOO

J Ml

Here, I _M1 is a current flowing through the transistor M 1, and I _M2 is a current flowing through the transistor M 2. Disclosure of the invention

In a particular circuit design, it is important to match two transistor pairs in addition to the matching between the two transistors Ml and M2 that make up one pair as described above. Now, suppose that it is necessary to match the transistor 'pair (Ml, M2)' with another transistor 'pair (M3, M4). Then, the following equation of mismatch percentage error (.mismatch percentage error) is [PM _2] mosquitoes definition.

^{^{PM, = (4 - 3)}} - (2 - 1) X 100 where, I _M1 is the current flowing through the transistors M 1, I _M2 is a current flowing the transistor M 2. I _M3 is the current flowing through transistor M 3, and I _M4 is the current flowing through transistor M 4.

Therefore, the present invention provides a circuit layout that reduces the mismatch percentage error [PM ₂ ] and also reduces the mismatch percentage error [ΡΜι]. For example, the mismatch of the transistor 'pair (Ml, M2) is matched with the mismatch of the transistor' pair (M3, M4). In addition, transistor Ml is matched to transistor M2 and transistor M3 is connected to transistor M2. Match to M4. Further, the transistor M3 is matched with the transistor Ml as much as possible, and the transistor M4 is matched with the transistor M2 as much as possible.

The present invention is characterized in that a first transistor, a second transistor, a third transistor, and a fourth transistor are arranged in a matrix of four rows and four columns as a whole. A circuit layout structure comprising:

The first transistor includes sub-transistors arranged in a first row and a second column, a second row and a first column, a third row and a fourth column, and a fourth row and a third column.

The second transistor includes sub transistors arranged in a first row and a first column, a second row and a second column, a third row and a third column, and a fourth row and a fourth column,

The third transistor includes sub-transistors arranged in a first row and a fourth column, a second row and a third column, a third row and a second column, and a fourth row and a first column.

The fourth transistor is composed of sub-transistors arranged in a first row and third column, a second row and fourth column, a third row and first column, and a fourth row and second column.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a plan view showing a multiple-pair 'matching' layout structure according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit of a multiple-pair matching. Layout structure according to an embodiment of the present invention. Fig. 3 is a circuit diagram of the circuit used for the simulation, Fig. 4 is a diagram showing the result of the simulation, and Fig. 5 is a common center point type layout scheme. FIG. 6 is a plan view, and FIG. 6 is an equivalent circuit diagram of a common center-point type rate scheme. BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a multiple-pair matching layout configuration, and FIG. 2 is a diagram showing an equivalent circuit of FIG. M 1, M 2, M 3, and M 4 are the MOS field effect transistors to be matched. Each of the transistors M l, M 2, M 3, and M 4 is composed of four sub-transistors described below, and as shown in FIG. 1, a matrix having a total of 4 rows and 4 columns is formed. Make up.

The first transistor Ml, which is the main transistor, is divided into four sub transistors Mil, MS12, MS13, and MS14. The sub-transistor M 11 is arranged in the first row and the second column, the sub-transistor MS 12 is arranged in the second row and the first column, the sub-transistor MS 13 is arranged in the third row and the fourth column, Transistor MS14 is arranged in the fourth row and the third column. These gates, drains and sources of the sub-transistors Ml 1, Ms 12, MS 13 and Ms 14 are connected in common to form a first transistor Ml.

Similarly, the second transistor, M 2, which is the main transistor, is also divided into four sub-transistors, M S 21, M S 22, M S 23, and M S 24. The sub-transistor M 21 is arranged in the first row and first column, the sub-transistor MS 22 is arranged in the second row and second column, the sub-transistor MS 23 is arranged in the third row and third column, The transistor MS24 is arranged in the fourth row and the fourth column. These gates, drains, and sources of these sub-transistors are connected in common to form a second transistor M2.

Similarly, the third transistor M 3, which is the main transistor, is also divided into four sub-transistors MS 31, MS 32, MS 33, and MS 34. The sub-transistor M 31 is arranged in the first row and the fourth column, the sub-transistor MS 32 is arranged in the second row and the third column, the sub-transistor MS 23 is arranged in the third row and the second column, Transistor MS34 is arranged in the fourth row and the first column. These gates, drains, and sources of these sub-transistors are commonly connected to form a third transistor M3.

Similarly, the fourth transistor M4, which is the main transistor, is also divided into four sub-transistors MS41, MS42, MS43, and MS44. The sub-transistor M 41 is arranged in the first row and third column, the sub-transistor MS 42 is arranged in the second row and fourth column, the sub-transistor MS 43 is arranged in the third row and first column, Transistor MS44 is arranged in the fourth row and the second column. These sub-transistors have their gates, drains, and sources connected in common to form a second transistor M2. These 16 sub-transistors are all N-channel MOS transistors (or all P-channel MOS transistors).

The 16 sub-transistors can be seen as belonging to the following four cells. The first cell C 1 is composed of sub-transistors MS 21, MS 11, M 12, and MS 22. The second cell C 2 is constituted by sub-transistors MS 41, MS 31, MS 32, MS 42. The third cell C3 is composed of sub-transistors MS43, MS33, MS34, and MS44. The fourth cell C4 is composed of sub-transistors MS23, MS13, MS14, MS24.

Next, when the above-described threshold voltage model is applied to the above 16 sub-transistors, the threshold value of each sub-transistor is given by the following equation. In FIG. 1, the origin 0, the gradient amplitude 0, and the gradient azimuth 0 are defined.

W f5L

MS 12: V _TU = V _T +-cosO + a-'^-+ d ₂ + d ₃ sin0

² v 2 sin Θ

W 1L

_MS21 : V _T2l = V _T +-^-cos0 + a-+ 2d ₂ + d ₃ sin ^

V

_{_{MS22: V T22 + d 2 +}} d 3 si 0

5W _V 3

MS23: V _T23 = V _T + + 2d, cosO + sm0

d ₃ sin (9

sin

(9

L MS34: F _r34 = _r + — or COS ¹ + —a sin Θ

_MS41 : F _r41 + 2d ₂ + d ₃ sm0

d ₂ + d ₃ sin <

In the above formula, d 1 is the distance between the drains (sources) of adjacent sub transistors, d 2 and d 3 are the distances between the gates of adjacent sub transistors, W _s is the gate width of the sub transistor, L _s is the gate length of the sub-transistor.

Next, a simulation using HSPICE will be described. The purpose of this simulation is to verify the matching characteristics of the multiple-pair matching layout configuration (Multiple-Pair Matching layout configuration) according to the present invention.

The parameters used in the simulation are _α = 0.5 V / μm, V _TN = 0.7 V (for N-channel MOS transistors), d 1 = d 2 = d 3 = 10 μ πι. The 16 sub-transistors have the same size, W s = 20 / m, and L s = 4 μm. Therefore, the sizes of all the main transistors M 1, M 2, M 3, and M 4 are W _s = 80 im and Ι ^ ₃ = 4 / ηηι.

In addition, for comparison, a simulation of the common center point layout structure (Common-Centroid Layout Configuration) was performed. The parameters used in the simulation are V _TN = 0.7 V (in the case of an N-channel MOS transistor) and d 1 = d 2 = 1 Ο μπι. The sizes of the sub-transistors constituting the common central point type late structure are all common, and W _s = 40 μm and L _s = 4 μm. Therefore, the main transistor M l, the size of M 2 is _{W s = 8 0 μ m,} 1 5 = 4 μ ιη. Figure 3 shows the circuit layout used for the simulation. For the multiple pair matching layout structure, four main transistors Ml, M2, M3, and M4 are used, and for the common center point type layout structure to be compared with this, the main transistor Ml , M2 only was used.

Fig. 4 shows the results of this simulation. In FIG. 4, the horizontal axis indicates the gradient azimuth angle of 0, and the vertical axis indicates the mismatch percentage error. In this simulation, the main transistors M 1 and M 2 having a multiple pair matching layout structure are matched as close as the main transistors M 1 and M 2 having a common center point layout structure. Is clearly shown.

The sizes of the main transistors Ml and M2 are the same for the two simulations. The same description holds for the main transistors M 3 and M 4. Therefore, the multiple-pair 'matching' layout structure of the present invention, compared with the common center point layout structure, matches the main transistor Ml with the main transistor M2 and the main transistor M3 with the main transistor M4. There is no deterioration in the matching with.

In addition to this, matching between two transistor pairs, i.e., matching between a transistor pair (Ml, M2) and a transistor pair (M3, M4), is a single transistor pair pair match. (Matching between the main transistor Ml and the main transistor M2).

As described above, according to the multiple pair matching late structure of the present invention, one transistor pair can be favorably matched to another transistor pair. The matching characteristic of the present invention is superior to a common center point type late structure in which one transistor is matched with another transistor. ―.

Claims

The scope of the claims

1. Circuit layout in which the first transistor, the second transistor, the third transistor, and the fourth transistor are composed of 16 sub-transistors arranged in a matrix of 4 rows and 4 columns as a whole. Structure

The first transistor includes sub transistors arranged in a first row and a second column, a second row and a first column, a third row and a fourth column, and a fourth row and a third column,

The circuit, wherein the fourth transistor includes sub-transistors arranged in a first row and a third column, a second row and a fourth column, a third row and a first column, and a fourth row and a second column. Layered structure.

2. Four sub-transistors constituting the first transistor

Gates are connected in common, drains are connected in common, sources are connected in common,

The second transistor is formed.The gates of the four sub-transistors are connected in common, the drains are connected in common, the sources are connected in common, and the four transistors forming the third transistor are connected. The gates of the sub-transistors are connected in common, the drains are connected in common, the sources are connected in common, and the gates of the four sub-transistors constituting the fourth transistor are connected in common. 2. The circuit layout structure according to claim 1, wherein each drain is connected in common, and each source is connected in common.

3. The circuit layout structure according to claim 1, wherein the 16 sub-transistors have the same size.

4. The circuit layout structure according to claim 1, wherein the 16 sub-transistors are MOS transistors of the same conductivity type.