JP2000091504A - Semiconductor integrated circuit and layout method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design a layout pattern, in which relative accuracy is maintained in a short TAT by dividing elements, in which relative accuracy is required, in a semiconductor integrated circuit, and symmetrically arranging the divided elements to center around a certain one point in response to a relative precision ratio. SOLUTION: In a current mirror circuit, transistors A, B, C are disposed relatively, centering around a certain one point on a layout. Only one element after division is arranged at the center, and other elements are disposed bilaterally in a lateral one row on both sides at the time of one element, in which a relative ratio is an odd number. The size of the divided elements is halved and only one element after division is disposed at the center, and other elements are arranged sqmetrically in the lateral one row, on both sides or disposed in the lateral one row so that the small elements in total width are placed on the insides when two or more of the elements, in which relative ratios are all odd number. The small elements in total width are arranged in the lateral one row so that the elements are placed on the insides for the elements, when all relative ratios are even numbers. Accordingly, the relative accuracy of the elements required for circuit characteristics can be ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit in which a layout pattern of the semiconductor integrated circuit is designed with a short TAT and a layout method thereof.

[0002]

2. Description of the Related Art Arrangement and wiring in a conventional layout design of a semiconductor integrated circuit are determined based only on element connection information. For this reason, only the wiring such as the wiring length and the degree of congestion of the wiring is considered as a factor for determining the arrangement position of the element. However, in recent years, the performance of computers has been accelerating year by year, and peripheral devices such as storage devices have been becoming faster and denser. For this reason, the semiconductor integrated circuit is required to have a higher speed using serial data or the like. In addition, a circuit having a strict standard of mixed analog and digital requires a relative accuracy of 1% or less. In particular, in an analog circuit, since there is a circuit that obtains characteristics on the circuit based on the characteristics of the elements, it is necessary to improve the precision of the elements in the layout design. What is generally known is a current mirror circuit that determines a current flowing at each operating point based on a ratio of W (width) of a transistor in an analog circuit.

In a conventional design method considering only wiring,
It is difficult to improve the relative accuracy of these circuits. This is because, as shown in FIG. 12, there are variations in dimensions, such as narrowing of L and biting of W, depending on the arrangement position of the elements on the wafer. This variation is due to fluctuation on the wafer, and the directionality of the variation differs depending on the location. However, the directionality of the variation within a narrower and limited area on the chip is one direction, and the degree of the variation has regularity.

As a method of ensuring relative accuracy in consideration of such element variations, for example, Japanese Patent Application Laid-Open No. 9-21 / 1990
There is an adjacent arrangement method or a relative arrangement method disclosed in Japanese Patent No. 2532 that ensures relative accuracy. This adjacent arrangement technique utilizes the fact that variations in elements are small in a narrow area.

On the other hand, the relative arrangement method is a method in which elements requiring relative accuracy are divided and arranged symmetrically around a certain point. This arrangement cancels out the variation among the transistors, so that the relative variation can be suppressed. By connecting a plurality of these divided elements in parallel, an element having a circuit design size can be formed. In an actual relative arrangement method, a required number of elements are evenly arranged in an arrangement area, a layout pattern is manually considered, and then wiring is used to connect elements to form a total size. At this time, by making the array pitch of the elements uniform, it is possible to suppress variations in the elements due to etching in the manufacturing process shown in FIG.

[0006]

However, in the former adjacent arrangement method described above, in order to obtain circuit characteristics, single elements must be arranged in a horizontal line after element division. Also, there is a restriction that elements which require relative accuracy must be arranged in a horizontal line as in the case of a single element, and it is difficult to reduce the arrangement area. When the element size is large, the arrangement area becomes large, the effect of the adjacent arrangement is weakened, and the accuracy cannot be improved. In addition, when the difference between the relative sizes of the elements is large, the dead space increases, and the degree of congestion of the wiring varies. On the other hand, in the latter relative arrangement method, the degree of congestion of the wiring in the central portion and the peripheral portion is different, and the design is performed manually, so that there is a lot of reversal and the number of steps is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and provides a semiconductor integrated circuit and a layout method thereof capable of designing a layout pattern maintaining a relative accuracy with a short TAT. It is to be.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit, wherein an element requiring relative accuracy is divided into a plurality of elements, and these divided elements are symmetrical about a certain point according to a relative ratio. It is characterized by being arranged in. In the case where the number of elements having an odd relative ratio is one, only one element after division can be arranged at the center, and the other elements can be arranged symmetrically on both sides in a horizontal row. When the relative ratio is an odd number of two or more elements, the size of the divided element is reduced to half, and only one element after division is arranged at the center, and the other elements are symmetrical on both sides. The elements can be arranged in a horizontal line, or can be arranged in a horizontal line so that the elements having a small total width are inside.
In the case where all the relative ratios are even numbers, the elements can be arranged in a horizontal row such that the elements having a small total width are inside. The layout method of a semiconductor integrated circuit according to claim 5, wherein the first step of calculating the maximum division size of the relative precision element, the step of comparing the restricted minimum division size, and the relative ratio in three cases. A second step of arranging the divided elements in a horizontal line after the identification based on the third element, a third step of determining whether or not the divided elements enter the arrangement area, and a case where the divided elements do not enter the arrangement area. A fourth step of further dividing the divided elements and arranging them by increasing the number of stages in the vertical direction, and a fifth step of blocking and arranging layout patterns including the same wiring and then connecting the same nodes. It is characterized by having. In addition, the three cases are the case where the relative ratio is one odd number, the case where the relative ratio is two or more, and the case where all the relative ratios are even. Can be. Further, in the third step, if the orientation of the elements to be arranged is irrelevant, it is determined whether or not the orientation of the element group arranged in a row is rotated by 90 ° to enter the arrangement area, and then the elements are arranged. Steps may be included. In addition, the fifth step may include a step of adding a dummy element having the same size as an unused element around the layout pattern after creating the layout pattern. In a semiconductor integrated circuit and a layout method thereof according to the present invention, an element requiring relative accuracy is divided into a plurality of elements, and these divided elements are symmetrically arranged around a certain point according to a relative ratio, and wiring is arranged. Array including layout patterns.

[0009]

Embodiments of the present invention will be described below. (First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment in which a semiconductor integrated circuit of the present invention is applied to a current mirror circuit, and FIGS. 2 and 3 are current mirrors of FIG. FIGS. 4 to 9 are flow charts for explaining a circuit layout method, and FIGS. 4 to 9 are diagrams showing examples of element arrangement according to the layout method.

In the current mirror circuit shown in FIG. 1, transistors A, B, and C, which are elements requiring relative accuracy, are relatively arranged around a certain point on a layout. When the transistors A, B, and C are arranged relative to each other and one element has an odd relative ratio, only one element after division is arranged at the center, and the other elements are symmetrical on both sides. Are arranged in a row. When the relative ratio is an odd number of two or more elements, the size of the divided element is reduced to half, and only one element after division is arranged at the center, and the other elements are symmetrical on both sides. Are arranged in a horizontal line, or are arranged in a horizontal line such that elements having a small total width are on the inside. In the case where all the relative ratios are even numbers, the elements are arranged in a horizontal line so that the element having the smaller total width is inside. The relative ratio here will be described later.

Next, a layout method of the transistors A, B, and C will be described. The flowcharts shown in FIGS. 2 and 3 are roughly divided into the following (a) to (d). (a) calculating the maximum division size of the relative precision element size,
The comparison with the minimum division size determined by the designer is performed. (b) Identify the relative ratios, classify them into three cases, and arrange them horizontally. (c) If placement is not possible in the restricted area,
The relative accuracy element is further divided and arranged in an increased number of stages in the vertical direction. (d) As shown in S of FIGS. 10 and 11, layout patterns including the same wiring are divided into blocks, arrayed in the horizontal direction, and connected to the same nodes as in the actual layout diagram shown in FIG. I do.

In the flowcharts shown in FIGS. 2 and 3, W of each transistor is A: B: C = 10.
Assume 0: 200: 400. (Step 101): A circuit is designed. (Step 102): Circuit information is confirmed. Here, each transistor A, which is an element requiring relative accuracy,
Confirm the dimensions of B and C and the connection between the elements. (Step 103): The arrangement area is restricted. Here, the designer determines an arrangement area on the layout of the element group that requires relative accuracy. For example, within XXμm in the vertical direction,
It is set so as to be within OO μm in the horizontal direction. (Step 104): The minimum division size for dividing the element is determined. That is, each of the transistors A, B, C
Since the influence of the dispersion of W increases when W is divided too much, the designer determines the minimum division size in the W direction. However, the greater the number of element divisions, the greater the degree of freedom in the shape of the entire relative precision element group.

(Step 105): W of relative accuracy element
The greatest common divisor of the size is taken, and the divisible element size and the relative ratio are calculated. In dividing the element for relative placement,
Calculate the maximum size that can be divided and the relative ratio. In this example, W = 100 μm and the relative ratio A: B: C = 1: 2: 4. (Step 106): The element size is compared with the minimum division size. Here, the designer compares the minimum division size determined in (Step 104) with the division element size calculated in (Step 105). When the element size is smaller than the minimum division size, the process proceeds to (Step 107), and when the element size is larger than the minimum division size,
Move to (Step 109). (Step 107): It is determined whether the restriction on the minimum division size can be reduced. Here, it is determined whether the minimum division size determined in (Step 104) can be reduced. If it is determined that the size can be reduced, the process proceeds to (Step 104), and if it is determined that the size cannot be reduced, (Step 10).
Go to 8).

(Step 108): The relative ratio is reexamined. That is, when the minimum division size determined in (Step 104) cannot be reduced in (Step 107), the element size requiring relative accuracy is reexamined, and the process returns to the circuit design in (Step 101). (Step 109): The element is divided. That is,
The relative precision element is divided into element sizes calculated in (Step 105).

(Step 110): The relative ratio is identified. That is, there are the following three cases of the relative ratio,
Identify these. When the relative ratio is odd one element When the relative ratio is odd two or more elements When the relative ratio is all even

In the present embodiment, the case of 1: 2: 4 is identified. (Step 111): If there is one element whose relative ratio is an odd number (in the case of), only one element after division is arranged at the center, and the other elements are arranged on both sides symmetrically in a horizontal line. To go. That is, as shown in FIG. 4, the transistor A is disposed at the center as A-1, and the transistor B is divided into B-1 and B-2 and disposed on both sides of A-1,
The transistor C is divided into C-1, C-2, C-3, and C-4, and is disposed symmetrically outside B-1 and B-2. In the arrangement patterns of the dividing elements shown in FIGS. 4 to 7, each of the squares is a divided transistor alone, and A, B, and C in the frames are the transistors A, B, and C in FIG. 1, respectively. Corresponds to C. The same elements have the same alphabet. The number after the alphabet is the number after division.

(Step 112): If there are two or more elements whose relative ratios are odd, the size of the divided elements is reduced to １ ／. Here, assuming that W of the transistors A, B, and C in FIG. 1 is A: B: C = 100: 300: 50.
When 0, the basic W = 100 μm and the relative ratio is 1: 3:
It becomes 5. At this time, the basic W = 50 μm (W / 2), the relative ratio is set to 2: 6: 10, and the process returns to (Step 106). (Step 113): When the relative ratios are all even-numbered elements (in the case of), the elements having a small W of TOTAL are arranged in a horizontal row so as to be inside. In other words, in the case where all the relative ratios are even-numbered elements, this is only the case where the process of (Step 112) is performed once. Assuming that W = 100 μm and the relative ratio is 2:
In the case of 2: 4, they are arranged as shown in FIG. this is,
This is because if elements with a small number of divisions are remotely arranged, the absolute accuracy will be reduced. Elements with a small W of TOTAL are arranged in a row so as to be inside.

(Step 114): It is determined whether or not it is within the placement area. Here, it is determined whether or not it is within the arrangement area restricted in (Step 103). If it is determined that it is within the arrangement area, the process proceeds to (Step 118), and if it is determined that it does not enter the arrangement region, the process proceeds to (Step 115). (Step 115): The W of the transistors is halved, the number of stages is doubled, and the transistors are stacked. As shown in FIG. 6, the W of the transistor is halved and the number of transistors is doubled. In other words, those arranged in one horizontal row are arranged in two stages, and those arranged in two stages are arranged in four stages as shown in FIG.
Arrange them in columns. (Step 116): The element size is compared with the minimum division size. Here, the minimum division size determined by the designer in (Step 104) is compared with the element size divided in half in (Step 115). When the element size is smaller than the minimum division size, the process proceeds to (Step 117), and when the element size is larger than the minimum division size, the process proceeds to (Step 114).

(Step 117): The arrangement area is increased. That is, as a result of the comparison in (Step 116),
If the element size divided in half in (Step 115) is smaller than the minimum division size determined in (Step 104) by the designer, the arrangement area restricted by the designer is increased,
Return to (Step 109). (Step 118): The divided elements are arranged in the vertical direction. That is, as a result of the comparison in (Step 114),
When entering the arrangement area, transistors of the current basic size are arrayed in the vertical direction. At this time, as shown in the layout of FIG. 10, by sharing the field which is the source or drain of the vertically adjacent transistors, the area in the vertical direction can be reduced. That is, a layout pattern of elements arranged in the vertical direction shown in S of FIG. 7 is created.

(Step 119): Wiring is performed. Here, as shown in the layout of FIG. 10, every other field which is a source or a drain of a transistor is connected by wiring, and a gate is connected. (Step 120): A layout pattern including wiring is arrayed. Here, as shown in the layout of FIG. 11, layout patterns including the wirings of FIG. 10 are arrayed in the horizontal direction. (Step 121): Wiring is performed. That is, the same node (for example, the gates of the transistors A, B, and C and the drain of the transistor A) in the layout pattern arrayed in (Step 120) is connected to the upper or lower part of the element. By such relative arrangement, the relative variation of the elements can be suppressed, and a layout pattern with a relative accuracy can be created with a short TAT.

As described above, in the first embodiment, the element requiring relative accuracy is divided into a plurality of elements, and the transistors A,
B and C, these divided elements are symmetrically arranged around a certain point according to the relative ratio, and a layout pattern including wiring is arrayed. As a result, it is possible to ensure the relative accuracy of the elements required for the circuit characteristics. Further, the congestion degree of the wiring can be made uniform. In addition, the arrangement and wiring area can be formed into a well-formed rectangle. In addition, since layout patterns are generated regularly, the layout and wiring can be easily automated, and the development period can be shortened.

(Second Embodiment) (Step 114)
In the case where the orientation of the element to be arranged may be either,
After judging whether the direction of the element group arranged in a row is rotated by 90 ° and enters the arrangement area, the elements are arranged. (Third Embodiment) In (Step 115), W
Has been described, and the number of stages has been doubled and arranged. In this method, the arrangement is one-stage, two-stage, four-stage, eight-stage,..., But it is also possible to make W one-third of the basic size and to arrange three stages. Also, W
Is set to 1/5 of the basic size, and can be stacked and arranged in five stages.

(Fourth Embodiment) As shown in FIG.
After the layout pattern is created according to the flow, unused dummy elements (the same size as the elements used) are added to the periphery, so that the correction by changing the relative ratio can be performed only by the above correction. In addition, the position where the dummy element is arranged may not be around. For example, as shown in FIG. 9, if the arrangement is symmetrical in the vertical and horizontal directions, the same effect can be obtained even if the elements are arranged in rows or columns between the elements used. In each of the above embodiments, the case where the present invention is applied to a MOS transistor has been described. However, the present invention is not limited to this example.
It goes without saying that the same effect can be obtained even with an active element or a passive element.

[0024]

As described above, according to the semiconductor integrated circuit and the layout method thereof according to the present invention, an element requiring relative accuracy is divided into a plurality of elements, and these divided elements are converted into one point according to the relative ratio. Since the layout patterns are arranged symmetrically at the center and the layout patterns including the wirings are arrayed, a layout pattern with relative accuracy maintained can be designed with a short TAT.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a case where a semiconductor integrated circuit of the present invention is applied to a current mirror circuit.

FIG. 2 is a flowchart illustrating a layout method of the current mirror circuit of FIG. 1;

FIG. 3 is a flowchart illustrating a layout method of the current mirror circuit of FIG. 1;

FIG. 4 is a diagram showing an example of the arrangement of elements according to the layout method of FIGS. 2 and 3;

FIG. 5 is a diagram showing an example of element arrangement according to the layout methods of FIGS. 2 and 3;

FIG. 6 is a diagram showing an example of the arrangement of elements according to the layout method shown in FIGS. 2 and 3;

FIG. 7 is a diagram showing an example of the arrangement of elements according to the layout method of FIGS. 2 and 3;

8 is a diagram showing an example of the arrangement of elements according to the layout methods of FIGS. 2 and 3. FIG.

FIG. 9 is a diagram showing an example of the arrangement of elements according to the layout method of FIGS. 2 and 3;

FIG. 10 is a diagram showing an example of the arrangement of elements according to the layout methods of FIGS. 2 and 3;

FIG. 11 is a diagram showing an example of the arrangement of elements according to the layout methods of FIGS. 2 and 3;

FIG. 12 is a diagram showing an example of the arrangement of a conventional semiconductor element.

FIG. 13 is a diagram showing an example of a conventional semiconductor device manufacturing process.

[Explanation of symbols]

 A, B, C transistor

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[Procedure amendment]

[Submission date] July 2, 1999 (1999.7.2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

[0008]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit, wherein an element requiring relative accuracy is divided into a plurality of elements, and these divided elements are symmetrical about a certain point according to a relative ratio. a semiconductor integrated circuit formed by arranging, when element relative ratio is odd one, only one element after divided centrally located and the other element a horizontal row symmetrically on both sides It is characterized by being arranged in. When the relative ratio is an odd number of two or more elements, the size of the divided element is reduced to half, and only one element after division is arranged at the center, and the other elements are symmetrical on both sides. May be arranged in a horizontal line, or the elements having a small total width may be arranged in a horizontal line so as to be inside. The layout method of a semiconductor integrated circuit according to claim 3, wherein a first step of calculating a maximum division size of the relative accuracy element and a step of comparing the maximum division size with the restricted minimum division size;
After identifying the relative ratio based on the three cases, a second step of arranging the divided elements in a horizontal line, a third step of determining whether or not the divided elements fall within the arrangement area, If it does not fall within the placement area, the fourth step of further dividing the divided elements and increasing the number of stages in the vertical direction is performed, and the layout pattern including the same wiring is divided into blocks and arrayed. And a fifth step of performing the following. In addition, the three cases are the case where the relative ratio is one odd number, the case where the relative ratio is two or more, and the case where all the relative ratios are even. Can be. Further, in the third step, if the orientation of the elements to be arranged is irrelevant, it is determined whether or not the orientation of the element group arranged in a row is rotated by 90 ° to enter the arrangement area, and then the elements are arranged. Steps may be included. In addition, the fifth step may include a step of adding a dummy element having the same size as an unused element around the layout pattern after creating the layout pattern. In the semiconductor integrated circuit and the layout method thereof according to the present invention, when an element requiring relative accuracy is divided into a plurality of elements, and when these divided elements are symmetrically arranged around a certain point according to the relative ratio , the relative Odd ratio
If the number of elements is one, for example, one element after division
Only the element is placed in the center, and the other elements are
Layout including wiring by symmetrically arranging horizontally
Array patterns.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

[0024]

As described above, according to the semiconductor integrated circuit and the layout method thereof according to the present invention, an element requiring relative accuracy is divided into a plurality of elements, and these divided elements are converted into one point according to the relative ratio. When symmetrically arranged at the center , the relative ratio
If the number of odd elements is one, for example, one
Only the element is placed in the center and the other elements are on both sides on the left
Since the layout patterns including wirings are arrayed by arranging them in a horizontal line symmetrically to the right, it is possible to design a layout pattern with relative accuracy maintained with a short TAT.

Claims (8)

[Claims] 1. An element requiring relative accuracy is divided into a plurality of elements.
A semiconductor integrated circuit characterized in that these divided elements are symmetrically arranged around one point according to a relative ratio. 2. In the case where the number of elements having an odd relative ratio is one, only one element after division is arranged in the center, and the other elements are arranged on both sides symmetrically in a horizontal line. The semiconductor integrated circuit according to claim 1, wherein: 3. When the relative ratio is an odd number of two or more elements, the size of the divided element is halved, and only one element after the division is arranged at the center, and the other elements are 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is arranged symmetrically on both sides in one horizontal line, or arranged in one horizontal line so that elements having a small total width are on the inside. 4. The semiconductor integrated circuit according to claim 1, wherein when the relative ratios are all even elements, the elements having a smaller total width are arranged in a row so as to be inside. 5. A first step of calculating a maximum division size of a relative precision element, a step of comparing the maximum division size with a restricted division size, and identifying a relative ratio based on three cases, and then dividing the division element. A second step of arranging the divided elements in a horizontal line, and a third step of determining whether or not the divided elements fall within an arrangement area.
And the fourth step of further dividing the divided elements and increasing the number of stages in the vertical direction when the divided elements do not fall within the arrangement region; and forming a layout pattern including the same wiring into blocks. And a fifth step of connecting the same node after arraying the semiconductor integrated circuits. 6. The three cases refer to a case where one element has an odd relative ratio, two or more elements having an odd relative ratio, and a case where all the relative ratios are even. 6. The layout method for a semiconductor integrated circuit according to claim 5, wherein: 7. In the third step, in a case where the orientation of the elements to be arranged is irrelevant, it is determined whether or not the orientation of the element group arranged in a row is rotated by 90 ° to enter the arrangement area. 6. The layout method for a semiconductor integrated circuit according to claim 5, further comprising the step of arranging the semiconductor integrated circuit. 8. The method according to claim 5, wherein the fifth step includes a step of, after creating a layout pattern, adding a dummy element having the same size as an unused element around the layout pattern. Layout method of a semiconductor integrated circuit.