JP3527483B2 - CMOS basic cell, semiconductor integrated circuit using the same, and method of manufacturing the semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS type basic cell and a method of manufacturing a gate array type semiconductor integrated circuit using the basic cell.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have tended to become more highly integrated and have higher performance in accordance with the miniaturization of processes, and accordingly, the development cost and the development period have been steadily increasing. In such a situation, the gate array can be designed by simply changing the wiring pattern using CAD (Computer-Aided Design), etc., which is suitable for shortening the product development period, cost reduction, or high-mix low-volume production. As a method for manufacturing a semiconductor integrated circuit, it has a wide range of applications.

As a method of manufacturing a gate array, a basic cell having a predetermined layout pattern and a wiring pattern of a logic cell using one or more of the basic cells are prepared in advance, and the basic cell is prepared. C automatic placement and automatic wiring between the automatically placed basic cells
A method performed using AD or the like is common.

FIG. 30 shows a configuration diagram of a conventional CMOS type basic cell composed of four transistors. In the figure, 1 is a CMOS type basic cell. In this basic cell 1, the first P-channel transistor TP1
Has a gate electrode 2A arranged in a katakana "U" shape in a plane and impurity diffusion layers 3A and 4A provided on both sides of the gate electrode 2A. The impurity diffusion layers 3A and 4A serve as a source and a drain. Second P
The channel transistor TP2 is the transistor T
The inverted “U” -shaped gate electrode 5A arranged in the opposite direction to the gate electrode 2A of P1, the impurity diffusion layer 6A provided on one side of the gate electrode 5A, and the impurity diffusion layer 4A shared with the transistor TP1. And have. Also,
The first N-channel transistor TN1 has a gate electrode 2B arranged in a katakana "U" shape in a plane, and impurity diffusion layers 3B and 4B provided on both sides of the gate electrode 2B. The impurity diffusion layers 3B and 4B
Becomes a source or drain. Further, the second N-channel transistor TN2 includes an inverted “U” -shaped gate electrode 5B arranged in the opposite direction to the gate electrode 2B of the transistor TN1, and an impurity diffusion layer provided on one side of the gate electrode 5B. 6B and the impurity diffusion layer 4B shared with the transistor TN1. In addition, 7 and 8
Are global power supply patterns and GND (ground) patterns provided on the upper and lower ends in the figure and formed on the first wiring layer.

In FIG. 30, the dot lines in the basic cell 1 are wiring grids. Here, the wiring grid means a place where the wiring pattern of the logic cell is arranged as a wiring track. The wiring grid is the basic cell 1
Of the gate electrodes 2A, 2B, 5A, 5B, the impurity diffusion layers 3A, 3B, 4A, 4B, 6A, 6B, the power supply pattern 7, and the GND pattern 8 are arranged so as to cross each other, and their mutual intervals are Is determined by the arrangement pitch of the transistors or the pitch of the wiring determined by the rules of the semiconductor manufacturing process.

The wiring is arbitrarily determined so as to lie on the wiring grid at the design stage of the logic cell, and at the design stage of the semiconductor integrated circuit using a plurality of logic cells, the wiring is arranged on the wiring grid by the CAD system or the like. Will be placed. In the design stage, when wiring is performed using two wiring layers, the wiring pitch of the second layer is set to the first wiring in order to facilitate connection with the wiring of the first layer. Generally, it is set to the same pitch as the wiring pitch of the layer. The same applies to the wiring pitch when wiring is performed using the third and higher wiring layers. In FIG. 30, the X-direction wiring track of the basic cell 1 is 11 and the Y-direction wiring track is 3.

[0007]

However, the above-mentioned conventional basic cell has the following problems. That is, for example,
When the circuit example of the DFF (D-type flip-flop) shown in FIG. 2A is configured by using the basic cell shown in FIG. 30, the first layer wiring and the second layer wiring are logically arranged. When used as a wiring for a cell, the layout configuration shown in FIG. 31 (a) or (b) is obtained. The wiring layer used in this case is, in addition to the first wiring layer and the second wiring layer,
A total of three layers including the VIA layer connecting the first wiring layer to the second wiring layer are required.

Further, as disclosed in, for example, Japanese Patent Application Laid-Open No. 1-270329, the wiring of the first layer is not used as the wiring for the logic cell but is a fixed wiring, and only the wiring of the second layer is for the logic cell. When used as a wiring, the layout configuration is as shown in FIG. The wiring layer used in this case is
Since the wiring is crowded, in addition to the second wiring layer, an upper third wiring layer and a VIA layer connecting the second wiring layer to the third wiring layer are necessary. It becomes a total of 3
You need two layers.

Regarding the VIA for connecting the gate electrode or the impurity diffusion region to the wiring of the first layer, the basic cell shown in FIG. 30 or the circuit configuration example shown in FIGS. 31 (a) and 31 (b) is used. Needless to say, it is of course necessary including the examples mentioned below, but since it is not directly related to the essence of the present invention, its explanation and illustration are omitted. Here, FIG.
2B is a symbol diagram of the DFF shown in FIG.
(C) is an operation timing chart. In FIGS. 2A and 2B, 100 is a DATA input terminal, 110 is a CLK input terminal, 120 is an inverted CLK input terminal, and 200.
Is a DATA output terminal, and 210 is an inverted DATA output terminal.

A layout diagram in which another logic cell is formed by using the basic cell is shown below. FIG. 33 shows FIG. 4 (a).
When the example of the buffer circuit shown in FIG. 30 is configured using the basic cell shown in FIG. 30, the layout configuration when the first layer wiring and the second layer wiring are used as the logic cell wiring Indicates. When the first-layer wiring is fixed wiring and only the second-layer wiring is used as the logic cell wiring, the layout configuration shown in FIG. 34 is obtained.

Further, FIG. 35 shows the OR shown in FIG.
FIG. 32 shows a layout configuration when the NAND circuit is configured using the basic cell shown in FIG. 30 and the first layer wiring and the second layer wiring are used as logic cell wiring. In addition, the wiring of the first layer is fixed wiring
When only the wiring of the layer is used as the wiring for the logic cell, the layout configuration shown in FIG. 36 is obtained.

In addition, FIG. 37 shows the wiring of the first layer and the wiring of the second layer when the selector circuit shown in FIG. 8A is constructed by using the basic cell shown in FIG. This is a layout configuration when and are used as the wiring for the logic cell. When the first layer wiring is used as a fixed wiring and only the second layer wiring is used as a logic cell wiring,
The layout configuration shown in FIG. 38 is obtained.

Further, FIG. 39 shows the wiring of the first layer and the wiring of the second layer when the SRAM circuit shown in FIG. 25A is constructed using the basic cell shown in FIG. This is a layout configuration when and are used as the wiring for the logic cell. When the first layer wiring is used as the fixed wiring and only the second layer wiring is used as the logic cell wiring, the layout configuration shown in FIG. 40 is obtained.

As described above, when the conventional basic cell shown in FIG. 30 is used to form a logic circuit having a clock signal line like a DFF, or a transistor is connected in parallel like a buffer circuit. A logical circuit having a control signal line such as a selector circuit, or a logical circuit for a memory such as SRAM. In the case of the configuration, in any case, two wiring layers are required only by the wiring layer. As a result, the wiring track for the upper wiring is consumed, and the wiring congestion degree at the time of designing the semiconductor integrated circuit is promoted. As a result, the gate usage rate of the gate array is reduced, and the integration degree of the semiconductor integrated circuit is reduced. There is a problem of decrease. Furthermore,
When logic changes or wiring changes occur, the correction layer
The need for a total of three layers, that is, two wiring layers and VIA layers, poses a problem for shortening the product development period and cost reduction, which are the greatest advantages of the gate array.

When a D-type flip-flop circuit with a scan function as shown in FIG. 20A is constructed by using the basic cell shown in FIG. 30, the wiring of the first layer and the wiring of the second layer are used. When is used as the wiring for the logic cell,
The layout configuration shown in FIG. 41 is obtained. Here, FIG.
As shown in (c), when a semiconductor integrated circuit is configured using three D-type flip-flop circuits DFF1 to DFF3 with a scan function and a combinational logic circuit LC, the D-type flip-flop circuit of the preceding stage ( For example DFF
It is common to use the scan chain method in which the output terminal Q of 1) is connected to the scan data input terminal DT of the D-type flip-flop circuit (for example, DFF2) in the subsequent stage via the wiring L. FIG. 20D shows a timing chart of the normal operation in that case, and FIG. 2 shows a timing chart of the scan operation in that case.
It is shown in 0 (e). During normal operation, the data output from the output terminal Q of the D-type flip-flop circuit of the preceding stage propagates to the data input terminal D of the D-type flip-flop circuit of the succeeding stage via the combinational logic circuit LC. Type flip-flop circuit has a margin in data hold time. On the other hand, during the scan operation, the output data of the output terminal Q of the D-type flip-flop circuit of the preceding stage is propagated to the scan-data input terminal DT of the D-type flip-flop circuit of the succeeding stage via only the line L, so that the scan data Propagation delay time is short and there is little margin in hold time,
There is a problem that a scan data hold error is likely to occur. Therefore, the wiring L is lengthened to make the wiring delay time longer.

However, when a D-type flip-flop circuit with a scanning function is constructed using the conventional basic cell shown in FIG. 30, the wiring layer used for delay adjustment is the first wiring layer. In addition, a total of two wiring layers of the second wiring layer are required. Further, since the wiring delay amount per unit length is different between the first and second wiring layers, it takes time to design the wiring delay adjustment. These drawbacks hinder the greatest advantage of the gate array, that is, the cost reduction of the product and the shortening of the development period.

Further, in US Pat. No. 5,814,844,
In a CMOS type basic cell, an auxiliary wiring used when connecting gate electrodes in the basic cell or connecting the gate electrode and the diffusion region is arranged in advance in a polysilicon layer (hereinafter referred to as a gate layer) in which the gate electrode is formed. If it is necessary to connect, for example, the gate electrode and the diffusion region in its own basic cell, the wiring connected to this gate electrode and the wiring connected to the diffusion region are located above the gate electrode. A configuration is disclosed in which the wirings are arranged in the wiring layer, and the both wirings are connected to the auxiliary wiring through two via holes. However, the auxiliary wiring is a wiring arranged in the gate layer and is used for connecting gate electrodes to each other in their own basic cells, connecting gate electrodes to diffusion regions, and the like. It is not used as part of global wiring for connecting gate electrodes of individual basic cells.

By the way, the speed and power consumption of the DFF are limited by the wiring length and parasitic capacitance determined according to the size and configuration of the basic cell. In order to speed up the operation and reduce the power consumption without changing the size of the basic cell itself, for example, in Japanese Unexamined Patent Publication No. 07-240501, the diffusion region is limited to be narrower than the contact region except the contact region. Then, a method of reducing the diffusion capacitance is disclosed, but there is a problem that the wiring tracks are reduced, and in order to solve this problem, it is necessary to devise a process for securing the wiring tracks. .

Further, for example, Japanese Patent Application Laid-Open No. 09-181284 discloses a method of shortening the signal propagation delay time to increase the speed by overlapping the contact regions of adjacent basic cells, but this technique is also applicable. The reduction of wiring tracks becomes a problem.

An object of the present invention is to realize a desired logic circuit with only one wiring layer as a wiring layer without increasing the area of a basic cell, and to hold error of a flip-flop circuit with a scan test function. It is an object of the present invention to provide a CMOS type basic cell capable of implementing the countermeasures and a method for manufacturing a semiconductor integrated circuit using the CMOS type basic cell.

Another object of the present invention is to provide a CMOS type basic cell capable of realizing high speed operation and low power consumption by reducing the layout area of the basic cell while sufficiently securing wiring tracks. It is to provide a method for manufacturing a semiconductor integrated circuit using the.

[0022]

In order to achieve the above object, according to the present invention, when a plurality of CMOS type basic cells are arranged in parallel to manufacture a semiconductor integrated circuit, a global structure is provided above these basic cells. Since the wiring layer for wiring is provided, the wiring layer located immediately below this wiring layer (that is,
A wiring pattern is previously incorporated in the uppermost wiring layer in each CMOS type basic cell, and the basic cells are also connected by global wiring using the wiring pattern.

Further, in the present invention, in order to achieve the above-mentioned other objects, an N-channel transistor or a P-channel transistor of a basic cell is provided.
The layout of the semiconductor integrated circuit obtained by arranging a plurality of basic cells is reduced by specially forming the shape of the gate of the channel transistor and the diffusion region.

Specifically, the CMOS of the invention according to claim 1
Type basic cell, and a N-channel tiger <br/> Njisu data and P-channel transistors Te semiconductor substrate smell, gate
CMOS for forming an array type semiconductor integrated circuit
In type basic cell, between the N-channel transient is te and <br/> the P-channel transistor motor, and the N
Channel transient scan data及 beauty P-channel transient scan data
And a wiring pattern that exists independently of the CMOS basic cell and another CMOS type basic pattern.
1 provided in the CMOS type basic cell that can be connected to a cell
It is characterized in that it is formed in the uppermost wiring layer among the two or more wiring layers .

The invention of claim 2 is the same as that of claim 1.
In the CMOS type basic cell of, the wiring pattern is
The N-channel transistor and the P-channel transistor
Extending in a direction vertical or horizontal to the boundary with the register
It is characterized by

The invention according to claim 3 is the same as claim 1 or
2. In the CMOS basic cell described in 2,
The basic cell consists of a power supply pattern, a ground pattern, and
Having another wiring pattern different from the wiring pattern,
The N-channel transistor and the ground pattern
Between the N-channel transistor and the P
Extend in a direction horizontal to the boundary with the channel transistor
And the N-channel transistor region and P-channel
Other than the above, which exists independently of the channel transistor region.
A wiring pattern, and the other wiring pattern is the C
One or two or more wiring layers provided in the MOS basic cell
It is characterized in that it is formed on the uppermost wiring layer.

The invention according to claim 4 is the same as claim 3.
In the CMOS type basic cell of
Are adjacent to each other when the CMOS type basic cells are adjacent to each other.
Is electrically connected to.

The invention according to claim 5 is the same as claim 1,
In the CMOS type basic cell described in 2, 3 or 4,
The wiring pattern is such that the CMOS type basic cells are adjacent to each other.
It is characterized in that they are electrically connected to each other when they are turned on.

A semiconductor integrated circuit according to a sixth aspect of the invention is
A plurality of CMOSs according to claim 1, 2, 3, 4 or 5.
Type basic cell is located above the wiring pattern
Characterized by being electrically connected by wiring
It

The invention according to claim 7, a plurality arranged basic cells, which like the semiconductor integrated circuit of the gate array type of the semiconductor integrated circuit by disposing a wiring one upper to upper layer of the basic cell of A method of manufacturing a semiconductor substrate comprising:
A plurality of CMOS type basic cells according to claim 1, 2, 3, 4 or 5 are arranged, and a wiring pattern formed in an uppermost wiring layer of each CMOS type basic cell and the upper wiring are used. , A logic circuit having a clock signal line is realized.

The invention according to claim 8, a plurality arranged basic cells, which like the semiconductor integrated circuit of the gate array type of the semiconductor integrated circuit by disposing a wiring one upper to upper layer of the basic cell of A method of manufacturing a semiconductor substrate comprising:
A plurality of CMOS type basic cells according to claim 1, 2, 3, 4 or 5 are arranged, and the wiring pattern formed on the uppermost wiring layer of each CMOS type basic cell and the upper wiring layer are used. Thus, a logic circuit having a portion in which transistors are connected in parallel is realized.

[0032] The invention of claim 9, wherein the plurality arranged basic cells, which like the semiconductor integrated circuit of the gate array type of the semiconductor integrated circuit by disposing a wiring one upper to upper layer of the basic cell of A method of manufacturing a semiconductor substrate comprising:
A plurality of CMOS type basic cells according to claim 1, 2, 3, 4 or 5 are arranged, and a wiring pattern formed in an uppermost wiring layer of each CMOS type basic cell and the upper wiring are used. , To realize a composite logic circuit.

The invention of claim 10, wherein the gate array method by arranging a plurality basic cell constituting the semiconductor integrated circuit by disposing a wiring <br/> of one upper to upper layer of the basic cell of this such a manufacturing method of a semiconductor integrated circuit, prior to the semiconductor substrate
A plurality of CMOS type basic cells according to claim 1, 2, 3, 4 or 5 are arranged, and the wiring pattern formed in the uppermost wiring layer of each CMOS type basic cell and the upper wiring are used. And a logic circuit having a control signal line is realized.

The invention of claim 11, wherein the gate array method by arranging a plurality basic cell constituting the semiconductor integrated circuit by disposing a wiring <br/> of one upper to upper layer of the basic cell of this such a manufacturing method of a semiconductor integrated circuit, prior to the semiconductor substrate
A plurality of CMOS type basic cells according to claim 1, 2, 3, 4 or 5 are arranged, and the wiring pattern formed in the uppermost wiring layer of each CMOS type basic cell and the upper wiring are used. And realize a logic circuit for memory.

The invention according to claim 12, a gate array method by arranging a plurality basic cell constituting the semiconductor integrated circuit by disposing a wiring <br/> of one upper to upper layer of the basic cell of this such a manufacturing method of a semiconductor integrated circuit, prior to the semiconductor substrate
A plurality of CMOS type basic cells according to claim 1, 2, 3, 4 or 5 are arranged, and the wiring pattern formed in the uppermost wiring layer of each CMOS type basic cell and the upper wiring are used. Thus, a flip-flop circuit with a scan function is realized .

According to a thirteenth aspect of the present invention, in the CMOS type basic cell, an N-channel transistor and a P-type are provided on a semiconductor substrate.
CMOS having a channel transistor and using other basic cells of the same configuration on the left side and the right side respectively
In the basic cell, the upper end of at least one of the diffusion region of the N-channel transistor and the diffusion region of the P-channel transistor is bent to one side.
It is characterized in that it is formed in a hook-shaped structure having a bent portion and a second bent portion whose lower end portion bends to the other side.

According to a fourteenth aspect of the present invention, in the CMOS type basic cell, an N-channel transistor and a P-type transistor are provided on a semiconductor substrate.
CMOS having a channel transistor and using other basic cells of the same configuration on the left side and the right side respectively
In the basic cell, at least one of the gate of the N-channel transistor and the gate of the P-channel transistor has a first bent portion having an upper end bent to one side and a second bent portion having a lower end bent to the other side. A first bent portion having an upper end bent to one side at least one of the diffusion region of the N-channel transistor and the diffusion region of the P-channel transistor. And a lower end portion having a second bent portion that bends to the other side, the hook-shaped structure is formed.

The invention according to claim 15 is the same as claim 14 above.
In the described CMOS basic cell, the first N
A channel transistor and a first P-channel transistor are formed, a second N-channel transistor is formed beside the first N-channel transistor, and a second N-channel transistor is formed beside the first P-channel transistor. Is formed, and the gates of the two N-channel transistors and the two P-channel transistors are formed in the hook-shaped structure.

The invention according to claim 16 is the above-mentioned claim 15.
In the CMOS basic cell described, the gates of the two N-channel transistors and the gates of the two P-channel transistors have a first bent portion of one gate and a second folded portion of the other gate. It is characterized in that the curved portion is formed so as to overlap from the same position in the horizontal direction when viewed in the vertical direction.

The invention according to claim 17 is the above-mentioned claim 15.
In the described CMOS basic cell, the first and second
And one diffusion region between the N-channel transistors and one diffusion region between the first and second P-channel transistors.
A shared diffusion region located between both gates and shared by both transistors, a first dedicated diffusion region located on the opposite side of the gate of the first transistor from the shared diffusion region, and the second diffusion region. The transistor is divided into a second dedicated diffusion region located on the opposite side of the gate of the transistor from the shared diffusion region, the first bent portion is formed in the first dedicated diffusion region, and the second dedicated diffusion region is formed. The second bent portion is formed in the diffusion region.

The invention according to claim 18 is the same as claim 1.
In the CMOS type basic cell described in 3, 14, 15, 16 or 17, a fixed wiring area in which a power supply wiring and a ground wiring are arranged is provided outside a transistor area in which the N-channel transistor and the P-channel transistor are arranged. It is characterized by

The invention according to claim 19 is the same as claim 1.
CMOS type according to 3, 14, 15, 16, 17 or 18
Met gate array type semiconductor integrated circuit comprising a standard cell
Then, the first bent portion of the gate of the P-channel transistor and the first bent portion of the diffusion region of the P-channel transistor of the CMOS basic cell adjacent thereto are electrically connected by the upper wiring. , The upper wiring is
It extends in a direction perpendicular to a boundary line between the N-channel transistor and the P-channel transistor.

A method of manufacturing a semiconductor integrated circuit according to a twentieth aspect of the present invention is a method of manufacturing a gate array type semiconductor integrated circuit in which a plurality of basic cells are arranged in a lateral direction to form a semiconductor integrated circuit. Claims 13, 14, 15, 1
The CMOS type basic cell described in 6, 17, or 18 is replaced by a C
In order that the first bent portion of the MOS type basic cell and the second bent portion of the CMOS type basic cell arranged on the side of this basic cell may overlap when viewed in the vertical direction from the same position in the horizontal direction, It is characterized by overlapping and arranging in the lateral direction.

According to a twenty-first aspect of the semiconductor integrated circuit of the invention.
The manufacturing method is such that the N-channel transistor is formed on the semiconductor substrate.
It has a gate transistor and a P-channel transistor.
CMOS type for forming a ray-type semiconductor integrated circuit
In the basic cell, in front of the N-channel transistor
Between the P channel transistor and the N channel
What are channel transistors and P-channel transistors?
The wiring pattern has an independently existing wiring pattern.
Are CMOS basic cells and other CMOS basic cells
1 provided in the CMOS type basic cell for connecting to
Layer or the uppermost wiring layer of two or more wiring layers
If a plurality of the CMOS type basic cells are arranged,
A plurality of CMs are provided by wiring above the wiring pattern.
Characterized by electrically connecting OS-type basic cells to each other
It

The invention according to claim 22 is the same as claim 21.
In the method for manufacturing a semiconductor integrated circuit described above, the wiring pattern
The turn includes the N-channel transistor and the P-channel transistor.
In the direction vertical or horizontal to the boundary line with the channel transistor
It is characterized by extending.

The invention according to claim 23 is the same as claim 21.
Alternatively, in the method for manufacturing a semiconductor integrated circuit according to 22,
The CMOS basic cell has a power supply pattern and a ground pattern.
Turns and other wiring patterns different from the wiring pattern
The N-channel transistor and the graph
And the N-channel transition
Horizontal to the boundary between the star and the P-channel transistor
Direction, and the N-channel transistor region
And exists independently of the P-channel transistor region
The other wiring pattern,
Is one layer or two or more layers included in the CMOS basic cell
Of the above wiring layers, it is formed on the uppermost wiring layer
And

The invention according to claim 24 is the same as claim 2
1. The method for manufacturing a semiconductor integrated circuit according to 1, 22, or 23.
The wiring pattern is such that the CMOS type basic cells are adjacent to each other.
It is characterized in that they are electrically connected to each other when they are turned on.

The invention of claim 25 is the same as that of claim 2.
Manufacturing method of semiconductor integrated circuit according to 1, 22, 23 or 24
Method, a plurality of the CMOS type basic cells are connected to the wiring
Electricity is provided by higher-level wiring that is located above the pattern.
It is characterized in that they are physically connected.

From the above, the claims 1 to 12 and the contract are obtained.
In the inventions according to claim 21 to claim 25 , a plurality of CMOs are provided.
When a semiconductor integrated circuit is manufactured by the gate array method using the S-type basic cells, the wiring pattern previously incorporated in the uppermost wiring layer of each CMOS-type basic cell is used for wiring between the basic cells. Since it is used as a part, even a logic circuit having a complicated structure can be manufactured and realized by using only one wiring layer as a wiring layer. Therefore, the degree of wiring congestion of the wiring layer used for wiring at the time of designing the semiconductor integrated circuit is alleviated, the gate usage rate of the gate array is increased, and the integration degree of the semiconductor integrated circuit is improved.

Further, in the CMOS type basic cell and the method for manufacturing a semiconductor integrated circuit having a plurality of the basic cells arrayed according to claims 13 to 20 , the shape of the gate of the N-channel or P-channel transistor of the basic cell is changed. When a semiconductor integrated circuit is manufactured by forming a hook-shaped structure and arranging a plurality of basic cells in a lateral direction, the hook-shaped structure portion of the basic cell may be inserted into the hook-shaped structure portion of an adjacent basic cell. It is placed so that it partially overlaps. Therefore, this overlay effectively reduces the layout area of the manufactured semiconductor integrated circuit. Moreover, when the gates of the transistors of one of the basic cells and the diffusion regions of the other transistor are connected by the overlapping arrangement as described above, the wirings may be arranged in the vertical direction at the same position in the horizontal direction, It is not necessary to arrange the wiring in the horizontal direction. Therefore, the wiring length is reduced accordingly. Therefore, it is possible to reduce the layout area while sufficiently securing the wiring tracks, and to shorten the wiring length and reduce the diffusion capacitance to achieve higher speed operation and lower power consumption.

[0051]

1 to 29, a CMOS type basic cell according to an embodiment of the present invention and a semiconductor integrated circuit manufacturing method using the same will be described.

(First Embodiment) FIG. 1A shows a CMO according to a first embodiment of the present invention.
It is a block diagram of an S-type basic cell. The same basic cell is claimed in claim 1.
3 is a block diagram of the basic cell described in FIG. FIG. 2B shows an equivalent circuit diagram of the basic cell shown in FIG. Incidentally, reference numerals TP1, TP2, TN1, TN2, 1, 7, shown in FIG.
Since 8 and 2A to 6A and 2B to 6B have the same configuration as that of the conventional basic cell of FIG. 30, the same reference numerals are given and detailed description thereof will be omitted.

In this embodiment, the basic cell 1 shown in FIG. 1A has a wiring pattern 9 extending in a direction perpendicular to the boundary line between the N-channel transistor region and the P-channel transistor region. The wiring pattern 9 exists independently of the N and P channel transistor regions. Although the number of wiring patterns 9 is one in FIG. 1A, there may be a plurality of wiring patterns 9. FIG. 1C is the same as FIG.
1A-1A sectional view of the basic cell 1 of FIG. The same figure (c)
In the figure, 50 is a semiconductor substrate, 51 is a gate oxide film formed above the substrate 50.
Two gate electrodes 2A and 5A are formed on the. The wiring pattern 9 is arranged above the interlayer insulating film 52 covering the gate electrodes 2A and 5A, and two wirings 53 and 54 are arranged on the left and right sides of the wiring pattern 9 in the drawing. The two wires 53 and 54 are connected to the gate electrode 2A through the connection holes 55 and 56 provided in the interlayer insulating film 52, respectively.
5A is connected. Although not shown, the power supply pattern 7 and the GND pattern 8 are also formed above the interlayer insulating film 52.

When a plurality of the basic cells 1 are arranged in parallel to manufacture a semiconductor integrated circuit, the global wiring 60 is arranged as shown in FIG. 1 (d). In FIG. 3D, for simplicity, two basic cells are used, and the global wiring 6 is formed above the interlayer insulating film 57 that covers the wiring patterns 9 and 9.
0 is arranged, and the global wiring 60 and the wiring patterns 9 and 9 are formed in the interlayer insulating film 57 in the connection hole 58,
It is connected via 59. In the case of FIG. 1D, the wiring layer in which the wiring patterns 9 are arranged is the first wiring layer (the uppermost wiring layer), and the wiring layer 6 in which the global wiring 60 is arranged.
1 is the second wiring layer (additional wiring layer).

FIG. 1 (e) shows a basic cell 1'which is a modification of the basic cell 1 shown in FIG. 1 (a). In the basic cell 1 of FIG. 1A, the wiring pattern 9 is arranged in the first wiring layer, but in the basic cell 1 ′ of FIG. 1E, the wiring pattern 9 is arranged in the third wiring layer. That is, as shown in FIG. 1F, which is a cross-sectional view taken along the line 1E-1E of FIG.
A first wiring layer in which the wirings 53 and 54 are arranged, a wiring 65,
It has a second wiring layer in which 66 is arranged and a third wiring layer in which wires 67 and 68 are arranged, and the wiring pattern 9 is arranged in the third wiring layer. The wirings 53, 65 and 67 are connected to the gate electrode 2A, and the wirings 54, 66 and 68 are connected to the gate electrode 5A.

When a plurality of basic cells 1'shown in FIG. 1E are arranged in parallel to manufacture a semiconductor integrated circuit,
As shown in (g), the global wiring 70 is arranged on the fourth wiring layer (additional wiring layer) 71, and the wiring pattern 9 is arranged on the third wiring layer (the uppermost wiring layer of the basic cell 1 ′).
9 and the global wiring 60 of the fourth wiring layer are connected via connection holes 73 and 74 formed in the interlayer insulating film 72 of the third wiring layer.

In the basic cell 1'of FIG. 1 (f), since the third wiring layer is the uppermost layer, the wiring pattern 9 is formed on this third wiring layer.
However, if the basic cell has four or more wiring layers, the wiring pattern 9 may be arranged in the uppermost layer.

FIG. 2A shows an example of a DFF circuit, FIG. 2B shows a symbol diagram of the DFF shown in FIG. 2A, and FIG. 2C shows an operation timing diagram. In FIG. 2B, 100 is a DATA input terminal, 110 is a CLK input terminal, 120 is an inverted CLK input terminal, and 200
Is a DATA output terminal, and 210 is an inverted DATA output terminal. FIG. 3A shows a semiconductor integrated circuit in which a plurality of the basic cells 1 of FIG. 1A are arranged on a semiconductor substrate (FIG. 2A).
2 shows a layout structure of a manufactured DFF). Figure 3
2A, the DFF circuit shown in FIG. 2A is obtained by arranging the basic cells 1A to 1F of FIG. 1A in the X direction and effectively utilizing the wiring pattern 9 of each of the basic cells 1A to 1F. Is realized only by the second layer as the wiring layer. Figure 3
2B shows a layout structure in which a plurality of the basic cells 1'of FIG. 1E are arranged on a semiconductor substrate to manufacture the DFF of FIG. 2A. Also in FIG. 2B, the basic cells 1A ′ to 1F ′ of FIG. 1E are arranged in the X direction, and each basic cell 1A ′ is arranged.
By effectively utilizing the wiring pattern 9 of 1F ′, the DFF circuit shown in FIG. 2A is realized only by the fourth wiring layer.

FIG. 4A shows a circuit example of the buffer, FIG. 4B shows a symbol diagram of the buffer, 100 is a DATA input terminal, 200 is a DATA output terminal, 210
Is an inverted DATA output terminal. FIG. 5 shows a structure in which a plurality of the basic cells 1 of FIG.
The layout structure which manufactured the buffer of (a) is shown. In FIG. 5, by arranging the basic cells 1A to 1F of FIG. 1A in the X direction and effectively utilizing the wiring pattern 9, the buffer circuit of FIG. 4A is used as a wiring layer. It is realized only by the second layer.

FIG. 6A shows an example of an ORNAND circuit, FIG. 6B shows a symbol diagram of the ORNAND, 100 to 105 are DATA input terminals, and 200 is DA.
TA output terminal. FIG. 7 shows the basic cell 1 of FIG.
Are arranged on a semiconductor substrate, and the ORN of FIG.
The layout structure which manufactured AND is shown. In FIG. 7, by arranging the basic cells 1A to 1C of FIG. 1A in the X (horizontal) direction and effectively utilizing the wiring pattern 9,
The circuit of the ORNAND of FIG. 6A is realized only by the second wiring layer.

FIG. 8A shows a circuit example of the selector, and FIG. 8B shows a symbol diagram of the selector. 100 is an A side DATA input terminal, 101 is a B side DATA input terminal, and 130 is A control signal input terminal for selection and a DATA output terminal 200. FIG. 9 shows a layout structure in which a plurality of basic cells 1 of FIG. 1A are arranged on a semiconductor substrate to manufacture the selector of FIG. 8A. In FIG. 9, by arranging the basic cells 1A to 1C of FIG. 1A in the X direction and effectively utilizing the wiring pattern 9, FIG.
The circuit of the selector in (a) is realized only by the second wiring layer.

(Second Embodiment) FIG. 10 shows a configuration diagram of a basic cell according to a second embodiment of the present invention. The basic cell in the figure shows a configuration diagram of the basic cell described in claim 2. The circuit diagram of this basic cell is the same as that shown in FIG. In addition, in FIG.
TP1, TP2, TN1, TN2, 1, 7, 8 and 2A
6A and 2B to 6B have the same configuration as the conventional basic cell of FIG. 30, the same reference numerals are given and detailed description thereof is omitted.

In this embodiment, in the basic cell 1,
Further, it has two wiring patterns 10 extending in a horizontal direction with a boundary line between the N-channel transistor region and the P-channel transistor region. Each wiring pattern 10
It exists independently of the N and P channel transistor regions. Although FIG. 10 has two wiring patterns 10, it may have one wiring pattern or three or more wiring patterns.

FIG. 11A shows the basic cell 1 of FIG.
A method of connecting the wiring pattern 10 in the inside to the wiring pattern 10 in another basic cell 1 adjacent to the basic cell 1 is shown. Generally, as shown in FIG. 11B, a method of connecting to the wiring 30 of the second layer by using two VIAs 20 on the grid is generally used as needed. However, if processally possible, as shown in FIG. 6C, the wiring pattern 10 of the first layer for signal lines is arranged so as to be adjacent to the adjacent basic cell with a minimum separation interval. In this state, if necessary, one VIA 20 may be used to connect to the second layer wiring 30. In the embodiments described below, only the case where the method of FIG.

FIG. 12 shows a layout structure in which the DFF circuit shown in FIG. 2A is manufactured. The layout structure of FIG. 12 is one in which a plurality of the basic cells 1 of FIG. 10 are arranged on a semiconductor substrate to manufacture a DFF circuit, and the reference numerals are the same as those in FIG. 2B. The description is omitted. In FIG. 12, the basic cells 1A to 1A of FIG.
2A by arranging 1F in the X direction and effectively utilizing the wiring pattern 10 of each basic cell 1.
It can be seen that the DFF circuit shown in FIG. 3 can be realized only by the second wiring layer.

FIG. 13 shows a layout structure for manufacturing the circuit of the buffer shown in FIG. 4 (a). The layout structure of FIG. 10 is a buffer circuit manufactured by arranging a plurality of the basic cells 1 of FIG. 10 on a semiconductor substrate, and the reference numerals are the same as those in FIG. 4B. The description is omitted. In FIG. 13, the basic cell 1A of FIG.
4 to 1F are arranged in the X direction and the wiring pattern 10 of each basic cell 1 is effectively used,
It can be seen that the buffer circuit shown in (a) can be realized only by the second wiring layer.

FIG. 14 shows the ORNA shown in FIG. 6 (a).
The layout structure which manufactured the circuit of ND is shown. The layout structure of FIG. 14 is one in which a plurality of the basic cells 1 of FIG. 10 are arranged on a semiconductor substrate to manufacture an ORNAND circuit, and the reference numerals are the same as those of FIG. 6B. The description is omitted. In FIG. 14, by arranging the basic cells 1A to 1C shown in FIG. 10 in the X direction and effectively utilizing the wiring pattern 10 of each basic cell 1, the ORNAND circuit shown in FIG. It can be seen that it can be realized only by the second wiring layer.

FIG. 15 shows a layout structure in which the circuit of the selector shown in FIG. 8A is manufactured. The layout structure of FIG. 15 is one in which a plurality of the basic cells 1 of FIG. 10 are arranged on a semiconductor substrate to manufacture a selector circuit.
Since the reference numerals are the same as those in FIG. 8B, detailed description thereof will be omitted. In FIG. 15, the basic cell 1 of FIG.
By arranging A to 1C in the X direction and effectively utilizing the wiring pattern 10 of each basic cell 1, the above-mentioned FIG.
It can be seen that the selector circuit shown in (a) can be realized only by the second wiring layer.

(Third Embodiment) FIG. 16 is a block diagram showing a CMOS type basic cell according to a third embodiment of the present invention. The basic cell shown in FIG.
3 is a block diagram of the basic cell described in FIG. The circuit diagram of this basic cell is the same as that shown in FIG. In addition, FIG.
, TP1, TP2, TN1, TN2, 1,
Since 7, 8 and 2A to 6A and 2B to 6B have the same configuration as that of the conventional basic cell shown in FIG.

In this embodiment, in the basic cell 1,
Further, it has two wiring patterns 11 and 12 extending in a horizontal direction with a boundary line between the N-channel transistor region and the P-channel transistor region. Both of the wiring patterns 11 and 12 are independent of the N and P channel transistor regions, but one wiring pattern 11 extends to the right end of the basic cell 1 and the other basic cell (see FIG. (Not shown) are connected to the wiring pattern 11 of the basic cell when they are adjacent to each other. The other wiring pattern 12
Extends to the left end of the basic cell 1 and is connected to the wiring pattern 12 of this basic cell when another basic cell (not shown) is adjacent to the left side of the drawing. That is, other basic cells adjacent to the left and right of the basic cell 1 are not shown, but two wiring patterns 1 similar to the basic cell 1 of FIG.
1 and 12, although one wiring pattern 11 extends to the left end in the drawing unlike FIG. 16, the other wiring pattern 12 extends to the right end in the drawing unlike FIG. 16 is different from the basic cell 1 in FIG.

In FIG. 16, the two wiring patterns 11,
Although 12 is provided, it goes without saying that one or three or more may be provided.

FIG. 17 shows a layout structure in which the DFF circuit shown in FIG. 2A is manufactured. The layout structure of FIG. 17 is a DFF circuit manufactured by arranging a plurality of the basic cells 1 of FIG. 16 on a semiconductor substrate, and the reference numerals are the same as those in FIG. 2B. The description is omitted. In FIG. 17, the basic cells 1A to 1A of FIG.
By arranging 1F in the X direction and effectively utilizing the wiring patterns 11 and 12 of each basic cell 1, the DFF circuit shown in FIG. 2A is realized only by the second wiring layer. You can see that it is done.

FIG. 18 shows a layout structure in which the circuit of the buffer shown in FIG. 4 (a) is manufactured. The layout structure of FIG. 18 is obtained by arranging a plurality of the basic cells 1 of FIG. 16 on a semiconductor substrate to manufacture a buffer circuit.
Since the reference numerals are the same as those in FIG. 4B, detailed description thereof will be omitted. In FIG. 18, the basic cell 1 of FIG.
By arranging A to 1F in the X direction and effectively utilizing the wiring patterns 11 and 12 of each basic cell 1, the buffer circuit shown in FIG. It can be seen that

FIG. 19A shows the O shown in FIG. 6A.
The layout structure which manufactured the circuit of RNAND is shown. The layout structure of FIG. 19A is one in which a plurality of basic cells 1 of FIG. 16 are arranged on a semiconductor substrate to manufacture an ORNAND circuit, and the reference numerals are the same as those of FIG. 6B. , Its detailed description is omitted. In FIG. 19A, by arranging the basic cells 1A to 1C of FIG. 16 in the X direction and effectively utilizing the wiring patterns 11 and 12 of each basic cell 1, the basic cells 1A to 1C of FIG. ORN to show
It can be seen that the AND circuit can be realized only by the second wiring layer.

FIG. 19B shows a layout structure in which the selector circuit shown in FIG. 8A is manufactured. FIG. 19
The layout structure of (b) is one in which a plurality of basic cells 1 of FIG. 16 are arranged on a semiconductor substrate to manufacture a selector circuit, and the reference numerals are the same as those of FIG. 8 (b). Detailed explanation is omitted. In FIG. 19B, by arranging the basic cells 1A to 1C of FIG. 16 in the X direction and effectively utilizing the wiring patterns 11 and 12 of each basic cell 1, the basic cells 1A to 1C of FIG. It can be seen that the selector circuit shown can be realized only by the second wiring layer.

FIG. 20A shows a circuit example of a D-type flip-flop circuit with a scan function, FIG. 20B is a symbol diagram of the circuit, and FIG. 20C is a semiconductor having three circuits. An example of the configuration of the integrated circuit is shown in FIG. 7D, which is a timing chart during normal operation of the semiconductor integrated circuit, and in FIG. 8E, which is a timing chart during scan operation of the semiconductor integrated circuit.
Further, (f) to (h) of the figure show the layout structure of the D-type flip-flop circuit with the scan function shown in (a) of the figure. This layout structure is manufactured by arranging a plurality of the basic cells 1 shown in FIG. 16 on a semiconductor substrate.
20 (f) to 20 (h) are denoted by the same reference numerals as those in FIG. 20 (b), and detailed description thereof will be omitted. Here, FIG.
(F) shows a layout example in which the wiring shown by a thick line up to the scan data input terminal DT is the shortest, and (g) shows a layout example in which a wiring shown by a thick line up to the scan data input terminal DT is lengthened. In (h), the polysilicon gates of the four vacant transistors Tra to Trd are arranged in the middle of the wiring shown by the thick line to the scan data input terminal DT to further reduce the wiring delay time as compared with the layout example of FIG. An example of a longer layout is shown below. FIG.
In any case of (h), the basic cell 1A of FIG.
It can be seen that the wiring delay adjustment can be realized by only the second wiring layer by arranging 1 to 1I in the horizontal direction and effectively utilizing the wiring patterns 11 and 12 of each basic cell 1.

(Fourth and Fifth Embodiments) FIG. 21 is a block diagram showing a CMOS type basic cell 1 according to a fourth embodiment of the present invention. The basic cell 1 in FIG. 21 is a block diagram of the basic cell described in claim 4. The circuit diagram is the same as that of FIG. In addition, FIG.
, TP1, TP2, TN1, TN2, 1,
Since 7, 8 and 2A to 6A and 2B to 6B have the same configuration as that of the conventional basic cell shown in FIG.

The basic cell 1 of FIG. 21 is a combination of the basic cell of FIG. 1A and the basic cell of FIG.
That is, the wiring pattern 9 extending in the vertical direction is arranged between the P-channel transistor region and the N-channel transistor region, and the wiring pattern 1 extending in the horizontal direction.
0 for N-channel transistor area and GND pattern 8
It is characterized by being placed between and.

FIG. 22 shows a block diagram of a CMOS type basic cell 1 according to the fifth embodiment of the present invention. The basic cell 1 shown in FIG. 22 is a block diagram of the basic cell described in claim 5. The basic cell 1 of FIG. 22 corresponds to the basic cell of FIG.
It is a combination of the basic cell of. That is, the wiring pattern 10 extending independently in the horizontal direction is arranged between the P-channel transistor region and the N-channel transistor region, and the wiring pattern 11 extending horizontally to the right end is formed in the N-channel transistor region and the GND.
It is characterized in that it is arranged between the pattern 8 and the pattern 8.

As described above, according to the present invention, it is possible to combine the basic cell shown in FIG. 1A, the basic cell shown in FIG. 10 and the basic cell shown in FIG. For example, in addition to the basic cells shown in FIGS. 21 and 22, the wiring pattern 9 extending in the vertical direction in the basic cell of FIG. 22 may be the wiring pattern 10 extending in the horizontal direction. Further, the wiring pattern 9 of FIG.
The wiring pattern 10 and the wiring pattern 11 or / and 12 of FIG. 16 may be provided.

Further, in this embodiment, FIG. 21 and FIG.
The wiring patterns 9, 10 and 11 of 2 are each one,
Of course, two or more may be provided.

FIG. 23 shows a layout structure in which the DFF circuit shown in FIG. 2A is manufactured. The layout structure of FIG. 23 is one in which a plurality of the basic cells 1 of FIG. 21 are arranged on a semiconductor substrate to manufacture a DFF circuit, and the reference numerals are the same as those in FIG. 2B. The description is omitted. In FIG. 23, the basic cells 1A to 1A of FIG.
2F by arranging 1F in the X direction and effectively utilizing the wiring patterns 9 and 10 of each basic cell 1.
It can be seen that the DFF circuit shown in (a) can be realized only by the second wiring layer.

FIG. 24 shows a layout structure in which the circuit of the selector shown in FIG. 8A is manufactured. The layout structure of FIG. 24 is one in which a plurality of basic cells 1 of FIG. 22 are arranged on a semiconductor substrate to manufacture a selector circuit.
Since the reference numerals are the same as those in FIG. 8B, detailed description thereof will be omitted. In FIG. 24, the basic cell 1 of FIG.
By arranging A to 1C in the X direction and effectively utilizing the wiring patterns 10 and 11 of each basic cell 1, the circuit of the selector shown in FIG. 8A is provided only in the second wiring layer. It can be seen that

FIG. 26 shows a layout structure in which the SRAM circuit shown in FIG. 25A is manufactured. The layout structure of FIG. 26 is one in which a plurality of the basic cells 1 of FIG. 22 are arranged on a semiconductor substrate to manufacture an SRAM circuit, and the reference numerals are shown in the SRAM symbol diagram shown in FIG. 25B. The same symbols are given to the BIT line 300, the inverted BIT line 310, and the WORD line 320. In FIG. 26, the basic cells 1A and 1B shown in FIG.
It can be understood that the SRAM circuit shown in FIG. 25A can be realized only by the second wiring layer by effectively utilizing the wiring patterns 10 and 11 of FIG.

(Sixth Embodiment) Next, with reference to FIGS. 27 to 29, a CMOS type basic cell according to a sixth embodiment of the present invention and a semiconductor integrated circuit using this basic cell will be described. The manufacturing method will be described.

FIG. 27A shows the CMOS of this embodiment.
The structure of a type basic cell is shown. This basic cell 1 is shown in FIG.
Shows an equivalent circuit of.

In FIG. 27A, reference numeral 120 is a basic cell, and four transistors T are provided on the semiconductor substrate 121.
P1, TP2, TN1, and TN2 are provided and configured. When designing a semiconductor integrated circuit such as a logic cell, the basic cell 20 is arranged on the left side and the right side of the basic cell 120 in the figure.
Another basic cell having the same configuration as is arranged.

The two P-channel transistors TP1 and TP2 of the basic cell 120 and the two N-channel transistors TN1 and TN2 are separated from each other by an insulating film (not shown). First P-channel transistor T
P1 has a gate electrode 101 and impurity diffusion regions 102 and 103 provided on both sides of the gate electrode 101. The impurity diffusion regions 102 and 103 serve as a source and a drain. The second P-channel transistor TP2 is the first P-channel transistor TP1.
Is arranged on the right side in the figure. This transistor TP2
Is a gate electrode 104, an impurity diffusion region 105 provided on the right side of the gate electrode 104 in the figure, and the first electrode
And an impurity diffusion region (shared diffusion region) 103 shared with the P channel transistor TP1.

The first and second N-channel transistors TN1 and TN2 are arranged below the two P-channel transistors TP1 and TP2. The first
The N-channel transistor TN1 of the
7 and impurity diffusion regions 108 and 109 provided on both sides of the gate electrode 107. The impurity diffusion regions 108 and 109 serve as a source and a drain. Further, the second N-channel transistor TN2 also includes the gate electrode 110, the impurity diffusion region 111 provided on the right side of the gate electrode 110 in the drawing, and the impurity diffusion region shared with the first N-channel transistor TN1. (Shared diffusion region) 109.

In the basic cell 120 of FIG. 27 (a),
Reference numerals 112 and 113 denote a global power supply pattern and a global GND pattern which are provided at the upper end and the lower end and are formed by the wiring of the first layer. Also, the basic cell 12
The dot line in 0 is the wiring grid, and X (horizontal)
There are 11 wiring tracks in the direction, and three wiring tracks v1, v2, and v3 exist in the Y (vertical) direction.

Next, the characteristic structure of the basic cell 120 shown in FIG. 27A will be described. In the basic cell 120 of the same figure, the gate electrode 101 of the first P-channel transistor TP1 has a main body portion 101a extending in the Y direction and a first folded portion obtained by bending the upper end portion of the main body portion 101a to the right side in the figure. It is composed of a bent portion 101b and a second bent portion 101c whose lower end portion is bent leftward in the drawing. Therefore, the gate electrode 101
Has a hook-like structure having a shape similar to the letter "S" having first and second bent portions 101b and 101c at the upper and lower ends of the main body 101a. Similarly, the gate electrode 104 of the second P-channel transistor TP2 also has a body portion 104a extending in the Y direction, and a first bent portion 104b obtained by bending the upper end portion of the body portion 104a to the right side in the drawing. It is composed of a second bent portion 104c whose lower end is bent leftward in the drawing. Therefore, the gate electrode 104 of the second P-channel transistor TP2 also includes the first and second gate electrodes 104 at the upper and lower ends of the main body 104a.
It has a hook-shaped structure having a shape similar to the letter "S" having the bent portions 104b and 104c.

The first P-channel transistor TP
The first bent portion 101b of No. 1 and the second bent portion 104c of the second P-channel transistor TP2 are arranged such that their tips are located on the wiring track v2 at the center in the Y direction, that is, The wiring tracks v2 are arranged so as to overlap each other when viewed in the Y direction from the X direction position.

In the basic cell 120, the first P
The impurity diffusion region of the channel transistor TP1 (first
Dedicated diffusion area 102) has a first bent portion 102a whose upper end is bent leftward in the drawing. Similarly, the second
The impurity diffusion region (second dedicated diffusion region) 105 of the P channel transistor TP2 has a second bent portion 105a whose lower end is bent rightward in the drawing. Therefore, the first and second P-channel transistors TP1,
The impurity diffusion regions 102, 103, 105 of TP2 are generally resembled to the reverse shape of the letter "S" having the first and second bent portions 102a, 105a at the upper left end and the lower right end in the figure, respectively. It has a hook-shaped structure.

The characteristic structure described above is also adopted for the first and second N-channel transistors TN1 and TN2.
That is, the gate electrode 107 of the first N-channel transistor TN1 includes a main body portion 107a extending in the Y direction, a first bent portion 107b obtained by bending the upper end portion of the main body portion 107a leftward in the drawing, and a lower end. No. 2 bent part to the right in the figure
And a bent portion 107c. Therefore, the gate electrode 107 of the first N-channel transistor TN1 has the first and second bent portions 107b at the upper and lower ends of the main body 107a.
It has a hook-shaped structure similar to the reverse shape of the English letter "S" with 107c. Similarly, the second N-channel transistor TN
The second gate electrode 110 also has a body portion 110 extending in the Y direction.
a, a first bent portion 110b in which the upper end portion of the main body portion 110a is bent leftward in the drawing, and a second bent portion 110c in which the lower end portion is bent rightward in the drawing. Therefore, the second
Electrode 110 of the N-channel transistor TN2 of
Also has a hook-shaped structure similar to the reverse shape of the letter "S" having first and second bent portions 110b and 110c at the upper and lower ends of the main body 110a. The first bent portion 107c of the first N-channel transistor TN1 and the second bent portion 110b of the second N-channel transistor TN2 have their tips on the wiring track v2 at the center in the Y direction. Position, that is, Y from the position of the wiring track v2 in the X direction.
Seen in the direction, they are arranged so as to overlap.

In the basic cell 120, the second N
The impurity diffusion region of the channel transistor TN2 (first
Dedicated diffusion area 111) has a first bent portion 111a whose upper end is bent rightward in the drawing. Similarly, the first
The impurity diffusion region (second dedicated diffusion region) 108 of the N-channel transistor TN1 has a second bent portion 108a whose lower end is bent leftward in the drawing. Therefore, the first and second N-channel transistors TN1,
The impurity diffusion regions 108, 109, and 111 of TN2 are generally similar to the shape of the letter "S" having the first and second bent portions 111a and 108a at the upper right end and the lower left end in the figure. Has a mold structure.

FIG. 29 shows the CM shown in FIG. 27 (a).
An example of a semiconductor integrated circuit in which six OS type basic cells 120 are arranged on a semiconductor substrate to realize the DFF circuit of FIG. 28A is shown. In FIG. 29, the basic cell 120 of FIG.
When A to 120F are arranged in the X direction, both basic cells to be arranged are arranged so as to overlap each other by one grid. That is, as can be seen from FIG. 29, for example, the basic cell 120
As an example of the relationship between A and the basic cell 120B adjacent thereto, the first P channel of the basic cell 120B is provided below the first bent portion 104b of the gate 104 of the second P channel transistor TP2 of the basic cell 120A. The first bent portion 102a of the impurity diffusion region 102 of the transistor TP1
Is located below the second bent portion 105a of the impurity diffusion region 105 of the second P-channel transistor TP2 of the basic cell 120A, and the second folding of the gate 101 of the first P-channel transistor TP1 of the basic cell 120B is performed. Music part 1
01c is located. The same applies to the relationship between the second N-channel transistor TN2 of the basic cell 120A and the first N-channel transistor TN1 of the basic cell 20B.

FIG. 29 of this embodiment and FIG. 31 of the prior art.
Comparing with (b), in the present embodiment, the layout area of the entire DFF logic circuit is reduced to about 70%, and the wiring grid used is also reduced to about 80%.

Moreover, for example, the gate 104 of the second P-channel transistor TP2 of the basic cell 120B and the first P-channel transistor TP1 of the basic cell 120C.
When connecting to the diffusion region 102 of
Since it is sufficient to connect the first bent portion 104b of No. 04 and the first bent portion 102a of the diffusion region 102, the wiring length of the wiring connecting both is sufficient to be one grid, and the wiring length can be shortened. . Therefore, the reduction of the wiring length and the reduction of the load capacitance due to the reduction of the layout area are combined,
The operation speed of the manufactured semiconductor integrated circuit can be increased.

In this embodiment, the first and second bent portions 101b, 101c, 104b, 104c and 107 are formed.
b, 107c, 110b, 110c, 102a, 105
Although a, 108a, and 111a exemplify the case of bending at a right angle to the side, the present invention is not limited to this.
It includes all cases where the body bends to the side, and also includes cases where the body bends to the side in a curved shape.

[0100]

As described above, claims 1 to 1
12 and the CMOS of the invention according to claims 21 to 25
According to the type basic cell and the method of manufacturing a semiconductor integrated circuit using the same, a complicated logic circuit which has conventionally required to use two or more wiring layers is manufactured using only one additional wiring layer, It can be realized and the timing adjustment of the hold time of the flip-flop circuit with scan function
Manufactured and realized using only one additional wiring layer,
The degree of wiring congestion at the time of designing a semiconductor integrated circuit is eased, the gate usage rate of the gate array is increased, and the integration degree of the semiconductor integrated circuit is improved. Moreover, cost reduction can be realized, and even if a change in logic or a change in wiring occurs, only one wiring layer is required as the correction layer, so that the development period can be shortened and the development cost can be reduced. is there.

According to the CMOS type basic cell and the method for manufacturing a semiconductor integrated circuit using this basic cell of the invention of claims 13 to 20 , the wiring track is sufficiently secured and the logic circuit It is possible to reduce the layout area, speed up the operation, and reduce the power consumption.

[Brief description of drawings]

FIG. 1A is a CMOS according to a first embodiment of the present invention.
Type basic cell layout diagram, (b) is an equivalent circuit diagram of the same basic cell, (c) is a basic cell 1A-1A shown in (a)
A line sectional view, (d) is a diagram for explaining the arrangement of global wirings when two basic cells shown in (a) are arranged in parallel, and (e) is a modification of the basic cell shown in (a). 2F is a cross-sectional view taken along line 1E-1E of the basic cell shown in (e), and (g) is a state of global wiring arrangement when two basic cells shown in (e) are arranged in parallel. It is a figure explaining.

2A is a circuit diagram of a DFF configured by using the basic cell of FIG. 1A, FIG. 2B is a symbol diagram of the DFF,
FIG. 7C is an operation timing chart of the DFF.

3A is a layout wiring diagram of a DFF using the basic cell shown in FIG. 1A, and FIG. 3B is a layout wiring diagram of a DFF using the basic cell shown in FIG. is there.

4A is a circuit diagram of a buffer configured by using the basic cell of FIG. 1A, and FIG. 4B is a symbol diagram of the buffer.

FIG. 5 is a layout wiring diagram of a buffer using the basic cell of FIG.

6A is a circuit diagram of an ORNAND configured by using the basic cell of FIG. 1A, and FIG. 6B is a symbol diagram of the same ORNAND.

7 is a layout wiring diagram of an ORNAND using the basic cell of FIG.

8A is a circuit diagram of a selector configured by using the basic cell of FIG. 1A, and FIG. 8B is a symbol diagram of the same selector.

FIG. 9 is a layout wiring diagram of a selector using the basic cell of FIG.

FIG. 10 is a layout diagram of a CMOS type basic cell according to the second embodiment of the present invention.

11 (a) is a layout wiring diagram using the basic cell of FIG. 10 and a basic cell adjacent to the basic cell, and FIG. 11 (b) is a wiring wiring diagram of two basic cells connected using two VIAs. The figure which shows a connection method, (c) is a figure which shows the connection method which connects wiring patterns mutually using one VIA.

12 is a layout wiring diagram of a DFF using the basic cell of FIG.

13 is a layout wiring diagram of a buffer using the basic cell of FIG.

14 is a layout wiring diagram of an ORNAND using the basic cell of FIG.

15 is a layout wiring diagram of a selector using the basic cell of FIG.

FIG. 16 is a layout diagram of a CMOS type basic cell according to the third embodiment of the present invention.

FIG. 17 is a layout wiring diagram of a DFF using the basic cell of FIG.

18 is a layout wiring diagram of a buffer using the basic cell of FIG.

FIG. 19 (a) is an ORNA using the basic cell of FIG.
FIG. 17B is a layout wiring diagram of an ND, and FIG. 17B is a layout wiring diagram of a selector using the basic cell of FIG.

20A is a circuit diagram showing a D-type flip-flop circuit with a scan function configured by using the basic cell of FIG. 16, FIG. 20B is a symbol diagram of the D-type flip-flop circuit, and FIG. Is a block diagram showing a logic circuit using the same D-type flip-flop circuit, (d) is an operation timing diagram during the normal operation of the same logic circuit, (e) is an operation timing diagram during the scan operation of the same logic circuit, ( f) is a diagram showing an example of layout wiring of a D-type flip-flop circuit with a scan function using the basic cell of FIG. 16;
(G) is a diagram showing another example of the same layout wiring diagram, (h)
FIG. 11 is a diagram showing still another example of the same layout wiring diagram.

FIG. 21 is a layout diagram of a CMOS type basic cell according to the fourth embodiment of the present invention.

FIG. 22 is a layout diagram of a CMOS type basic cell according to the fifth embodiment of the present invention.

FIG. 23 is a layout wiring diagram of a DFF using the basic cell of FIG. 21.

24 is a layout wiring diagram of a selector using the basic cell of FIG. 22. FIG.

FIG. 25A is an SRA configured using a basic cell.
A circuit diagram of M, and (b) are symbol diagrams of the SRAM.

FIG. 26 is a layout wiring diagram of an SRAM using the basic cell of FIG. 22.

FIG. 27 (a) is a CMO according to a sixth embodiment of the present invention.
A layout diagram of the S-type basic cell, and (b) is an equivalent circuit diagram of the basic cell.

28A is a circuit diagram of a D-type flip-flop circuit configured by using the basic cell shown in FIG. 27, FIG. 28B is a symbol diagram of the same D-type flip-flop circuit, and FIG. 6 is an operation timing chart of the flip-flop circuit of FIG.

29 is a layout wiring diagram when a D-type flip-flop circuit is manufactured using the CMOS basic cell shown in FIG. 27. FIG.

FIG. 30 is a diagram showing a layout of a conventional basic cell.

31A is a layout wiring diagram of a DFF using a conventional basic cell, and FIG. 31B is a DF using a conventional basic cell.
It is another layout wiring diagram of F.

FIG. 32 is another layout wiring diagram of a DFF using a conventional basic cell.

FIG. 33 is a layout wiring diagram of a buffer using a conventional basic cell.

FIG. 34 is another layout wiring diagram of a buffer using a conventional basic cell.

FIG. 35 is a layout wiring diagram of an ORNAND using a conventional basic cell.

FIG. 36 is another layout wiring diagram of an ORNAND using a conventional basic cell.

FIG. 37 is a layout wiring diagram of a selector using a conventional basic cell.

FIG. 38 is another layout wiring diagram of a selector using a conventional basic cell.

FIG. 39 is a layout wiring diagram of an SRAM using a conventional basic cell.

FIG. 40 is another layout wiring diagram of an SRAM using a conventional basic cell.

FIG. 41 is a layout wiring diagram of a D-type flip-flop circuit with a scan function using a conventional basic cell.

[Explanation of symbols]

1, 1 ′ CMOS type basic cell 1A to 1F Basic cell used in logic cell TP1 First P-channel transistor TP2 Second P-channel transistor TN1 First N-channel transistor TN2 Second N-channel transistor 2A TP1 gate Electrode 2B TN1 gate electrode 3A TP1 one side impurity diffusion layer 3B TN1 one side impurity diffusion layer 4A TP1, TP2 common impurity diffusion layer 4B TN1, TN2 common impurity diffusion layer 5A TP2 gate electrode 5B TN2 gate electrode 6A Impurity diffusion layer 6B on one side of TP2 6B Impurity diffusion layer on one side of TN2 7 Power supply pattern 8 GND patterns 9, 10, 11, 12 Wiring pattern 20 VIA 30 Wiring 61, 71 Additional wiring layer 101, 104 107 , 110 gates 101a, 104a 107a, 110a Gate body 101b, 104b 107b, 110b Gate first bent portion 101c, 104c 107c, 110c Gate second bent portion 102, 111 Diffusion region (first dedicated diffusion region) 103, 109 diffusion region (shared diffusion region) 105, 108 diffusion region (second dedicated diffusion region) 102a, 111a first bent portion 105a, 108a of diffusion region second bent portion 112 power supply pattern 113 GND Pattern 120, 120A to 120F CMOS type basic cell 121 Semiconductor substrate

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/092 (56) References JP-A-6-252367 (JP, A) JP-A-9-97885 (JP, A) Special Kai 61-202452 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/118 H01L 21/82 H01L 21/822 H01L 21/8238 H01L 27/04 H01L 27/092 G06F 17/50

Claims (25)

(57) [Claims] 1. A semiconductor substrate on odor Te and an N-channel tiger <br/> Njisu data and P-channel transient is te, gate
CMOS for forming an array type semiconductor integrated circuit
In type basic cell, between the N-channel transient scan data and the P-channel tiger <br/> Njisu data, and the N-channel transient is te
及 beauty has a wiring pattern existing independently of the P-channel transient scan data, the wiring pattern, the CMOS basic cell and other CM
A CMOS type basic cell, which is formed in an uppermost wiring layer among one or two or more wiring layers included in the CMOS type basic cell that can be connected to an OS type basic cell. 2. The N-channel wiring pattern
Boundary between transistor and P-channel transistor
Characterized by extending in a direction vertical or horizontal to the line
The CMOS type basic cell according to claim 1. 3. The CMOS type basic cell is a power supply pattern.
, The ground pattern, and the wiring pattern
And other wiring patterns, the N-channel transistor and the ground pattern
Between the N-channel transistor and the P
Extend in a direction horizontal to the boundary with the channel transistor
And the N-channel transistor region and P-channel
Other than the above, which exists independently of the channel transistor region.
A wiring pattern, and the other wiring pattern includes the CMOS type basic cell.
The uppermost wiring layer among one or two or more wiring layers
The CM according to claim 1 or 2, wherein the CM is formed.
OS type basic cell. 4. The other wiring pattern is the CMOS
The basic cells are electrically connected to each other when they are adjacent to each other.
4. The CMOS type basic cell according to claim 3, wherein
Le. 5. The wiring pattern is the CMOS type substrate.
When the cells are adjacent to each other, they are electrically connected to each other
The CMO according to claim 1, 2, 3 or 4.
S-type basic cell. 6. A plurality of said claims 1, 2, 3, 4 or 5
The described CMOS type basic cell is more than the wiring pattern.
Be electrically connected by the upper wiring located above.
And a semiconductor integrated circuit. 7. A basic cell plurality sequences, which like a manufacturing method of a semiconductor integrated circuit of the gate array type which arranged a wiring one upper to upper layer of the basic cell constituting the semiconductor integrated circuit , C on the semiconductor substrate according to claim 1, 2, 3, 4 or 5.
A plurality of MOS basic cells are arranged, and a wiring pattern formed on the uppermost wiring layer of each CMOS basic cell and the upper wiring are used to realize a logic circuit having a clock signal line. A method of manufacturing a semiconductor integrated circuit having a feature. 8. A basic cell plurality sequences, which like a manufacturing method of a semiconductor integrated circuit of the gate array type which arranged a wiring one upper to upper layer of the basic cell constituting the semiconductor integrated circuit , C on the semiconductor substrate according to claim 1, 2, 3, 4 or 5.
A logic circuit in which a plurality of MOS basic cells are arranged and a wiring pattern formed in the uppermost wiring layer of each CMOS basic cell and the upper wiring layer are used to connect transistors in parallel. A method of manufacturing a semiconductor integrated circuit, which comprises: 9. A basic cell plurality sequences, which like a manufacturing method of a semiconductor integrated circuit of the gate array type which arranged a wiring one upper to upper layer of the basic cell constituting the semiconductor integrated circuit , C on the semiconductor substrate according to claim 1, 2, 3, 4 or 5.
A MOS basic cells and a plurality placed, a wiring pattern formed on the uppermost wiring layer of the CMOS type basic cells, using the said upper wire, characterized in that to realize a complex logic semiconductor Manufacturing method of integrated circuit. The method according to claim 10 basic cells and a plurality sequences, which like a manufacturing method of a semiconductor integrated circuit of the gate array type which arranged a wiring one upper to upper layer of the basic cell constituting the semiconductor integrated circuit , C on the semiconductor substrate according to claim 1, 2, 3, 4 or 5.
A plurality of MOS basic cells are arranged, and a wiring pattern formed in the uppermost wiring layer of each CMOS basic cell and the upper wiring are used to realize a logic circuit having a control signal line. A method of manufacturing a semiconductor integrated circuit having a feature. 11. A basic cell plurality sequences, which like a manufacturing method of a semiconductor integrated circuit of the gate array type which arranged a wiring one upper to upper layer of the basic cell constituting the semiconductor integrated circuit , C on the semiconductor substrate according to claim 1, 2, 3, 4 or 5.
A plurality of MOS type basic cells are arranged, and a wiring pattern formed in the uppermost wiring layer of each CMOS type basic cell and the upper wiring are used to realize a logic circuit for memory. Method for manufacturing semiconductor integrated circuit. 12. A basic cell plurality sequences, which like a manufacturing method of a semiconductor integrated circuit of the gate array type which arranged a wiring one upper to upper layer of the basic cell constituting the semiconductor integrated circuit , C on the semiconductor substrate according to claim 1, 2, 3, 4 or 5.
A MOS basic cells and a plurality arrangement, the wiring patterns formed on the uppermost wiring layer of the CMOS type basic cells, using the said upper wire, to realize a flip-flop circuit having a scan test function A method of manufacturing a semiconductor integrated circuit, comprising: 13. A CMOS-type basic cell having an N-channel transistor and a P-channel transistor on a semiconductor substrate, wherein other basic cells having the same structure are arranged on the left side and the right side, respectively, and used. Or at least one of the diffusion regions of the P-channel transistor has a first bent portion whose upper end portion bends to one side and a second bent portion whose lower end portion bends to the other side. A CMOS-type basic cell characterized by being formed into a hook-shaped structure. 14. A CMOS-type basic cell having an N-channel transistor and a P-channel transistor on a semiconductor substrate, wherein other basic cells having the same structure are arranged on the left side and the right side, respectively, and used. Or at least one of the gates of the P-channel transistors,
A hook-shaped structure having a first bent portion having an upper end bent to one side and a second bent portion having a lower end bent to the other side, wherein the diffusion region of the N-channel transistor or the At least one of the diffusion regions of the P-channel transistor has a hook-shaped structure having a first bent portion whose upper end portion bends to one side and a second bent portion whose lower end portion bends to the other side. A CMOS type basic cell characterized by being formed. 15. A first N-channel transistor and a first P-channel transistor are formed in the vertical direction, and a second N-channel transistor is formed laterally of the first N-channel transistor.
A channel transistor is formed and the first
A second P-channel transistor is formed on a side of the P-channel transistor, and the gates of the two N-channel transistors and the two P-channel transistors are formed in the hook-shaped structure. The CMOS type basic cell according to claim 14 . 16. The gates of the two N-channel transistors and the gates of the two P-channel transistors have a first bent portion of one gate and a second bent portion of the other gate. 16. The CMOS type basic cell according to claim 15, wherein the cells are formed so as to overlap each other when viewed in the vertical direction from the same position in the horizontal direction. 17. The first and second N-channel transistors have one diffusion region, and the first and second P-channel transistors have one diffusion region, and the both diffusion regions are A shared diffusion region located between both gates and shared by both transistors; a first dedicated diffusion region located on the opposite side of the gate of the first transistor from the shared diffusion region; A second dedicated diffusion region located on the opposite side of the gate of the transistor from the shared diffusion region, wherein the first bent portion is formed in the first dedicated diffusion region, and the second bent region is formed. 16. The CMOS type basic cell according to claim 15 , wherein the second bent portion is formed in a dedicated diffusion region. 18. The N-channel transistor and P
15. A fixed wiring region in which a power supply wiring and a ground wiring are wired is provided outside a transistor region in which a channel transistor is arranged .
15. A CMOS type basic cell according to 15, 16 or 17 . 19. The first bent portion of the gate of the P-channel transistor and the first bent portion of the diffusion region of the P-channel transistor of the CMOS basic cell adjacent thereto are electrically connected by an upper wiring. And the upper wiring extends in a direction perpendicular to a boundary line between the N-channel transistor and the P-channel transistor.
A gate array type semiconductor integrated circuit including the CMOS type basic cell according to 16, 17, or 18. 20. A method of manufacturing a semiconductor integrated circuit of the gate array type which are arranged basic cells in the plurality laterally constituting the semiconductor integrated circuit, claim 13,14,15,16,17 or 18 In the CMOS basic cell described, the first bent portion of one CMOS basic cell and the second bent portion of the CMOS basic cell arranged on the side of this basic cell are from the same lateral position. A method of manufacturing a semiconductor integrated circuit, characterized in that the semiconductor integrated circuits are arranged in a horizontal direction so as to overlap each other when viewed in the vertical direction. 21. N-channel transistor on a semiconductor substrate
It has a transistor and a P-channel transistor,
CMO for forming a semiconductor array circuit of the array type
In the S-type basic cell, the N-channel transistor and the P-channel transistor are
And the N-channel transistor
And a P-channel transistor that exists independently of the P-channel transistor.
A line pattern, and the wiring pattern includes the CMOS basic cell and another CM
The CMOS type basic cell for connecting to the OS type basic cell
The top layer of one or more wiring layers provided in the cell
It is formed on the wiring layer, a plurality arranging the CMOS type basic cell, said wiring pattern
A plurality of CMOS-type basics by wiring above
Collection of semiconductors characterized by electrically connecting cells to each other
Method of manufacturing integrated circuit. 22. The wiring pattern is the N channel.
Boundary between the transistor and the P-channel transistor
Characterized by extending in a direction vertical or horizontal to the field line
22. The method of manufacturing a semiconductor integrated circuit according to claim 21. 23. The CMOS type basic cell is a power source pattern.
The wiring pattern, the ground pattern, and the wiring pattern are different.
And another wiring pattern, the N-channel transistor and the ground pattern
Between the N-channel transistor and the P
Extend in a direction horizontal to the boundary with the channel transistor
And the N-channel transistor region and P-channel
Other than the above, which exists independently of the channel transistor region.
A wiring pattern, and the other wiring pattern includes the CMOS type basic cell.
The uppermost wiring layer among one or two or more wiring layers
23. Formed according to claim 21 or 22, characterized in that it is formed.
Manufacturing method of semiconductor integrated circuit. 24. The wiring pattern is the CMOS type
When the basic cells are adjacent to each other, they are electrically connected to each other.
24. The half according to claim 21, 22 or 23, characterized in that
Manufacturing method of conductor integrated circuit. 25. A plurality of said CMOS type basic cells are said
By the upper wiring located higher than the wiring pattern
23. Electrically connected to each other,
25. A method for manufacturing a semiconductor integrated circuit according to 2, 23 or 24.