WO2003092078A1 - Semiconductor element and manufacturing method thereof - Google Patents
Semiconductor element and manufacturing method thereofInfo
- Publication number
- WO2003092078A1 WO2003092078A1 PCT/JP2003/005334 JP0305334W WO03092078A1 WO 2003092078 A1 WO2003092078 A1 WO 2003092078A1 JP 0305334 W JP0305334 W JP 0305334W WO 03092078 A1 WO03092078 A1 WO 03092078A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor region
- region
- semiconductor
- central portion
- peripheral portion
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 186
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 230000002093 peripheral effect Effects 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 abstract description 29
- 238000000407 epitaxy Methods 0.000 description 14
- 230000005684 electric field Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention 'relates to a semiconductor device, and more particularly to a semiconductor device having a structure called a RESURF structure and a method for manufacturing the same.
- MOS FET Metal Oxide Semiconductor Field Effect Transistor
- the channel M ⁇ SFET 101 (hereinafter referred to as MO SFET 101) includes a p-type semiconductor substrate 102, an n-type epitaxy region 103 formed on the upper surface of the semiconductor substrate 102 by an epitaxial growth method or the like, A p + -type isolation region 104 for isolating each MOSFET 101 mounted on the integrated circuit by using the reverse bias of the junction is provided.
- the MOSFET 101 has a P ⁇ type diffusion region 105 formed in the surface region on the upper surface of the epitaxial region 103, and a p + formed in the surface region on the upper surface of the epitaxial region 103 so as to be in contact with the diffusion region 105. And a drain region 106 of a mold type.
- the MOSFET 101 has a p + type source region 107 formed in the surface region of the epitaxial region 103 between the diffusion regions 105 when viewed in cross section, and an epitaxial region 103 that is sandwiched between the source region 107.
- Top surface of epitaxy region 103 between diffusion region 105 and source region 107 Has a gate insulating film 109 formed thereon. On the gate insulating film 109, a gate electrode 110 is formed. Of the surface region of the epitaxial region 103, the surface region facing the good electrode 110 via the gate insulating film 109 functions as a channel region.
- the top surface of the drain region 106, the top surface of the source region 107, the top surface of the back gate region 1 ⁇ 8, and the top surface of the isolation region 104 have a drain electrode 1 1 1, a source electrode 1 1 2, A gate electrode 113 and a ground electrode 114 grounded are formed.
- the surface except the gate insulating film 109, the gate electrode 110, the drain electrode 111, the source electrode 112, the back gate electrode 113, and the ground electrode 114 are formed.
- the field oxide film is covered by 115.
- the n-type epitaxial region 103 is formed on the p-type semiconductor substrate 102, and the p-type diffusion region 105 is formed in the surface region of the epitaxial region 103. It has a so-called double RESURF structure.
- the MOS FET 101 having the double RESURF structure when a voltage equal to or higher than a predetermined value is applied between the source electrode 112 and the drain electrode 111, the epitaxial region 103 and the diffusion region 105 are formed. Is substantially depleted. Thereby, the electric potential is fixed, and the electric field density per unit area of the epitaxial region 103 is reduced. As a result, the effect of improving the withstand voltage characteristics can be obtained.
- the MOS FET 101 makes use of the high withstand voltage characteristics of the RESURF structure. For example, it can be used for a level shift down circuit. When used in a level shift-down circuit, the MOS FET 101 is required to have a withstand voltage characteristic capable of withstanding a drain voltage that is about ten volts higher than the voltage of the semiconductor substrate 102, for example. The MOS FET 101 having the above configuration can easily respond to such a demand. However, when used in applications requiring withstand voltage characteristics that can withstand even higher voltage levels, the MOS FET 101 with the above configuration can cope with situations where the drain voltage changes from the ground level to a higher voltage level. Did not.
- a ground-level isolation region 104 is formed near the drain region 106 in order to maintain a good charge balance in the vicinity of the drain region 106.
- the electric field strength between the drain region 106 and the isolation region 104 increases, and punch-through and the like occur. Breakdown may occur at a voltage level lower than the desired voltage level.
- the present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device having excellent high withstand voltage characteristics and a method for manufacturing the same.
- Another object of the present invention is to provide a semiconductor device in which punch-through and undesirable breakdown hardly occur, and a method for manufacturing the same. Disclosure of the invention
- a semiconductor device includes a first conductive type first semiconductor region (2) and a first semiconductor region formed on one main surface of the first semiconductor region.
- the semiconductor region (6) includes a central portion (6a) surrounding the fourth semiconductor region, and a peripheral portion (6b) surrounding the central portion (6a).
- A, said central portion (6 a) is deeply formed than that of said peripheral edge depth from the surface of the second semiconductor material region (3) (6 b)
- a part of the second semiconductor region (3) disposed directly below the central portion (6a) is the second semiconductor region (3) disposed immediately below the peripheral portion (6b).
- a RESURF structure is formed by the first semiconductor region, the second semiconductor region, and the fourth semiconductor region.
- the electric field in the lateral direction of the semiconductor element can be satisfactorily reduced, and the effect of improving the withstand voltage characteristic can be obtained.
- a part of the second semiconductor region directly below the central portion is formed relatively thin, so that a portion of the second semiconductor region directly below the central portion is formed. Has a relatively small amount of charge. This prevents the charge balance near the fourth semiconductor region from being lost even when the ground level voltage is applied to the fourth semiconductor region.
- a part of the second semiconductor region disposed immediately below the peripheral portion is formed relatively thick.
- the semiconductor device of the present invention can cope with all situations where the voltage applied to the fourth semiconductor region changes from the ground level to the high level, and the improvement effect of the withstand voltage characteristic by the provision of the resource structure can be fully achieved. Can be obtained under the circumstances.
- the semiconductor element comprises: a drain electrode (12) formed on the fourth semiconductor region (7); a source electrode (13) formed on the fifth semiconductor region (8); A gate insulating film (10) covering the second semiconductor region (3) between a third semiconductor region (6) and the fifth semiconductor region; and a gate insulating film (10) on the gate insulating film (10). And a gate electrode (11) formed on the substrate.
- the semiconductor element includes a first conductivity type isolation region (4) formed on an outer peripheral edge of the second semiconductor region (3), and the second semiconductor region so as to be in contact with the isolation region (4).
- the third semiconductor region (6) is formed substantially at the center of the surface of the second semiconductor region (3), and the fourth semiconductor region (7) is formed in the third semiconductor region (6). ) May be formed substantially at the center of the surface.
- the semiconductor device further includes a ground electrode (15) formed on the isolation region (4), and applies a predetermined level of voltage between the gate electrode (10) and the drain electrode (12). By applying the voltage and grounding the ground electrode (15), the second semiconductor region (3) and the third semiconductor region (6) are substantially depleted. Good.
- the amount of charge that maintains the charge balance near the fourth semiconductor region (7) is reduced to the central portion ( 6 a) when a part of the second semiconductor region (3) immediately below is provided, and the voltage level of the voltage applied to the fourth semiconductor region (7) is higher than ground level, A portion of the second semiconductor region (3) immediately below the peripheral portion (6b) is provided with an amount of charge that maintains a charge balance in the vicinity of the fourth semiconductor region (7). You may.
- a method for manufacturing a semiconductor device includes a method for manufacturing a semiconductor device, comprising: forming a first semiconductor region of a first conductivity type on a semiconductor substrate (2); Forming a second semiconductor region (3); and providing a second semiconductor region (3) with a central portion (6a) and a peripheral portion (6b) having different depths in a surface region of the second semiconductor region (3).
- a RESURF structure is formed from the first semiconductor region, the second semiconductor region, and the fourth semiconductor region.
- the relaxation of the electric field in the lateral direction of the semiconductor element is satisfactorily achieved, and the effect of improving the withstand voltage characteristic is obtained.
- the central portion is formed deeper than the peripheral portion, a portion of the second semiconductor region immediately below the central portion is thinner than a portion of the second semiconductor region immediately below the peripheral portion. Therefore, a portion of the second semiconductor region immediately below the center has a relatively small amount of charge, and a portion of the second semiconductor region immediately below the peripheral portion has a relatively large amount of charge.
- this semiconductor element can prevent the charge balance in the vicinity of the fourth semiconductor region from being destroyed in all situations where the voltage applied to the fourth semiconductor region changes from the ground level to the high level. .
- this semiconductor element can obtain the effect of improving the withstand voltage characteristic by providing the RESURF structure under all circumstances.
- FIG. 1 is a cross-sectional view illustrating a configuration of a p-channel MOS FET according to an embodiment of the present invention.
- FIG. 2 is a plan view of the p-channel MOS FET of FIG.
- FIG. 3 is a cross-sectional view illustrating an example of a configuration of a channel MOS FET.
- a semiconductor device according to an embodiment of the present invention will be described with an example of a channel M ⁇ SFET (Metal Oxide Semiconductor Field Effect Transistor) mounted on an integrated circuit. The details will be described with reference to FIGS. 1 and 2.
- M ⁇ SFET Metal Oxide Semiconductor Field Effect Transistor
- MOS FET 1 As shown in FIG. 1, a p-channel MOS FET 1 (hereinafter, MOS FET 1) includes a semiconductor substrate 2, an epitaxial region 3, an isolation region 4, a first diffusion region 5, and a second diffusion region 6. , A drain region ⁇ , a source region 8, and a knock gate region 9.
- MOS FET 1 includes a good insulating film 10, a good electrode 11, a drain electrode 12, a source electrode 13, a back gate electrode 14, a ground electrode 15, and a field insulating film 16. Is provided.
- description will be made with reference to FIG. 1 unless otherwise indicated.
- the semiconductor substrate 2 is formed of a semiconductor substrate of a first conductivity type, for example, a p_ type.
- the epitaxy region 3 is composed of a semiconductor region of the second conductivity type, for example, n-type, formed on one main surface (upper surface) of the semiconductor substrate 2 by the epitaxy growth method.
- the epitaxial region 3 functions as the drain region in which the drain current flows in the lateral direction in FIG.
- the isolation region 4 is composed of a p + -type semiconductor region formed by diffusing a p-type impurity into a predetermined region of the epitaxial region 3.
- the separation region 4 has an annular shape surrounding the epitaxial region 3.
- the isolation region 4 uses the reverse bias of the pn junction to isolate each MOS FET 1 mounted on the integrated circuit.
- the first diffusion region 5 is composed of a p-type semiconductor region formed by diffusing a p-type impurity into a surface region on the outer peripheral edge of the epitaxial region 3. Further, the first diffusion region 5 is formed so as to be in contact with the separation region 4, and is formed so as to extend from the separation region 4 to the center of the epitaxy region 3 when viewed in cross section. As shown in FIG. 2, the first diffusion region 5 has an annular shape that surrounds the outer peripheral edge of the epitaxial region 3 when viewed from above the MO'S FET 1.
- the gate insulating film 10, the gate electrode 11, the drain electrode 12, the source electrode 13, and the knock gate are provided for easy understanding of the structure of the first diffusion region 5, etc.
- the electrode 14, the ground electrode 15 and the field insulating film 16 are omitted.
- the second diffusion region 6 is formed of a p-type semiconductor region formed by diffusing a p-type impurity into a surface region at a substantially central portion of the epitaxial region 3.
- the second diffusion region 6 includes a central portion 6a and a peripheral portion 6b having different depths when viewed in cross section.
- the central portion 6a is formed thicker than the peripheral portion 6b. As shown in FIG. 2, the central portion 6a is formed at a substantially central portion of the MOSFET 1 when viewed from the upper surface of the MOSFET 1.
- the peripheral portion 6 b is formed to have a thickness substantially equal to the thickness of the first diffusion region 5. As shown in FIG. 2, the peripheral portion 6b is formed in an annular shape so as to surround (the outer peripheral edge of) the central portion 6a.
- An epitaxial region 3 is interposed between the second diffusion region 6 and the semiconductor substrate 2. Due to the difference in thickness between the central portion 6a and the peripheral portion 6b, the epitaxial region 3 is relatively thin immediately below the central portion 6a and relatively thick immediately below the peripheral portion 6b. 'The thickness of the epitaxial region 3 immediately below the peripheral portion 6 b is substantially equal to the thickness of the epitaxial region 3 immediately below the first diffusion region 5.
- the drain region 7 is formed by diffusing a p-type impurity into the surface region of the second diffusion region 6 (central portion 6a), and is a p + -type semiconductor having a higher p-type impurity concentration than the second diffusion region 6. It consists of an area.
- the drain region 7 is formed substantially at the center of the second diffusion region 6, as shown in FIG. As shown in FIG. 1, a central portion 6a exists immediately below the drain region 7, and the central portion 6a functions as a drain-drift region.
- the source region 8 is formed of a p + -type semiconductor region formed by diffusing a p-type impurity into a surface region on the upper surface of the epitaxial region 3. As shown in FIG. 2, the source region 8 has an annular shape so as to surround the second diffusion region 6 (peripheral portion 6 b) via the epitaxial region 3.
- the back gate region 9 diffuses n-type impurities into the surface region of the epitaxial region 3.
- n-type impurity concentration is comprised of high n + -type semiconductor region than the n-type non-net concentration of Epitakisharu region 3.
- the pack gate region 9 has an annular shape surrounding the source region 8 via the epitaxial region 3. ⁇
- the gut insulating film 10 is composed of a silicon oxide film or the like.
- the gut insulating film 10 is formed so as to cover the upper surface of the epitaxial region 3 and a part of the upper surface of the source region 8 sandwiched between the second diffusion region 6 and the source region 8.
- the gate electrode 11 is made of a conductive film of polysilicon, metal, or the like, and is formed on the gate insulating film 10 by CVD (Chemical Vapor Deposition) or the like.
- the drain electrode 12, the source electrode 13, the knock gate electrode 14, and the ground electrode 15 are made of a conductive film such as a metal, and are formed on the drain region 7 and the source region 8 by CVD or the like, respectively. It is formed on the back gate region 9 and the isolation region 4.
- the field insulating film 16 is made of, for example, a silicon oxide film.
- the field insulating film 16 is a gate insulating film 10, a gate electrode 11, a drain electrode 12, a source electrode 13, a back gate electrode 14, and a ground electrode on the upper surface of the MOSFET 1. 1 and 5 cover the surface where it is not formed.
- the field insulating film 16 is formed thicker than the gate insulating film.
- a first RESURF structure including the p-type first diffusion region 5, the n-type epitaxy region 3, and the p-type semiconductor substrate 2 is formed. Have been. Further, in the center of the MOSFET 1, a second RESURF structure including a p_ type second diffusion region 6, an n-type epitaxy region 3, and a p-type semiconductor substrate 2 is formed. Have been. Therefore, the MOSFET 1 has a so-called double RESURF structure.
- the epitaxy region 3 of the first RESURF structure and the second diffusion region 6 of the second RESURF structure are connected to the ground electrode 15 and the gate electrode 11 and the drain.
- a voltage equal to or higher than a predetermined level is applied to the electrode 12
- the electrode 12 is substantially depleted.
- the potential is fixed, and the electric field in the horizontal direction in FIG.
- the effect of improving the breakdown voltage characteristics is obtained.
- the effect of improving the withstand voltage characteristics can be obtained even with a single RESURF structure, but since the M ⁇ SFET 1 has two RESURF structures, the effect of improving the withstand voltage characteristics is better than when a single RESURF structure is provided. Even better.
- the relatively thick central portion 6a is disposed immediately below the drain region 7.
- the epitaxy region 3 immediately below the central portion 6a is made thinner, and the amount of charge of the epitaxy region 3 is made smaller than the amount of charge of the epitaxy region 3 directly below the peripheral portion 6b. I have.
- a charge balance is established by an electric field from the isolation region or the like.
- the electric field from the drain region 7 or the like is reduced. Charge balance is established.
- the thickness of the central portion 6a is approximately equal to the peripheral portion 6b
- the thickness of the epitaxy region 3 directly below the central portion 6a is approximately equal to the thickness of the epitaxy region 3 directly below the peripheral portion 6b.
- the voltage level of the drain voltage changes to the ground level
- the voltages of the get, source, and pack gates change to a positive voltage. Breakdown occurs at the drain voltage.
- the MOSFET 1 of the present embodiment prevents the charge balance in the vicinity of the drain region 7 from being disrupted by reducing the charge amount of the epitaxial region 3 immediately below the drain region 7. For this reason, in the MOSET 1 of the present embodiment, breakdown does not occur at a relatively low voltage.
- the peripheral portion 6b is made thinner than the central portion 6a, and the epitaxial region 3 immediately below the peripheral portion 6b is made relatively thick, so that punch-through occurs. In order to prevent this, a sufficient amount of charge in the epitaxial region 3 is obtained.
- the MOS FET 1 By balancing the depth and concentration profile of the central portion 6a and the peripheral portion 6b, the thickness of the epitaxy region 3 below the central portion 6a and the peripheral portion 6b, etc., the MOS FET 1 according to the present embodiment is balanced. Can handle the situation where the voltage level of the drain voltage changes from the ground level to the high level of plus. For this reason, the MOS FET 1 can have excellent high withstand voltage characteristics under the above circumstances due to the effect of the electric field relaxation of the RESURF structure.
- the drain region 7 is formed substantially at the center of the epitaxial region 3. For example, it is assumed that a drain region is formed near an isolation region as in a conventional MOS FET.
- the present invention it is possible to provide a semiconductor device having excellent high withstand voltage characteristics. Further, according to the present invention, it is possible to provide a semiconductor device in which punch-through and breakdown are unlikely to occur, and a method for manufacturing the same.
- each semiconductor region has an annular shape when viewed from the top surface of the MOSFET 1 has been described as an example.
- the present invention is not limited to this. As viewed from above, it may have a square shape.
- the epitaxial region 3 is formed by the epitaxial growth method, but may be formed by a bonding technique or the like. '
- the semiconductor device of the above embodiment is not limited to the p-channel MOS FET, but may be an n-channel MOS FET. Further, in the above embodiment, the case where the p-channel MOS FET 1 is formed using the p-type semiconductor substrate 2 has been described as an example. However, the present invention is not limited to this, and a reverse conductive type MOS FET may be formed using an n-type semiconductor substrate. '
- the present invention can be used for a semiconductor element having a so-called RESURF structure and a method for manufacturing the same.
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03723204A EP1498956A4 (en) | 2002-04-25 | 2003-04-25 | SEMICONDUCTOR ELEMENT AND METHOD FOR THE PRODUCTION THEREOF |
JP2004501968A JPWO2003092078A1 (ja) | 2002-04-25 | 2003-04-25 | 半導体素子及びその製造方法 |
KR1020047016786A KR100794880B1 (ko) | 2002-04-25 | 2003-04-25 | 반도체소자 및 그 제조방법 |
US10/511,741 US7071527B2 (en) | 2002-04-25 | 2003-04-25 | Semiconductor element and manufacturing method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002123615 | 2002-04-25 | ||
JP2002-123615 | 2002-04-25 |
Publications (1)
Publication Number | Publication Date |
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WO2003092078A1 true WO2003092078A1 (en) | 2003-11-06 |
Family
ID=29267495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2003/005334 WO2003092078A1 (en) | 2002-04-25 | 2003-04-25 | Semiconductor element and manufacturing method thereof |
Country Status (6)
Country | Link |
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US (1) | US7071527B2 (ja) |
EP (1) | EP1498956A4 (ja) |
JP (1) | JPWO2003092078A1 (ja) |
KR (1) | KR100794880B1 (ja) |
TW (1) | TWI287873B (ja) |
WO (1) | WO2003092078A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005083794A2 (de) * | 2004-02-27 | 2005-09-09 | Austriamicrosystems Ag | Hochvolt-pmos-transistor |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100781033B1 (ko) * | 2005-05-12 | 2007-11-29 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
US7462534B2 (en) * | 2005-08-02 | 2008-12-09 | Micron Technology, Inc. | Methods of forming memory circuitry |
DE102007058489B3 (de) * | 2007-12-04 | 2009-04-30 | Moeller Gmbh | Zusatzbetätigungsvorrichtung für ein elektromechanisches Schaltgerät |
US8618627B2 (en) * | 2010-06-24 | 2013-12-31 | Fairchild Semiconductor Corporation | Shielded level shift transistor |
JP6704789B2 (ja) * | 2016-05-24 | 2020-06-03 | ローム株式会社 | 半導体装置 |
JP6740831B2 (ja) * | 2016-09-14 | 2020-08-19 | 富士電機株式会社 | 半導体装置 |
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JP3265712B2 (ja) * | 1992-05-25 | 2002-03-18 | 松下電器産業株式会社 | 高耐圧半導体装置及びその製造方法 |
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JP4610786B2 (ja) * | 2001-02-20 | 2011-01-12 | 三菱電機株式会社 | 半導体装置 |
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JPWO2003075353A1 (ja) * | 2002-03-01 | 2005-06-30 | サンケン電気株式会社 | 半導体素子 |
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US6900091B2 (en) * | 2002-08-14 | 2005-05-31 | Advanced Analogic Technologies, Inc. | Isolated complementary MOS devices in epi-less substrate |
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2003
- 2003-04-25 EP EP03723204A patent/EP1498956A4/en not_active Withdrawn
- 2003-04-25 JP JP2004501968A patent/JPWO2003092078A1/ja active Pending
- 2003-04-25 KR KR1020047016786A patent/KR100794880B1/ko not_active IP Right Cessation
- 2003-04-25 US US10/511,741 patent/US7071527B2/en not_active Expired - Lifetime
- 2003-04-25 TW TW092109726A patent/TWI287873B/zh not_active IP Right Cessation
- 2003-04-25 WO PCT/JP2003/005334 patent/WO2003092078A1/ja active Application Filing
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005083794A2 (de) * | 2004-02-27 | 2005-09-09 | Austriamicrosystems Ag | Hochvolt-pmos-transistor |
WO2005083794A3 (de) * | 2004-02-27 | 2005-12-15 | Austriamicrosystems Ag | Hochvolt-pmos-transistor |
KR100826714B1 (ko) * | 2004-02-27 | 2008-04-30 | 오스트리아마이크로시스템즈 아게 | 고전압 pmos 트랜지스터 |
US7663203B2 (en) | 2004-02-27 | 2010-02-16 | Austriamicrosystems Ag | High-voltage PMOS transistor |
Also Published As
Publication number | Publication date |
---|---|
EP1498956A4 (en) | 2008-04-09 |
TW200400636A (en) | 2004-01-01 |
US7071527B2 (en) | 2006-07-04 |
JPWO2003092078A1 (ja) | 2005-09-02 |
US20050212073A1 (en) | 2005-09-29 |
EP1498956A1 (en) | 2005-01-19 |
KR100794880B1 (ko) | 2008-01-14 |
KR20040099460A (ko) | 2004-11-26 |
TWI287873B (en) | 2007-10-01 |
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