WO2003085727A2 - Puce a semiconducteurs comportant une couche de protection et procede de fabrication - Google Patents

Puce a semiconducteurs comportant une couche de protection et procede de fabrication Download PDF

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Publication number
WO2003085727A2
WO2003085727A2 PCT/DE2003/001149 DE0301149W WO03085727A2 WO 2003085727 A2 WO2003085727 A2 WO 2003085727A2 DE 0301149 W DE0301149 W DE 0301149W WO 03085727 A2 WO03085727 A2 WO 03085727A2
Authority
WO
WIPO (PCT)
Prior art keywords
protective layer
semiconductor chip
chip
semiconductor
flip
Prior art date
Application number
PCT/DE2003/001149
Other languages
German (de)
English (en)
Other versions
WO2003085727A3 (fr
Inventor
Volker Beyer
Jürgen Fischer
Erik Heinemann
Ida Marbach-Fischbach
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2003085727A2 publication Critical patent/WO2003085727A2/fr
Publication of WO2003085727A3 publication Critical patent/WO2003085727A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]

Definitions

  • the present invention relates to a semiconductor chip for ⁇ flip-chip assembly, which is protected against mechanical stress, damage and electrical short circuit.
  • stamps, pickups, converters and other devices for handling and transporting the chips Even after the actual one.
  • Flip-chip assembly of the semiconductor chip upside down on a carrier endangers the now exposed back and flanks by further treatment of the chip. Every processing step during and after the flip-chip assembly carries a high risk of mechanically damaging the chip.
  • a housing e.g. As a cover with a sealing compound is, at the very listed at the end of the manufacturing process on the chip .bracht '.
  • conductive 'adhesives or solders may be used for the electrical connection contacts of a semiconductor chip in flip chip. These materials serve to • connect the contacts of the chip and the contacts of the carrier in an electrically conductive manner; 'But they must not get on the chip flanks, as this can lead to short circuits. This risk exists above all in the case of small chips and in particular in the case of all chips in which the contact surfaces are arranged on the outside on the edge of an upper side, ie in the vicinity of an edge.
  • Object of the present invention is to provide 'for the flip-chip assembly to provide a protective unpackaged semiconductor chips against mechanical damage or electrical short. This object is achieved with the semiconductor chip with the features of claim 1 and with the method for flip-chip assembly with the features of claim 3. Refinements result from the dependent claims.
  • a protective layer is applied to the back of the semiconductor chip.
  • This protective layer can also be present on the flanks of the semiconductor chip.
  • the protective layer can be applied before the entire as- • sembly process chain.
  • the edge protection can be applied to the chip before the process chain begins.
  • the wafer is etched with the semiconductor chips in the first scribe line of the integrated circuit and contact surfaces, or the like provided front side, so * 'that the flanks of the individual semiconductor chips are exposed.
  • the etching depth is selected according to the desired chip thickness. This is followed by a similar process or PI ', so that the edges of the chips are covered with a protective layer.
  • the wafer is thinned from the back opposite the front side until the non-etched portions - the wafer thickness. are removed and the chips are thus isolated.
  • a protective layer can then be applied to the back of the chips.
  • This backside coating can be applied after the semiconductor chip has been placed on a carrier which is intended for the fli-chip assembly, optionally before or after the fixing of the chip by pressing on from the back.
  • the protective layer material pre preferably dimensioned so that the material upon application of the 'layer which runs over the edge of one die flanks of the chip.
  • the protective layer can also be applied to the back of the semiconductor chips before they are separated. In this case, the wafer is only thinned from the back to such an extent that the chips are still connected via very thin bridges made of semiconductor material. The protective layer can then be applied to the back. The wafer is then broken to separate the semiconductor chips.
  • the process steps of applying the side protection and the back protection are closer together in the production process.
  • the subsequent process step, in which the back protection is applied when the isolated semiconductor chip has already been placed on the carrier can be saved in this way.
  • An electrically non-conductive or anisotopically conductive material is used for the protective layer.
  • the material is preferably applied using a dispensing process.
  • the protection of the chip flanks can be omitted.
  • FIG. 1 An example of a semiconductor chip in flip-chip arrangement is shown in cross section '.
  • the semiconductor chip 2 is arranged upside down on the carrier 1., So that the contact areas 3 of the carrier 1 and the contact areas 4 of the semiconductor chip 2 are arranged opposite one another.
  • the contact areas assigned to each other. Chen are permanently bonded to each other with a conductive adhesive or a solder.
  • the contact areas 4 are located on the front side 5 of the semiconductor chip 2.
  • the rear side 6 of the semiconductor chip 2 is provided with a protective layer 7, which in this example also covers the flanks 8 with portions 9, but can be omitted there.
  • a filler material (underfill) 10 is shown, with which the space between the carrier 1 and the semiconductor chip 2 is filled.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)

Abstract

L'invention s'applique à la connexion par billes de puces à semiconducteurs, une couche de protection (7) servant à la protection contre les contraintes et dégâts mécaniques et à l'isolation électrique étant appliquée sur l'arrière de la puce à semiconducteurs (2). Ladite couche de protection peut aussi être appliquée sur les bords (8) de la puce à semiconducteurs. Selon l'invention, ladite couche de protection peut être appliquée en amont du processus d'assemblage ou lors de la fixation de la puce à semiconducteurs à l'envers sur un support (1).
PCT/DE2003/001149 2002-04-08 2003-04-08 Puce a semiconducteurs comportant une couche de protection et procede de fabrication WO2003085727A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10215355A DE10215355B4 (de) 2002-04-08 2002-04-08 Verfahren zur Flip-Chip-Montage von Halbleiterchips
DE10215355.8 2002-04-08

Publications (2)

Publication Number Publication Date
WO2003085727A2 true WO2003085727A2 (fr) 2003-10-16
WO2003085727A3 WO2003085727A3 (fr) 2004-08-05

Family

ID=28684817

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/001149 WO2003085727A2 (fr) 2002-04-08 2003-04-08 Puce a semiconducteurs comportant une couche de protection et procede de fabrication

Country Status (3)

Country Link
DE (1) DE10215355B4 (fr)
TW (1) TW200305263A (fr)
WO (1) WO2003085727A2 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722130A (en) * 1984-11-07 1988-02-02 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
EP1014444A1 (fr) * 1999-05-14 2000-06-28 Siemens Aktiengesellschaft Circuit intégré avec une couche de protection et sa méthode de fabrication
US20010018229A1 (en) * 2000-02-28 2001-08-30 Nbc Corporation Semiconductor device and method for fabricating same
US20010033016A1 (en) * 2000-02-14 2001-10-25 Masato Sumikawa Semiconductor device and method of manufacturing the same
US20020014661A1 (en) * 2000-07-25 2002-02-07 Fujitsu Limited Method of manufacturing semiconductor devices by dividing wafer into chips and such semiconductor devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5645056A (en) * 1979-09-21 1981-04-24 Hitachi Ltd Manufacture of semiconductor device
JPH08204497A (ja) * 1995-01-26 1996-08-09 Murata Mfg Co Ltd 弾性表面波装置
JPH11102985A (ja) * 1997-09-26 1999-04-13 Mitsubishi Electric Corp 半導体集積回路装置
US6023094A (en) * 1998-01-14 2000-02-08 National Semiconductor Corporation Semiconductor wafer having a bottom surface protective coating
US6075290A (en) * 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
JP2001085560A (ja) * 1999-09-13 2001-03-30 Sharp Corp 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722130A (en) * 1984-11-07 1988-02-02 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
EP1014444A1 (fr) * 1999-05-14 2000-06-28 Siemens Aktiengesellschaft Circuit intégré avec une couche de protection et sa méthode de fabrication
US20010033016A1 (en) * 2000-02-14 2001-10-25 Masato Sumikawa Semiconductor device and method of manufacturing the same
US20010018229A1 (en) * 2000-02-28 2001-08-30 Nbc Corporation Semiconductor device and method for fabricating same
US20020014661A1 (en) * 2000-07-25 2002-02-07 Fujitsu Limited Method of manufacturing semiconductor devices by dividing wafer into chips and such semiconductor devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 005, no. 103 (E-064), 3. Juli 1981 (1981-07-03) & JP 56 045056 A (HITACHI LTD), 24. April 1981 (1981-04-24) *

Also Published As

Publication number Publication date
DE10215355B4 (de) 2004-08-05
TW200305263A (en) 2003-10-16
DE10215355A1 (de) 2003-10-30
WO2003085727A3 (fr) 2004-08-05

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