WO2003085727A3 - Puce a semiconducteurs comportant une couche de protection et procede de fabrication - Google Patents

Puce a semiconducteurs comportant une couche de protection et procede de fabrication Download PDF

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Publication number
WO2003085727A3
WO2003085727A3 PCT/DE2003/001149 DE0301149W WO03085727A3 WO 2003085727 A3 WO2003085727 A3 WO 2003085727A3 DE 0301149 W DE0301149 W DE 0301149W WO 03085727 A3 WO03085727 A3 WO 03085727A3
Authority
WO
WIPO (PCT)
Prior art keywords
protective layer
semiconductor chip
production method
corresponding production
semiconductor
Prior art date
Application number
PCT/DE2003/001149
Other languages
German (de)
English (en)
Other versions
WO2003085727A2 (fr
Inventor
Volker Beyer
Juergen Fischer
Erik Heinemann
Ida Marbach-Fischbach
Original Assignee
Infineon Technologies Ag
Volker Beyer
Juergen Fischer
Erik Heinemann
Ida Marbach-Fischbach
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Volker Beyer, Juergen Fischer, Erik Heinemann, Ida Marbach-Fischbach filed Critical Infineon Technologies Ag
Publication of WO2003085727A2 publication Critical patent/WO2003085727A2/fr
Publication of WO2003085727A3 publication Critical patent/WO2003085727A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)

Abstract

L'invention s'applique à la connexion par billes de puces à semiconducteurs, une couche de protection (7) servant à la protection contre les contraintes et dégâts mécaniques et à l'isolation électrique étant appliquée sur l'arrière de la puce à semiconducteurs (2). Ladite couche de protection peut aussi être appliquée sur les bords (8) de la puce à semiconducteurs. Selon l'invention, ladite couche de protection peut être appliquée en amont du processus d'assemblage ou lors de la fixation de la puce à semiconducteurs à l'envers sur un support (1).
PCT/DE2003/001149 2002-04-08 2003-04-08 Puce a semiconducteurs comportant une couche de protection et procede de fabrication WO2003085727A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10215355.8 2002-04-08
DE10215355A DE10215355B4 (de) 2002-04-08 2002-04-08 Verfahren zur Flip-Chip-Montage von Halbleiterchips

Publications (2)

Publication Number Publication Date
WO2003085727A2 WO2003085727A2 (fr) 2003-10-16
WO2003085727A3 true WO2003085727A3 (fr) 2004-08-05

Family

ID=28684817

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/001149 WO2003085727A2 (fr) 2002-04-08 2003-04-08 Puce a semiconducteurs comportant une couche de protection et procede de fabrication

Country Status (3)

Country Link
DE (1) DE10215355B4 (fr)
TW (1) TW200305263A (fr)
WO (1) WO2003085727A2 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5645056A (en) * 1979-09-21 1981-04-24 Hitachi Ltd Manufacture of semiconductor device
US4722130A (en) * 1984-11-07 1988-02-02 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
EP1014444A1 (fr) * 1999-05-14 2000-06-28 Siemens Aktiengesellschaft Circuit intégré avec une couche de protection et sa méthode de fabrication
US20010018229A1 (en) * 2000-02-28 2001-08-30 Nbc Corporation Semiconductor device and method for fabricating same
US20010033016A1 (en) * 2000-02-14 2001-10-25 Masato Sumikawa Semiconductor device and method of manufacturing the same
US20020014661A1 (en) * 2000-07-25 2002-02-07 Fujitsu Limited Method of manufacturing semiconductor devices by dividing wafer into chips and such semiconductor devices

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204497A (ja) * 1995-01-26 1996-08-09 Murata Mfg Co Ltd 弾性表面波装置
JPH11102985A (ja) * 1997-09-26 1999-04-13 Mitsubishi Electric Corp 半導体集積回路装置
US6023094A (en) * 1998-01-14 2000-02-08 National Semiconductor Corporation Semiconductor wafer having a bottom surface protective coating
US6075290A (en) * 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
JP2001085560A (ja) * 1999-09-13 2001-03-30 Sharp Corp 半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5645056A (en) * 1979-09-21 1981-04-24 Hitachi Ltd Manufacture of semiconductor device
US4722130A (en) * 1984-11-07 1988-02-02 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
EP1014444A1 (fr) * 1999-05-14 2000-06-28 Siemens Aktiengesellschaft Circuit intégré avec une couche de protection et sa méthode de fabrication
US20010033016A1 (en) * 2000-02-14 2001-10-25 Masato Sumikawa Semiconductor device and method of manufacturing the same
US20010018229A1 (en) * 2000-02-28 2001-08-30 Nbc Corporation Semiconductor device and method for fabricating same
US20020014661A1 (en) * 2000-07-25 2002-02-07 Fujitsu Limited Method of manufacturing semiconductor devices by dividing wafer into chips and such semiconductor devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 005, no. 103 (E - 064) 3 July 1981 (1981-07-03) *

Also Published As

Publication number Publication date
TW200305263A (en) 2003-10-16
WO2003085727A2 (fr) 2003-10-16
DE10215355A1 (de) 2003-10-30
DE10215355B4 (de) 2004-08-05

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