WO2003061009A1 - Procede de fabrication de dispositif semi-conducteur - Google Patents

Procede de fabrication de dispositif semi-conducteur Download PDF

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Publication number
WO2003061009A1
WO2003061009A1 PCT/JP2003/000257 JP0300257W WO03061009A1 WO 2003061009 A1 WO2003061009 A1 WO 2003061009A1 JP 0300257 W JP0300257 W JP 0300257W WO 03061009 A1 WO03061009 A1 WO 03061009A1
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Prior art keywords
semiconductor
region
regions
mask
impurity
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PCT/JP2003/000257
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English (en)
Japanese (ja)
Inventor
Akio Iwabuchi
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Sanken Electric Co., Ltd.
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Publication date
Application filed by Sanken Electric Co., Ltd. filed Critical Sanken Electric Co., Ltd.
Priority to JP2003560999A priority Critical patent/JP4117483B2/ja
Priority to KR1020047010864A priority patent/KR100649292B1/ko
Priority to EP03701731A priority patent/EP1475837A4/fr
Publication of WO2003061009A1 publication Critical patent/WO2003061009A1/fr
Priority to US10/890,688 priority patent/US7074663B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device including a plurality of semiconductor elements having a buried layer.
  • a semiconductor device having a buried layer is known, for example, from US Pat. No. 5,330,922. Also, a semiconductor device in which an insulated gate field effect transistor and a bipolar transistor are formed on one semiconductor substrate, and each transistor is provided with a buried layer having a different thickness is disclosed in Japanese Patent Application Laid-Open No. H10-224. It is disclosed in Japanese Patent Publication No. 2 311.
  • the buried layer of the field effect transistor in the semiconductor device disclosed herein is formed by diffusion of antimony and phosphorus, and the buried layer of the bipolar transistor is formed by diffusion of antimony.
  • the resistance value between the drain and source of the first field effect transistor is the second value.
  • the drain-source resistance of the second field-effect transistor is smaller than the resistance between the source and the drain-source breakdown voltage of the second field-effect transistor. In some cases, it is required to form the first and second field effect transistors so as to be higher than the drain / source withstand voltage.
  • the first field effect The thickness of the buried layer of the transistor is formed to be thicker than the thickness of the buried layer of the second field effect transistor, and the impurity concentration of the buried layer of the first field effect transistor is increased. Good. As described above, when the thickness of the buried layer of the first field-effect transistor is increased and the impurity concentration is increased, the thickness of the drain region in the semiconductor substrate is reduced and the field-effect transistor of the field-effect transistor is reduced. In the ON state, the resistance value between the drain and the source decreases, and the withstand voltage between the drain and the source decreases.
  • any of the above methods requires special manufacturing steps for the first and second buried layers, which increases the manufacturing cost of the semiconductor device. It is another object of the present invention to provide a method capable of forming first and second buried layers having different thicknesses and impurity concentrations in the same manufacturing process. Disclosure of the invention
  • the method for manufacturing a semiconductor device comprises a first selective portion 49 for forming the first buried layer 8 or 8a for the first semiconductor element 1 or 1a and a second semiconductor element 2 for forming the first buried layer 8 or 8a. Or a semiconductor substrate comprising a first semiconductor region 6 of the first conductivity type having a second buried layer 9 for 2a or a second selective part 50 for forming a 9a. 4 Use 1 Steps
  • the ratio S a / S 1 of the area S a of 47 is larger than the ratio S b / S 2 of the area S b of the second opening 48 to the area S 2 of the second selected portion 50.
  • the first semiconductor region 6 has an opposite side to the first conductivity type through the first and second openings 47 or 47a or 47b, 48 or 48a of the mask.
  • An impurity of the second conductivity type is introduced, whereby the second and third layers as a part of the first and second buried layers 8 or 8a, 9 or 9a are respectively introduced.
  • a second conductivity type epitaxy layer 7 having a lower impurity concentration than the second and third semiconductor regions is grown, whereby the second conductive type epitaxial layer 7 is formed.
  • the third buried layer 8 or 8a, and the first buried layer 8 or 8a based on the thermal diffusion of impurities in the third semiconductor region 51 or 51a or 52. Forming the second buried layer 9 or 9a having a small thickness;
  • Each of the first and second buried layers 8 and 9 can be formed by both the first and second impurities having different diffusion coefficients.
  • first and second semiconductor elements can be first and second insulated gate field effect transistors.
  • first and second semiconductor elements are replaced with first and second bipolar elements.
  • the type transistors la and 2a can be used.
  • the impurity of the second conductivity type is phosphorus.
  • the first impurity is antimony
  • the second impurity is phosphorus
  • each of the first and second openings of the mask be composed of a plurality of strip-shaped openings 47 and 48 juxtaposed in a plan view.
  • a plurality of openings 47 a and 48 a are arranged so that each of the first and second openings of the mask is distributed and arranged to form a plurality of rows and a plurality of columns when viewed in plan. It can be.
  • the first opening of the mask is one opening 47 c for exposing at least a part of the second semiconductor region in plan view
  • the second opening is A plurality of openings 48 or 48a for exposing a plurality of portions of the third semiconductor region in a plan view can be formed.
  • a third semiconductor element 3 having a third buried layer 10 can be provided.
  • the boundary between the first and second buried layers 8 and 9 and the first semiconductor region 6 is formed of the second conductive type for forming the first and second buried layers 8 and 9.
  • the position where the impurity concentration is the same as the original impurity concentration of the first semiconductor region 6, and the boundary between the first and second buried layers 8 and 9 and the epitaxial layer 7 is In addition, this is a position where the impurity concentration of the second conductivity type for forming the second buried layers 8 and 9 becomes the same as the original impurity concentration of the epitaxial layer 7.
  • the first and second selection portions 49, 50 as the planned regions for forming the first and second buried layers 8 or 8a, 9 or 9a are formed.
  • S 2 areas SI and S2 Ratio of areas Sa and Sb of areas Sa and Sb, Sb /
  • the same impurity diffusion step and The thickness and impurity concentration of the first and second buried layers 8 or 8a, 9 or 9a can be made different by the same growth step of the epitaxial layer 7.
  • the first and second semiconductor elements having different characteristics can be obtained without increasing the number of manufacturing steps, and the manufacturing cost of the semiconductor device can be reduced.
  • FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a plan view showing a surface including first and second FETs of the semiconductor substrate of FIG.
  • FIG. 3 is a cross-sectional view showing a semiconductor substrate with a silicon oxide film for manufacturing the semiconductor device of FIG.
  • FIG. 4 is a sectional view showing a semiconductor substrate after a first mask is formed using the silicon oxide film of FIG. 3 and antimony is further introduced.
  • FIG. 5 is a cross-sectional view showing the semiconductor substrate after the second mask is formed and the phosphorus is introduced.
  • FIG. 6 is a plan view of the second mask of FIG.
  • FIG. 7 is a cross-sectional view showing a semiconductor substrate after forming a third mask and forming a P + -type semiconductor region for an isolation region.
  • FIG. 8 is a cross-sectional view showing the semiconductor substrate after forming the N-type epitaxial layer.
  • FIG. 9 is a cross-sectional view showing the semiconductor substrate after forming the fourth mask and forming the isolation region.
  • FIG. 10 is a cross-sectional view showing the semiconductor substrate after the fifth mask is formed and the lead region is formed.
  • FIG. 11 is a cross-sectional view illustrating a semiconductor device according to the second embodiment.
  • FIG. 12 is a plan view showing a second mask of the third embodiment.
  • FIG. 13 is a plan view showing a semiconductor substrate with a second mask according to the fourth embodiment.
  • FIG. 14 is a sectional view showing the semiconductor device according to the fifth embodiment.
  • FIG. 15 is a cross-sectional view showing the semiconductor substrate after phosphorus has been introduced through a mask in order to manufacture the semiconductor device of FIG.
  • FIG. 16 is a cross-sectional view showing a semiconductor substrate after forming an isolation region.
  • FIG. 17 is a cross-sectional view showing a semiconductor substrate after forming an epitaxial layer on the semiconductor substrate of FIG. BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment
  • the composite semiconductor device manufactured according to the present invention shown in FIG. 1 includes first and second semiconductors.
  • the first and second FETs 1, 2 and the transistor 3 are formed on a common silicon semiconductor substrate 4.
  • the silicon semiconductor substrate 4 is a silicon semiconductor substrate 4
  • a third buried layer 10 for transistor 3 is provided.
  • a drain region 15 for the second FET 2 a P-type body region 16, a source region 17 and a drain extraction region 18;
  • a collector region 19 for the transistor 3 a base region 20, an emitter region 21 and a collector lead region 22;
  • the P-type semiconductor region 6 corresponds to the first semiconductor region of the first conductivity type in each claim of the present application.
  • First first buried layer 8 of the FET 1 has a first part 2 4 made of New tau type semiconductor, the first buried region 2 4 yo impurity concentration Ri from relatively low New + -type semiconductor And a second part 25 consisting of:
  • the first portion 24 of the first buried layer 8 contains both antimony as the first rectangular impurity and phosphorus as the second rectangular impurity.
  • the second portion 25 contains phosphorus as a second type II impurity. This second part 25 is located both above and below the first part 24. Therefore, the upper portion of the first portion 24 of the second portion 25 is a portion where the phosphorus as the second rectangular impurity is diffused into the epitaxial layer 7, and the upper portion of the second portion 25.
  • the lower side of the first portion 24 is a portion where the phosphorus as the second rectangular impurity is diffused into the rectangular semiconductor region 6.
  • the impurity concentration of the second portion 25 of the first buried layer 8 has a value between the impurity concentration of the first portion 24 and the impurity concentration of the ⁇ -shaped drain region 11. Therefore, by providing the second portion 25, the resistance of the drain current path can be reduced.
  • the second buried layer 9 for the second FET 2 is composed of a third portion 27 made of an NT-type semiconductor and a ⁇ ⁇ -type semiconductor having a relatively lower impurity concentration than the third portion 27.
  • a fourth portion 28 consisting of The third portion 27 of the second buried layer 9 contains antimony and phosphorus as in the first portion 24 of the first buried layer 8 .
  • the 4th The portion 28 includes phosphorus as a second N-type impurity similarly to the second portion 25. This fourth part 28 is located both above and below the third part 27.
  • the upper part of the third part 27 of the fourth part 28 is a part where phosphorus as the second N-type impurity is diffused into the epitaxial layer 7, and the fourth part 28
  • the lower side of the third portion 27 is a portion where the phosphorus as the second N-type impurity is diffused into the P-type semiconductor region 6.
  • the impurity concentration of the fourth portion 28 has a value between the impurity concentration of the third portion 27 and the impurity concentration of the drain region 15. Therefore, the fourth portion 28 has a function of reducing the resistance value of the drain current path of the second FET 2.
  • the thickness of the second buried layer 9 is smaller than the thickness of the first buried layer 8.
  • the third buried layer 10 for the transistor 3 comprises a diffused layer of antimony.
  • the boundary between 5, 28 and the N-type epitaxial layer 7 is to form the second and fourth portions 25, 28 with the original N-type impurity concentration of the N-type epitaxial layer 7. This is the position where the phosphorus concentration becomes the same.
  • the boundary between the third buried layer 10 and the P-type semiconductor region 6 is a position where these impurity concentrations become the same.
  • the boundary between the third buried layer 10 and the N-type epitaxial layer 7 is a position where these impurity concentrations become the same.
  • the first and second FETs 1 and 2 and the transistor 3 are formed in the N-type epitaxial layer 7, respectively.
  • Drain region 1 composed of first and second FETs 1 and 2 N-type semiconductor
  • Each of 9 comprises an epitaxial layer 7 of an N-type semiconductor.
  • the drain region 11 of the first FET 1 is made of an N-type semiconductor and is adjacent to the second portion 25 of the first buried layer 8.
  • the first buried layer 8 composed of the first and second portions 24 and 25 is referred to as a drain region of the first FET 1, and the drain region 11 is referred to as a drain region. It can also be called a drift region.
  • the plurality of P-type body regions 12 of the first FET 1 are semiconductor regions for forming a channel, that is, a current path of the first FET 1, and are formed like islands in the N-type drain region 11. It is formed. Therefore, the P-type body region 12 can also be called a channel region, an island region, or a base region.
  • the plurality of source regions 13 of the first FET 1 are made of an N-type semiconductor, and are formed in islands in the P-type body region 12.
  • the first drain lead-out region 1 4 of FET 1 consists New tau type semiconductor, is connected to the first part 2 4 of the first buried layer 8 and in part exposed on one main surface of the semiconductor substrate 4 are doing.
  • This drain extraction region 14 can also be called a plug ( ⁇ 1 ug) region.
  • the first FET 1 has a drain electrode 31, a source electrode 32, and a gate electrode 33.
  • the drain electrode 31 is connected to the drain lead-out region 14, and the source electrode 32 is connected to the source region 13 and also to a portion of the P-type body region 12 opposite to the channel portion. .
  • the gate electrode 33 is disposed so as to face the channel portion of the P-type body region 12, that is, the current path portion, via the insulating film 30.
  • the drain region 15 of the second FET 2 is made of an N-type semiconductor and is adjacent to the fourth portion 28 of the second buried layer 9.
  • the second buried layer 9 composed of the third and fourth portions 27 and 28 is referred to as a drain region of the second FET 2, and the drain region 15 is referred to as a drain 'drift region. You can.
  • the plurality of P-type body regions 16 of the second FET 2 are formed in an N-type drain region 15 in an island shape. This P-type body region 16 can be called a channel region, an island-like region, or a base region, similarly to the P-type body region 12 described above.
  • Multiple sources of second FET 2 The region 17 is made of an N-type semiconductor, and is formed in an island shape in the P-type body region 16.
  • the drain extraction region 18 of the second FET 2 is made of an N + -type semiconductor, is connected to the third portion 27 of the second buried layer 9, and a part thereof is formed on one main surface of the semiconductor substrate 4. It is exposed.
  • the second FET 2 has a drain electrode 34, a source electrode 35 and a gate electrode 36.
  • the drain electrode 34 is connected to the drain extraction region 18, and the source electrode 35 is connected to the source region 17 and also to the portion of the P-type body region 16 on the side opposite to the channel portion.
  • the electrode 36 is disposed opposite to the channel portion of the P-type body region 16, that is, the current path portion, via the insulating film 30.
  • the collector region 19 of the transistor 3 is made of an N-type semiconductor and is adjacent to the third buried layer 10.
  • the base region 20 of the transistor 3 is made of a P-type semiconductor, and is formed in an island shape in the collector region 19.
  • the emitter region 21 of the transistor 3 is made of an N-type semiconductor. It is formed in an island shape in the base region 20.
  • the collector lead-out region 22 of the transistor 3 is made of an N + type semiconductor, is connected to the third buried layer 10, and a part thereof is exposed on one main surface of the semiconductor base 4.
  • the transistor 3 has a collector electrode 37, an emitter electrode 38 and a base electrode 39.
  • the collector electrode 37 is connected to the collector extraction region 22
  • the emitter electrode 38 is connected to the emitter region 21, and the base electrode 39 is connected to the base region 20.
  • the isolation region 23 is made of a P-type semiconductor, and includes first and second FETs 1, 2, and a transistor 3 when viewed in a plan view, that is, in a direction perpendicular to the surface of the semiconductor substrate 4. It is arranged so as to surround it, and is formed so as to extend from one main surface of the base 4 to the P-type semiconductor region 6 in the cross section of FIG.
  • a P-type silicon semiconductor substrate 41 is prepared as shown in FIG.
  • the semiconductor substrate 41 has a ⁇ -type semiconductor region 5 and a ⁇ -type semiconductor region 6.
  • [Rho type semiconductor region 6 has been formed on the [rho + type semiconductor region 5 in Epitakisha Le growth method, and a [rho form impurity contained at a concentration of about 1 X 1 0 1 ° cm- 3 boron And a thickness of about 40 / m.
  • the P-type semiconductor region 6 has first, second and third buried layers 8, 9, and 10 for the first, second, and third semiconductor elements. a ′, including first, second and third optional portions 49, 50, 10 a ′ that are to be formed.
  • the P + type semiconductor region 5 can be omitted, and the semiconductor substrate 41 can be composed of only the P type semiconductor region 6.
  • a silicon oxide film 42 is formed on the flat upper surface of the P-type semiconductor region 6 as shown in FIG. 3, and thereafter, as shown in FIG. First, second and third antimony introduction openings 43a, 43b and 43c are provided to obtain a first mask 44 for selectively diffusing impurities.
  • the first antimony introduction opening 43a of the first mask 44 is provided inside between the first and second chain lines 45a and 45b in FIG.
  • the first and second chain lines 45 a and 45 b correspond to the first selected portion 49 for the first buried layer 8 shown in FIGS. 5 and 6.
  • the second antimony introduction opening 43b of the first mask 44 is provided inside the third and fourth chain lines 45c and 45d in FIG.
  • the third and fourth chain lines 45 c, 45 d correspond to the second selected portion 50 for the second buried layer 9.
  • the third antimony introduction opening 43c of the first mask 4 is provided inside the fifth and sixth chain lines 45e and 45f in FIG.
  • the portions between the fifth and sixth chain lines 45 e and 45 f correspond to the third selected portion 10 a ′ for the third buried layer 10.
  • the first, second and third antimony introduction openings 43a, 43b, and 43c of the first mask 44 are selectively inserted into the P-type semiconductor region 6 through the first mask.
  • Antimony as an N-type impurity is simultaneously introduced or diffused, and the first, second and third selective portions 4 9 for the first-second and third buried layers 8, 9 and 10 are formed.
  • 50, 10a, the first, second and third antimony introduction regions 24a, 27a, 10a are formed.
  • the first and second antimony introduction regions 24 a, 27 & are formed to form the first and second buried layers 8, 9 for the first and second punches 1, 2. used.
  • the third antimony introduction region 10 a is used to form a third buried layer 10 for the transistor 3.
  • Each antimony introduction region 24a, 27a, 10a is formed by thermal diffusion of antimony under the condition that the diffusion temperature is about 1230 ° C and the diffusion time is about 180 minutes. It has a surface impurity concentration of about 2 XI 0 18 cm- 3 and a diffusion depth of about 6 ⁇ .
  • the P-type semiconductor region 6 may be referred to as a first semiconductor region
  • the first and second antimony-introduced regions 24a and 27a may be referred to as second and third semiconductor regions. is there.
  • the first mask 44 of FIG. 4 is removed, and thereafter, a second mask 46 made of a silicon oxide film having a function of preventing impurity doping is formed.
  • the second mask 46 includes a P-type semiconductor region 6 in which the first, second, and third antimony introduction regions 24a, 27a, and 10a are formed. Formed on the surface of Note that the second mask 46 may be obtained by forming a silicon oxide film on the first mask 44 without removing the first mask 44 in FIG. Wear
  • the second mask 46 in FIG. 5 has first and second phosphorus introduction openings 47 and 48 for selectively introducing phosphorus as the second impurity.
  • the first and second ring introduction openings 47, 48 are viewed in plan, When viewed from a direction perpendicular to the surface of the conductive substrate 41, the first and second selected portions 49, 50 for the first and second buried layers 8, 9 shown by chain lines in FIG. Each is arranged inside.
  • the first and second selection portions 49, 50 are interlinked, and the third selection portion 10a 'for the third buried layer 10 is covered with a second mask 46. ing.
  • the first ring introduction opening 47 consists of a collection of six strip-shaped openings each having a width of W1, and is formed so as to expose a part of the first selection portion 49. I have. That is, the first phosphorus introduction opening 47 is arranged so as to expose a part of the surface of the first antimony introduction region 24a. A narrow portion of the mask 46 having a width W2 is arranged between the six band-shaped first ring introduction openings 47.
  • the second ring introduction opening 48 includes a collection of six strip-shaped openings each having a width W3, and is formed so as to expose a part of the second selection portion 50. That is, the second phosphorus introduction opening 48 is arranged so as to expose a part of the second antimony introduction region 27a.
  • a narrow portion of the mask 46 having a width W4 is arranged between the six band-shaped second ring introduction openings 48.
  • the width W1 of the first phosphorus introduction opening 47 is larger than the width W3 of the second phosphorus introduction opening 48.
  • the lengths 1 of the first and second ring introduction openings 47, 48 have the same value.
  • the area of the first and second selected parts 49, 50 is S l, S 2, and the total area of the six first ring introduction openings 47 is S a
  • the total area of the six second line introduction openings 48 is Sb
  • the total of the six first line introduction openings 47 for the area S1 of the first selected portion 49 is The ratio S a / S 1 of the area S a is the ratio S b of the total area S b of the six second line introduction openings 48 to the area S 2 of the second selected portion 50. Greater than / S1.
  • Fig. 6 shows the first and second openings 47,
  • first and second openings 47 and 48 for introducing a line be uniformly distributed in the first and second selected portions 49 and 50.
  • the outermost peripheral edges of the first and second phosphorus introduction openings 47, 48 are formed in the first mask 44 of the first mask 44 in plan view. ⁇ It is desirable to be located inside the second antimony introduction openings 43a and 43b.
  • the semiconductor substrate 41 having the first and second antimony-introduced regions 24a and 27a is passed through the openings 47 and 48 of the second mask 46 to the semiconductor substrate 41 having the second N-type impurity.
  • the first and second phosphorus introduction regions 51 and 52 shown in FIG. 5 are formed.
  • the diffusion temperature is about 115 ° C and the diffusion time is about 1 ° C.
  • the diffusion depth of 2 is about 8 / xm.
  • the diffusion coefficient of phosphorus as the second impurity that is, the diffusion rate, is sufficiently larger than the diffusion coefficient of antimony as the first impurity. Therefore, phosphorus diffuses deeper than the first and second antimony introduction regions 24a and 27a. In Fig. 5, the first and second antimony introduction regions 24a and 27a overlap the first and second phosphorus introduction regions 51 and 52. And both are included.
  • the plurality of first phosphorus introduction openings 47 of the first selection portion 49 are relatively narrow, the plurality of first phosphorus introduction openings are formed by heat diffusion and diffusion.
  • a phosphorus introduction region 51 is also formed below the mask 46 between the regions 47.
  • the width W 4 between the plurality of second lin introduction openings 48 of the second selection portion 50 is equal to the mutual width of the plurality of first lin introduction openings 47 of the first selection portion 49. It is wider than the width W 2 between them.
  • a second phosphorus introduction region 52 is also formed under the mask 46 between the introduction openings 48. It should be noted that a plurality of first and second inlet openings 47,
  • the distance W 2, W 4 between each of 48 is not more than twice the diffusion length of the phosphorus in the heat treatment before forming the N-type semiconductor epitaxial layer 7.
  • the second and fourth portions 25 and 28 of the first and second buried layers 8 and 9 having good continuity as shown in FIG. 8 are obtained.
  • the impurity concentration of the phosphorus in the first and second phosphorus-introduced regions 51, 52 is the same as that of the surface of the semiconductor substrate 41, ie, the first and second antimony-introduced regions 24a, 27a. It is the highest on the surface and gradually decreases as it moves toward the lower surface of the semiconductor substrate 41.
  • the amount of phosphorus per unit area of the first selected part 49 is greater than the amount of phosphorus per unit area of the second selected part 50. That is, as described above, the ratio Sa / S1 of the total area Sa of the six first line introduction openings 47 to the area S1 of the first selection portion 49 is the second selection. part
  • the ratio of the total area Sb of the six second ring introduction openings 48 to the area S2 of 50 is larger than Sb / S2. Therefore, if the areas S l and S 2 of the first and second selected portions 49 and 50 are assumed to be the same, the amount of phosphorus in the first selected portion 49 is Is greater than the amount of lin in the selected portion 50 of.
  • the fact that the amount of phosphorus introduced into the first selected part 49 is larger than the amount of phosphorus introduced into the second selected part 50 means that the amount of phosphorus introduced into the surface of the first selected part 49 is large. This means that the average impurity concentration is higher than the average impurity concentration of phosphorus on the surface of the second selected portion 50.
  • the first, second and third antimony introduction regions 24a, 27a, 10a and the first and second phosphorus introduction regions 51, 52 are formed.
  • a third mask 54 made of a silicon oxide film having an opening 53 is formed on the surface of the formed N-type semiconductor region 6, that is, on the surface of the semiconductor substrate 41. That is, the second mask 46 in FIG. 5 is removed, and thereafter, the third mask 54 is formed. Note that the second mask 46 in FIG. 5 should not be removed. Then, a third mask 54 can be obtained by forming a silicon oxide film on the second mask 46. In the case where the P + type semiconductor region 23 a or the element isolation region 23 is formed by means other than the mask, it is not necessary to provide the third mask 54.
  • the opening 53 of the third mask 54 is formed so as to correspond to the P-type isolation region 23 of FIG.
  • P-type impurities to form the [rho tau type semiconductor region 2 3 a to P Katachihanshirube body region 6 from the opening 5 of the third mask 5 4.
  • the [rho tau type semiconductor region 2 3 a for example diffusion temperature of about 1 1 5 0 ° C, the diffusion time is formed in about 1 5 0 minutes.
  • the impurity concentration on the surface of the ⁇ ⁇ type semiconductor region 23 a is, for example, 3 ⁇ 10 18 cm— ⁇ , and the diffusion depth is, for example, about 3 jum .
  • the third mask 54 shown in FIG. 7 is removed, and the surface of the semiconductor substrate 41 is exposed. Thereafter, the first, second and third antimony introduction regions 24a, 27a, 10a and the first and second phosphorus introduction regions 51, 52 are provided.
  • an epitaxial layer 7 made of an N-type semiconductor shown in FIG. 8 is grown by a well-known vapor phase epitaxial growth method.
  • the semiconductor substrate 41 is heated to about 118 ° C.
  • the first and third portions 24 and 27 shown in FIGS. 1 and 8 are regions including both antimony and phosphorus, and the second and fourth portions 25 , 28 are regions containing phosphorus, the third buried layer 10 is a region containing antimony, and the P + -type semiconductor region 23 b is a region containing boron (as described above). Since the diffusion rate of phosphorus is higher than that of antimony, the second and fourth portions 25 and 28 comprising the phosphorus diffusion region are located above and below the first and third portions 24 and 27.
  • the thicknesses Tl and ⁇ 2 of the first and second buried layers 8 and 9 change according to the average impurity concentration of phosphorus on the surface of the substrate 41.
  • the average impurity concentration of the phosphorus in the first phosphorus-introduced region 51 of FIG. 7 is higher than the average impurity concentration of the phosphorus in the second phosphorus-introduced region 52. Therefore, the epitaxial layer 7 Based on the heat treatment in the formation process of the first and second FETs 1 and 2 and the transistor 3 after that, the region where the phosphorus is diffused, that is, the first and third FETs
  • the first and second thicknesses Tl and ⁇ 2 of the buried layers 8 and 9 have a relationship of Tl> ⁇ 2, that is, the first thickness T1 is larger than the second thickness ⁇ 2.
  • the thickness ⁇ ⁇ 3 is smaller than the first and second thicknesses ⁇ 1 and ⁇ ⁇ 2.
  • the fourth and fifth thicknesses ⁇ 4 and ⁇ 5 from the surface of the rectangular epitaxial layer 7 to the first and second buried layers 8 and 9 have a relationship of ⁇ 4 ⁇ 5.
  • the fourth thickness ⁇ 4 is thinner than the fifth thickness ⁇ 5.
  • Fifth thickness ⁇ 4 , ⁇ Greater than 5.
  • the first buried layer 8 composed of the first part 24 and the second part 25 of FIG. 8 functions as a drain current path of the first FET 1 of FIG. 1, Further, the second buried layer 9 including the third portion 27 and the fourth portion 28 functions as a drain current path of the second FET 2.
  • the tips of the plurality of first and second phosphorus introduction regions 51 and 52 are non-flat. However, due to the diffusion of phosphorus in the heat treatment in the epitaxial growth step and the subsequent steps, as shown in FIGS. 1, 8, 9 and 10, the second and third layers having a substantially uniform thickness are obtained. The parts 25, 28 of 4 are obtained.
  • N-type epitaxial layer 7 When growing the N-type epitaxial layer 7, in addition to the original N-type impurities for the N-type epitaxial layer 7, antimony, phosphorus, and boron evaporated from the substrate 41 side may be used. The power contained in layer 7 slightly.
  • a fourth mask 56 made of a silicon oxide film having an opening 55 on the surface of the N-type epitaxial layer 7 is formed.
  • the opening 55 is provided at a position for obtaining the separation region 23 in FIG.
  • boron which is a P-type impurity, is selectively diffused into the N-epitaxy layer 7 through the opening 55 of the mask 56 to form a P-type semiconductor region 23 c as shown in FIG.
  • This region 23c is connected to the lower region 2'3b and becomes a part of the separation region 23.
  • a fifth mask 60 having openings 57, 58 and 59 is formed on the upper surface of the N-type epitaxial layer 7.
  • phosphorus which is an N-type impurity, is selectively diffused into the N-type epitaxial layer 7 through the openings 57, 58, and 59 of the mask 60, thereby forming the first and second FETs.
  • the regions 14 and 18 and the collector take-out region 22 formed of an N-type semiconductor region connected to the buried layer 10 of the transistor 3 are simultaneously formed.
  • the first and second FETs shown in FIG. The P-type body regions 12 and 16 of FIG. 2 and the N-type source regions 13 and 17 and the P-type base region 20 and the N-type emitter region 21 of the transistor 3 are simultaneously formed.
  • the base electrode 39 By forming the base electrode 39, the integrated semiconductor device of FIG. 1 is completed.
  • the same selective diffusion mask is used for the body regions 12 and 16 composed of the P-type well regions of the first and second FETs 1 and 2 and the base region 20 of the transistor 3.
  • the N-type epitaxial layers 7 are formed at the same time by the diffusion of pol- lones, and the depth from the surface of the N-type epitaxial layer 7 is the same.
  • the distances T 4, T 5, and 6 from the surface of the N-type epitaxial layer 7 to the first, second, and third buried layers 8, 9, and 10 are different from each other.
  • the thickness of the first drain region 11 between the rectangular body region 12 of the first FET 1 and the first buried layer 8 is reduced to the rectangular body region 1 of the second FE layer 2.
  • second de Rei down region 1 5 thickness, collector region 1-9 thickness between layers 1 0 embedding the base region 2 0 ⁇ Pi transistor 3 between 6 and the second buried layer 9 It will be smaller.
  • the average impurity concentration of the first buried layer 8 is higher than the average impurity concentration of the second buried layer 9.
  • the resistance value of the drain current path in the ON state of the first FET 1 becomes smaller than the resistance value of the drain current path of the second FET 2. Therefore, the power loss of the first FET 1 becomes smaller than the power loss of the second FET 2.
  • the thickness of the drain region 15 of the second F ⁇ ⁇ ⁇ 2 is larger than the thickness of the first drain region 11, and the average impurity concentration of the second buried layer 9 is the first. Is lower than the average impurity concentration of the buried layer 8 of the first FET 2, so that the drain voltage of the second FET 2 is higher than the drain voltage of the first FET 1 and the drain voltage of the first FET 1. .
  • the thickness of the collector region 19 of the bipolar transistor 3 is equal to the drain region 11 of the first and second FETs 1 and 2. Since the thickness is larger than the thickness of 15, the breakdown voltage between the base and the collector and between the collector and the emitter of the transistor 3 is relatively high.
  • the first and second drain extraction regions 14 and 18 are connected to the first and third buried regions 24 and 27 in the state of FIG.
  • the collector lead region 22 is connected to the third buried layer 10.
  • the respective lead-out regions 14, 18, and 22 are filled with the first and third portions 24, 27, and the third buried portions of the first and second buried layers 8, 9.
  • these connections are made as shown in Figure 1, P-body regions 12 and 16, source regions 13 and 17, base region 20 and emitter region 2. It can be achieved by diffusion by heating during the formation of 1.
  • the first and second drain draw-out areas 14 and 18 are in the completed state of FIG. 1 and are connected to only the second and fourth parts 25 and 28. Is also good.
  • This embodiment has the following advantages.
  • the first and second buried layers 8 and 9 having different thicknesses and different average impurity concentrations can be easily formed in the same manufacturing process. That is, as shown in FIGS. 5 and 6, the first and second selection portions 49 and 50 for the first and second buried layers 8 and 9 in the same mask 46.
  • the thickness and average impurity concentration of the first and second buried layers 8 and 9 should be different only by making the patterns of the first and second phosphorus introduction openings 47 and 48 different from each other. Can be. More specifically, the ratio S a / S 1 of the total area S a of the plurality of first line introduction openings 47 to the area S 1 of the first selection portion 49 is represented by the second selection portion.
  • the ratio of the total area Sb of the plurality of second inlet holes 48 to the area S2 of 50 is made larger than Sb / S2, so that the first selected portion 4 9
  • the average impurity concentration of the phosphorus in the second selected portion 50 is higher than the average impurity concentration of the phosphorus in the second selected portion 50.
  • the thickness and the average impurity concentration of the first buried layer 8 become larger than those of the second buried layer 9.
  • the first, second, and third buried layers 8, 9, and 10 having different thicknesses and different average impurity concentrations can be easily formed. That is, the first and second buried layers 8 and 9 of the first and second FETs 1 and 2 are formed of antimony and a phosphorus having a higher diffusion speed, and the transistor 3 has The third buried layer 10 is formed of antimony. For this reason, the first, second, and third buried layers 8, 9, and 10 having different thicknesses and different average impurity concentrations are obtained by the same epitaxial growth step and the heat treatment in the subsequent steps. When the thickness of the third buried layer 10 of the transistor 3 is reduced, the thickness of the collector region 19 is increased, and the distance between the collector and the base and between the collector and the emitter is reduced. The breakdown voltage of the battery increases.
  • the first and second buried layers 8, 9 are formed not only in the phosphorus-doped region but in both the antimony-doped region and the phosphorus-doped region. As a result, the impurity concentration of the phosphorus is reduced. It can be kept relatively low, and it is possible to prevent phosphorus from entering the epitaxial growth layer on the side of the bipolar transistor 3 during the epitaxial growth process. That is, if the first and second buried layers 8 and 9 of the first and second FETs 1 and 2 are formed only of phosphorus, the buried layer 10 of the transistor 3 is formed of only antimony. For example, in the first and second buried layers 8 and 9, it is required to increase the impurity concentration of phosphorus by an amount not including antimony.
  • the impurity concentration in the phosphorus-introduced region of the substrate 41 is increased, the phosphorus is evaporated during the epitaxy growth process and the epitaxy growth layer for the transistor 3 is removed. As a result, the transistor 3 having desired characteristics cannot be obtained.
  • the anti-diffusion rate is low, and the anti-evaporation rate is low. Since mon is used for the first and second buried layers 8 and 9 together with the phosphorus, it is not necessary to increase the concentration of phosphorus more than necessary, and the transistor 3 It is possible to prevent the characteristic deterioration of the device.
  • the first and second buried layers 8, 9 are formed by a combination of antimony and phosphorus. Therefore, the thickness and impurity concentration of the first and second buried layers 8 and 9 can be easily adjusted, and the withstand voltage and on-resistance of the first and second FETs 1 and 2 can be easily adjusted. Become.
  • the P-type semiconductor region 6 It is possible to suppress the operation of a parasitic element, that is, an unnecessary element, which occurs between the first and second buried layers 8 and 9. Second embodiment
  • FIG. 11 substantially the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.
  • the semiconductor device of FIG. 11 is obtained by transforming the first and second FETs 1 and 2 of the semiconductor device of FIG. 1 into first and second bipolar transistors 1 a and 2 a, and otherwise has the same configuration as that of FIG. It is formed. That is, the semiconductor device of FIG. 11 is composed of the drain regions 11 and 15, the body regions 12 and 16, the source regions 13 and 17, and the drain lead regions 14 and 1 of the semiconductor device of FIG.
  • drain electrodes 31 and 34 instead of drain electrodes 31 and 34, source electrodes 32 and 35 and gate electrodes 33 and 36, collector areas 11a and 15a, base areas 12a and 1 6 a, E Mi jitter region 1 3 a, 1 7 a, collector leading region 1 4 a, 1 8 a, co Lek heater electrode 3 1 a, 3 4 a, E Mi jitter electrode 3 2 a, 35a and base electrodes 33a and 36a are provided, and the other portions are formed in the same manner as in FIG.
  • the first, second and third buried layers 8, 9, and 10 in FIG. Since it is formed by the same method as the embodiment, the same effect as that of the first embodiment can be obtained by the second embodiment. That is, the first, second, and third bipolar transistors la, 2a, and 3 having different characteristics can be easily formed.
  • FIG. 12 shows a second mask 46 a obtained by modifying the second mask 46 of FIG.
  • the plurality of first and second link introduction openings 47a and 48a of the second mask 46a in FIG. 12 are planar quadrangular and form rows and columns, respectively. It is arranged in a matrix so that The total areas S a and S b of the first and second ring introduction openings 47 a and 48 a have a relationship of S a> S b and have different values. Accordingly, the amount of phosphorus introduced into the first and second selection portions 49 and 50 can be made different from each other by the mask 46a in FIG. 12 as in the first embodiment. Therefore, the third embodiment has the same effect as the first embodiment. Fourth embodiment
  • FIG. 13 shows a second mask 46 b obtained by deforming the second mask 46 of FIGS. 5 and 6, and a first mask 46 b formed by using the second mask 46 b.
  • a semiconductor substrate 41 having second phosphorus introduction regions 5 la and 52 is shown.
  • the second mask 46 b of FIG. 13 is provided with a first line introduction opening 47 b which is a modification of the first line introduction opening 47 of the second mask 46 of FIG.
  • Other parts are the same as those shown in FIG.
  • the first phosphorus introduction opening 47 b in FIG. 13 consists of one opening that is slightly smaller than the first antimony introduction opening 43 a in FIG.
  • the areas Sa and Sb of the first and second ring introduction openings 47b and 48 have a relationship of Sa> Sb.
  • first and second phosphorus introduction openings 47 b and 48 shown in FIG. 13 form the first and second phosphorus introduction openings formed by introducing phosphorus into the semiconductor substrate 41.
  • Lin introduction area 5 The relationship between the impurity concentrations of 1a and 52 is similar to the relationship between the impurity concentrations of the first and second phosphorus introduction regions 51 and 52 in FIG. For this reason, the same effects as in the first embodiment can be obtained also in the fourth embodiment. Fifth embodiment
  • FIGS. 14 to 17 substantially the same parts as those in FIGS. 1 to 10 are denoted by the same reference numerals, and description thereof will be omitted.
  • the semiconductor device of the fifth embodiment shown in FIG. 14 is the same as the semiconductor device of the first embodiment shown in FIG. 1 except that the first and second buried layers 8 containing both antimony and phosphorus are used.
  • the first and third parts 2 and 27 of FIG. 9 are omitted, and other parts are the same as those in FIG. Accordingly, the first and second buried layers 8a and 9a of FIG. 14 have the same structure as the second and fourth portions 25 and 28 of FIG. Only the first and second N + type semiconductor regions 25 ′ and 28 ′ are formed.
  • a semiconductor substrate 41a composed of the P + type semiconductor region 5 and the P type semiconductor region 6 shown in FIG. 15 is prepared. This semiconductor substrate 41a does not have the first and second antimony introduction regions 24a and 27a shown in FIG.
  • a mask 46 is formed on the surface of the P-type semiconductor region 6 as shown in FIG.
  • the first mask 46 in FIG. 15 has the same pattern as the second mask 46 shown in FIGS. That is, the width W1 of the first phosphorus introduction opening 47 is larger than the width W3 of the second phosphorus introduction opening 48.
  • the lengths 11 of the first and second opening openings 47 and 48 are the same.
  • the area of the first and second selected portions 49.50 for the first and second buried layers 8a and 9a is defined as S l, S 2, six first The area of the first selected portion 49 is S 1, where S a is the total area of the opening 47 for introducing the lin and S b is the total area of the openings 48 for introducing the second lin.
  • the ratio of the total area S b of the six second ring introduction openings 48 to the area S 2 of the second area S 2 is larger than S b / S 1.
  • the phosphorus as N-type impurity is formed in the same manner as in the process of FIG. Is diffused into the P-type semiconductor region 6 to form first and second phosphorus introduction regions 51 and 52 in the same manner as in FIG.
  • the impurity concentration of the phosphorus is highest on the surface of the P-type semiconductor region 6 and gradually decreases toward the lower surface of the P-type semiconductor region 6.
  • the amount of phosphorus per unit area of the first selected part 49 is larger than the amount of phosphorus per unit area of the second selected part 50.
  • an opening is formed on the surface of the N-type semiconductor region 6 where the first and second phosphorus introduction regions 51 and 52 are formed, that is, on the surface of the semiconductor substrate 41a.
  • a second mask 54 made of a silicon oxide film having 53 is formed. That is, the first mask 46 shown in FIG. 15 is removed, and thereafter, the second mask 54 shown in FIG. 16 is formed.
  • the second mask 54 may be obtained by forming a silicon oxide film on the first mask 46 without removing the first mask 46 in FIG. 15. it can. In the case where the P + type semiconductor region 23a or the element isolation region 23 is formed by means other than the mask, it is not necessary to provide the second mask 54.
  • the second mask 54 of FIG. 16 has the same pattern as the third mask 54 of FIG.
  • the opening 53 of the second mask 54 is formed so as to correspond to the P-type isolation region 23 of FIG.
  • boron which is a P-type impurity, is diffused from the opening 53 of the second mask 54 into the P-type semiconductor region 6 to form a P + -type semiconductor region 23 a as in FIG.
  • the second mask 54 of FIG. 16 is removed, and the surface of the semiconductor substrate 41a is exposed. Thereafter, as shown in FIG. 17, the first and second antimony are removed.
  • An N-type semiconductor region is formed on the upper surface of the P-type semiconductor region 6 including the introduction region 10a and the first and second phosphorus introduction regions 51, 52, that is, the upper surface of the semiconductor substrate 41a.
  • the epitaxy layer 7 is It grows by the Charl growth method.
  • the N-type epitaxial layer 7 is formed by the vapor phase epitaxial growth method, the semiconductor substrate 41a is heated to about 118 ° C. As a result, the antimony in the antimony introduction region 10a in FIG.
  • the semiconductor substrate 41 a diffuses to the P-type semiconductor region 6 side and also simultaneously diffuses to the N-type epitaxial layer 7 side, and has different thicknesses and impurity concentrations shown in FIGS. 14 and 17.
  • the first, second, and third buried layers 8a, 9a, and 10 are obtained.
  • the thickness of the first, second, and third buried layers 8a, 9a, 10 is determined by the heat treatment at the time of forming the P-type body regions 12, 16, and the source regions 13, 17, and the like. Will also increase.
  • the first and second buried layers 8a and 9a in FIG. 17 are composed of the first and second phosphorus diffusion regions 25 'and 28'.
  • the average impurity concentration of the phosphorus in the first phosphorus-introduced region 51 of FIG. 16 is higher than the average impurity concentration of the phosphorus in the second phosphorus-introduced region 52. Therefore, the first and second buried layers 8a formed by the phosphorus diffusion of the first and second phosphorus introduction regions 51, 52 during the heat treatment in the epitaxial growth step and the subsequent steps.
  • the first and second thicknesses Tl and T2 of 9a have a relationship of T1> T2.
  • the fourth and fifth thicknesses T4 and T5 from the surface of the epitaxial layer 7 to the first and second buried layers 8a and 8b satisfy the relationship of T4 ⁇ T5.
  • the average impurity concentration of the first buried layer 8a is higher than that of the second buried layer 9a.
  • the element separation region 23, the drain lead-out regions 14, 18 and the collector lead-out region 2 are formed in the same steps as in FIGS. 9 and 10. Then, the P-type body regions 12 and 16, the N-type source regions 13 and 17, the P-type base region 20 and the N-type emitter region 21 shown in FIG. 14 are formed. It is formed by the same method as in the first embodiment.
  • the semiconductor device of the fifth embodiment shown in FIG. 14 is similar to the semiconductor device shown in FIG. Since it is the same as FIG. 1 except that it does not have the embedded regions 24 and 27 including both and, it has the same advantages as the first embodiment except for the effect of antimony. Modified example
  • another semiconductor element such as a junction type field effect transistor and a passive element such as a resistor and a capacitor can be further formed.
  • first and second ring introduction openings 47, 47 a, 48, 48 a can have the same area, and the number thereof can be changed.
  • a field effect transistor can be provided in place of the bipolar transistor 3.
  • As (arsenic) can be introduced into the first and third portions 24, 27 instead of antimony.
  • the semiconductor element can be configured such that one or both of the first buried layer 8 or 8a and the second buried layer 9 or 9a reaches the P + type semiconductor region 5.
  • an insulated gate bipolar transistor I Other semiconductor devices such as GBTs, thyristors, diodes, etc. can be formed.
  • the first and second buried layers 8 and 9 of the first and second bipolar transistors 1a and 2a in FIG. 11 should be composed of semiconductor regions containing only phosphorus as in FIG. Can be.
  • the present invention can be used for manufacturing a composite semiconductor device including a plurality of transistors or FETs.

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Abstract

L'invention concerne un procédé de fabrication de dispositifs semi-conducteurs présentant diverses caractéristiques sur le même substrat semi-conducteur. Des première et seconde régions d'introduction d'antimoine (24a, 27a) sont crées dans une région semi-conductrice de type P (6) d'un substrat semi-conducteur (41), de manière à former des première et seconde couches enterrées TEC (,9). Un masque (46) présentant des première et seconde ouvertures d'introduction de phosphore (47, 48) de différentes formes est placé sur le substrat semi-conducteur (41). Du phosphore est introduit dans le substrat semi-conducteur (41) par l'intermédiaire des ouvertures (47, 48). Des première et seconde régions d'introduction de phosphore (51, 52) sont ainsi formées de manière à chevaucher les première et seconde régions d'introduction d'antimoine (24a, 27a). La teneur moyenne en impuretés de phosphore d'une première partie sélectionnée (49) pour la première couche enterrée est supérieure à celle d'une seconde partie sélectionnée (50) pour la seconde couche enterrée. Une couche épitaxiale de type N est formée sur la région semi-conductrice de type P (6) comprenant les régions d'introduction d'antimoine (24a, 27a) et les régions d'introduction de phosphore (51, 51). Par conséquent, les première et seconde couches enterrées sont formées.
PCT/JP2003/000257 2002-01-16 2003-01-15 Procede de fabrication de dispositif semi-conducteur WO2003061009A1 (fr)

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EP03701731A EP1475837A4 (fr) 2002-01-16 2003-01-15 Procede de fabrication de dispositif semi-conducteur
US10/890,688 US7074663B2 (en) 2002-01-16 2004-07-14 Method of making semiconductor device including a first set of windows in a mask with larger ratio of surface area than a second set of windows

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TW594946B (en) 2004-06-21
KR20040083077A (ko) 2004-09-30
EP1475837A4 (fr) 2007-11-28
US20040248389A1 (en) 2004-12-09
JPWO2003061009A1 (ja) 2005-05-19
KR100649292B1 (ko) 2006-11-24

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