WO2003055074A1 - Grille logique multi-entrees - Google Patents

Grille logique multi-entrees Download PDF

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Publication number
WO2003055074A1
WO2003055074A1 PCT/JP2002/013191 JP0213191W WO03055074A1 WO 2003055074 A1 WO2003055074 A1 WO 2003055074A1 JP 0213191 W JP0213191 W JP 0213191W WO 03055074 A1 WO03055074 A1 WO 03055074A1
Authority
WO
WIPO (PCT)
Prior art keywords
resistor
circuit
transistors
input
gate
Prior art date
Application number
PCT/JP2002/013191
Other languages
English (en)
Japanese (ja)
Inventor
Yukio Shimpo
Akihiro Yamagishi
Tsuneo Tsukahara
Original Assignee
Nippon Telegraph And Telephone Corporation
Ntt Electronics Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph And Telephone Corporation, Ntt Electronics Corporation filed Critical Nippon Telegraph And Telephone Corporation
Publication of WO2003055074A1 publication Critical patent/WO2003055074A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic

Definitions

  • the present invention relates to a CMOS multi-input logic gate, and more particularly to a CMOs multi-input logic gate operable with a small signal amplitude and capable of reducing power consumption.
  • logic circuits such as a NAND circuit, a NOR circuit, and a NOT circuit have been manufactured by a CMOS process, which is a process of manufacturing by combining two types of transistors called MOSFETs.
  • the operation of a logic circuit manufactured by such a CMOS process can be sped up by miniaturization of the circuit. Further, the operation can be further accelerated by operating in the current mode logic in addition to the above miniaturization.
  • FIG. 1 is a diagram showing the configuration of a conventional N ⁇ R circuit using current mode logic.
  • This NOR circuit is manufactured by the CMOS process described above.
  • the operation speed of this NOR circuit is increased by the above-described miniaturization.
  • the operation of this conventional NOR circuit is as follows.
  • the conventional NOR circuit determines the gate voltage High and Low using the threshold voltage VR.
  • a threshold voltage V R is required to determine the data High and Low.
  • the power supply voltage required to operate this circuit must be the voltage value obtained by adding the signal amplitude to the operating voltage of each transistor.
  • an object of the present invention is to provide a multi-input logic gate that can operate with a small signal amplitude and that can achieve low power consumption. Disclosure of the invention
  • a first resistor and a second resistor each having one end connected to a power supply, a current source, and a source are connected in parallel to the current source, and a drain is connected in parallel.
  • M transistors (m is an integer of 2 or more) connected to the other end of the first resistor, and a source and a drain between the current source and the other end of the second resistor.
  • Has m transistors connected in series, and m sets of differential input signals are input to the gates of the transistors connected in parallel and the gates of the transistors connected in series, respectively.
  • the first resistance This is a multi-input logic gate characterized in that a differential signal is output from the other end of each of the resistor and the second resistor.
  • the signal amplitude of the NOR circuit can be reduced to about 1 Z 2 of the signal amplitude of the conventional NOR circuit. Therefore, according to the NOR circuit according to the present invention, low power consumption can be achieved.
  • FIG. 1 is a diagram showing the configuration of a conventional NOR circuit using the current 'mode' logic.
  • FIG. 2 is a diagram showing a configuration of an N 0 R circuit according to an embodiment of the present invention.
  • FIG. 2 is a diagram showing a configuration of a NOR circuit according to an embodiment of the present invention.
  • the NOR circuit operates in a current 'mode' logic to ensure high speed.
  • Rl and R2 are resistors
  • M1 to M4 are transistors
  • I-1 is a current source
  • AP, BP, AN, and BN are input signals
  • YP and YN are output signals. I have.
  • the circuit of FIG. 2 operates as N AND when the input and output polarities are reversed. At this time, an AND signal is output to YN.
  • the multi-input logical gate according to the present invention can increase the operation margin with a small signal amplitude. Therefore, according to the multi-input logic gate of the present invention, the power supply voltage can be reduced, and the power consumption can be reduced.

Landscapes

  • Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'invention concerne une grille logique multi-entrées présentant une première résistance, et une seconde résistance dont, pour chacune de ces résistance, une extrémité est reliée à une source d'alimentation, une source de courant, m éléments de transistors (m désignant un nombre entier supérieur ou égal à 2), dont les sources sont reliées en parallèle à la source de courant, et dont le drain est relié aux autres extrémités des premières résistances, et m éléments de transistors dont les sources et les drains sont reliés en série entre la source de courant et les autres extrémités des secondes résistances. M paires de signaux d'entrées différentiels sont entrées respectivement dans les grilles des transistors reliés en parallèle et dans les grilles des transistors reliés en série, et sont sortis à partir des autres extrémités des premières et des secondes résistances respectivement, en tant que signaux différentiels.
PCT/JP2002/013191 2001-12-20 2002-12-17 Grille logique multi-entrees WO2003055074A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-386875 2001-12-20
JP2001386875A JP2003188714A (ja) 2001-12-20 2001-12-20 多入力論理ゲート

Publications (1)

Publication Number Publication Date
WO2003055074A1 true WO2003055074A1 (fr) 2003-07-03

Family

ID=19188004

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/013191 WO2003055074A1 (fr) 2001-12-20 2002-12-17 Grille logique multi-entrees

Country Status (2)

Country Link
JP (1) JP2003188714A (fr)
WO (1) WO2003055074A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114630A (ja) * 1981-12-28 1983-07-08 Fujitsu Ltd 論理回路
JPS62261225A (ja) * 1986-05-07 1987-11-13 Nec Corp 論理回路
JP2001244808A (ja) * 2000-02-29 2001-09-07 Toshiba Corp 論理演算機能を備えた半導体集積回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58114630A (ja) * 1981-12-28 1983-07-08 Fujitsu Ltd 論理回路
JPS62261225A (ja) * 1986-05-07 1987-11-13 Nec Corp 論理回路
JP2001244808A (ja) * 2000-02-29 2001-09-07 Toshiba Corp 論理演算機能を備えた半導体集積回路

Also Published As

Publication number Publication date
JP2003188714A (ja) 2003-07-04

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