Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers

Definitions

• the present invention is related to semiconductor devices and, more specifically, to a transistor metal gate structure that minimizes non-planarity effects.
• high-k material or “high dielectric constant material” refers to any material with a dielectric constant that is greater than silicon dioxide.
• the dielectric constant of silicon dioxide is approximately 3.9.
• metal gate structures can be used.
• One method used to form transistor metal gate structures includes depositing metal layers within a gate trench, meaning a trench where a gate will subsequently be formed, and along the top surface of insulating materials surrounding the gate trench. An etch back or polishing process is used to remove the portions of the metal layers lying outside the gate trench.
• CMP chemical mechanical polishing
• FIG. 1 illustrates a cross-sectional view of a semiconductor device after removing the dummy gate in a replacement gate integration in accordance with an embodiment of the present invention
• FIG. 2 illustrates the semiconductor device in FIG. 1 after depositing a gate dielectric and a gate electrode in accordance with an embodiment of the present invention
• FIG. 3 illustrates the semiconductor device in FIG. 2 after depositing a stop layer in accordance with an embodiment of the present invention
• FIG. 4 illustrates the semiconductor device in FIG. 3 after depositing a metal layer in accordance with an embodiment of the present invention
• FIG. 5 illustrates the semiconductor device in FIG. 4 after removing portions of the metal layer in accordance with an embodiment of the present invention
• FIG. 6 illustrates the semiconductor device in FIG. 5 after removing portions of the metal layer, the stop layer, the gate electrode layer and the gate dielectric in accordance with an embodiment of the present invention.
• a control electrode dielectric layer is formed adjoining all surfaces of a control electrode trench and extending beyond the control electrode trench.
• a control electrode layer is formed adjoining the control electrode dielectric layer in the control electrode trench.
• a stop layer is formed within the control electrode trench over the control electrode dielectric layer. Both the control electrode layer and the stop layer fill less than all of the control electrode trench.
• a conductive layer is formed adjoining all exposed surfaces of the stop layer and extending beyond the gate trench and substantially filling all the remaining volume of the control electrode trench.
• the control electrode dielectric layer, the control electrode layer, the stop layer and the conductive layer form a control electrode stack overlying a channel area in a substrate and having a lateral dimension and a height defining the control electrode trench that is determined by a sidewall spacer.
• FIG. 1 illustrates a cross-section of a semiconductor device or integrated circuit 10 including a semiconductor substrate 12, a source region 14, a drain region 16, sidewall spacers 18 and an interlevel dielectric layer (ILD) 20 after removing a dummy gate stack to form a gate trench 19 in a replacement gate integration, as known to a skilled artisan.
• ILD interlevel dielectric layer
• the semiconductor substrate 12 can be any semiconductor material such as silicon, gallium arsenide, silicon germanium and the like.
• the semiconductor substrate 12 can be the silicon layer of a silicon-on-insulator (SOI) substrate.
• the source region 14 and the drain region 16 are doped a conductivity that is opposite that of the semiconductor substrate 12, if doped, and are separated from each other to define a channel area in the semiconductor substrate 12.
• the sidewall spacers 18 are insulating and, preferably, include a nitride or oxide material. In one embodiment, the sidewall spacers 18 are a stack of insulating materials.
• the ILD layer 20 is an insulating material, such as silicon dioxide, and can also include a stack of insulating materials. The ILD layer 20 adjoins an outer perimeter of the sidewall spacers and will insulate the subsequently formed transistor structure.
• a gate dielectric or control electrode dielectric 22 and a gate electrode 24 are formed in the gate trench 19 and along the upper surface of the ILD LAYER 20 by CVD
• the gate dielectric layer 22 can be any dielectric material, such as silicon dioxide, a high-k material, a metal-oxy-nitride, a metal oxide, a metal silicate, or a metal aluminate.
• the gate dielectric layer 22 can be silicon nitride, silicon dioxide, Hf0 2 , Zr0 2 , HfSi x O y , SiO x N y , and the like.
• the gate dielectric layer 22 is approximately 10 Angstroms to 60 Angstroms.
• the gate electrode or current electrode 24 can be a metal nitride (such as TiN, TaN, TiSiN, TaSiN), a conductive metal oxide (such as IrO, RuO, or a metal aluminum nitride (such as Ti x Al y N z ), a metal suicide, a metal-silicon-nitride, or any other material that has a suitable work function.
• a suitable work function is a material property that determines the desired threshold voltage value for the transistor.
• the gate electrode 24 will be a thickness that is less than half of the gate length of the transistor and greater than 10 Angstroms.
• a stop layer 26 is formed, by CVD, PVD, ALD, MBE, plating, the like, or combinations of the above, as shown in FIG. 3.
• the stop layer 26 is conductive and can be a pure metal (such as Ti, Ta, Ag, Au, Ir or Ru), a metal suicide (such as cobalt suicide or titanium suicide), or silicon.
• the stop layer 26 can serve as an etch stop layer and/or a polish stop layer for the subsequently formed overlying layers.
• the stop layer 26 can be a polish stop layer for a chemical mechanical polish (CMP) or a physical mechanical polish of the overlying materials.
• CMP chemical mechanical polish
• the stop layer 26 is a polish stop layer
• a thickness of 50 Angstroms has shown to be sufficient using conventional CMP equipment.
• the stop layer 26 can be a stop layer for a chemical etch back of the overlying materials
• a conductive layer 28 is formed over the semiconductor device 10 by CVD, PVD, ALD, MBE, plating, the like or combinations of the above.
• the conductive layer 28 is a conductive material with a low resistivity and can be a metal (such as W, Al, Au, Cu, Ag, Pt), a metal suicide or silicon, the like, or combinations of metals.
• the conductive layer 28 should be able to be polished or etched selectively to the stop layer 26 material.
• the conductive layer 28 is thicker than the sum total of the thicknesses of the stop layer 26, the gate electrode layer 24 and the gate dielectric layer 22.
• the stop layer 26, the gate electrode layer 24, and the gate dielectric layer 22 are thinner than the conductive layer 28.
• the thickness of the conductive layer 28 is approximately twice the depth of the gate trench 19.
• a portion of the conductive layer 28 is polished or etched until the stop layer 26 is exposed as shown in FIG. 5. This is performed by using a process that is selective to the material chosen for the stop layer 26. For example, if the conductive layer 28 is tungsten and the stop layer 26 is titanium a CMP chemistry using FeN0 3 can be used. The chemistry used to remove materials suitable for the conductive layer 28 tends to not be selective to metal nitrides or other gate electrode type materials, however, the chemistry is selective to materials disclosed for the stop layer 26.
• a different polish or etch process is performed to remove the stop layer 26, the gate electrode layer 24 and the gate dielectric layer 22.
• the ILD LAYER 20 will serve as a second stop material for the selective layer removal of overlying materials.
• the semiconductor device 10 can be switched to a different platen in the CMP tool with a different slurry and pad to remove the stop layer 26, the gate electrode layer 24 and the gate dielectric layer 22 selective to the ILD LAYER 20.
• a chemistry using ammonium hydroxide can be used to CMP the three layers 26, 24, and 22.
• the resulting structure after removing the portions of the gate electrode stack or control electrode stack - which includes the conductive layer 28, the stop layer 26, the gate electrode layer 24, and the gate dielectric layer 22 - that are over the ILD LAYER 20 is a transistor metal gate structure with a minimum dishing or recessing of the gate or control electrode stack.
• the dishing of the ILD LAYER 20 is also minimized in other areas of the semiconductor substrate 12 (not shown).
• yield is increased due to the decrease in dishing.
• the presence of the stop layer 26 allows for at least a two-step polish or etch process to be performed.
• Another advantage of the invention is that it allows for the selection of the gate electrode material independently of its polishing or etching characteristics. Therefore, the present invention provides for a wider range of choices for the gate electrode material than if the stop layer 26 is not used.
• a transistor metal gate with minimized non- planarity After forming a transistor metal gate with minimized non- planarity, traditional additional processing (not shown) known to one skilled in the art is performed. For example, a second ILD material is deposited over the structure shown in FIG. 6 and metal interconnects are subsequently formed.

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Composite Materials (AREA)
• Chemical & Material Sciences (AREA)
• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Thin Film Transistor (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (2)

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• 2001
  • 2001-11-30 US US09/997,899 patent/US6423619B1/en not_active Expired - Lifetime
• 2002
  • 2002-11-13 KR KR10-2004-7007928A patent/KR20040063971A/ko not_active Withdrawn
  • 2002-11-13 WO PCT/US2002/036653 patent/WO2003049186A2/en not_active Ceased
  • 2002-11-13 AU AU2002365768A patent/AU2002365768A1/en not_active Abandoned
  • 2002-11-13 EP EP02804420A patent/EP1451859A2/en not_active Withdrawn
  • 2002-11-13 CN CNB028236610A patent/CN1306561C/zh not_active Expired - Lifetime
  • 2002-11-13 JP JP2003550282A patent/JP4159471B2/ja not_active Expired - Lifetime
  • 2002-11-29 TW TW091134782A patent/TWI251345B/zh not_active IP Right Cessation

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