WO2003044864A1 - Semiconductor Devices - Google Patents

Semiconductor Devices Download PDF

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Publication number
WO2003044864A1
WO2003044864A1 PCT/CN2002/000674 CN0200674W WO03044864A1 WO 2003044864 A1 WO2003044864 A1 WO 2003044864A1 CN 0200674 W CN0200674 W CN 0200674W WO 03044864 A1 WO03044864 A1 WO 03044864A1
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region
semiconductor
layer
contact
conductivity type
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PCT/CN2002/000674
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English (en)
French (fr)
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Xingbi Chen
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Tongji University
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Priority to AU2002338003A priority Critical patent/AU2002338003A1/en
Priority to US10/504,575 priority patent/US7230310B2/en
Publication of WO2003044864A1 publication Critical patent/WO2003044864A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device, particularly a withstand layer of a semiconductor power device. Background technique
  • the reverse voltage applied to the n + region and p + region is supported by a lighter and thicker doped semiconductor layer.
  • This layer is hereinafter referred to as a voltage-resistant layer (Voltage Sustaining Layer).
  • Voltage Sustaining Layer Voltage Sustaining Layer
  • the on-resistance. (or the on-voltage drop) is also mainly determined by the withstand voltage layer. The lighter the doping of this layer, or the greater the thickness, or both, the breakdown The higher the voltage, the greater the on-resistance (or on-voltage drop). In many power devices, one of the most important issues is to have both a high breakdown voltage and a low on-resistance.
  • the relationship between the two becomes an obstacle to the manufacture of high-performance power devices.
  • the above refers to the resistance per unit area of the conduction region in the voltage-resistant layer, and in fact, some areas of the voltage-resistant layer do not participate in conduction.
  • the area under the source substrate area of the vertical (vertical) MOSFET and the area under the contact layer of the base region of the bipolar transistor are all areas that do not participate in conduction.
  • the inventor's Chinese invention patent ZL91101845.X and US invention patent 5,216,275 solve the above problems.
  • the solution is to use a composite buffer layer (or CB layer for short) in the p + region and n + region to withstand pressure.
  • the CB layer contains two regions of opposite conductivity types. These two regions are arranged alternately from any cross section parallel to the interface between the CB layer and the n + layer (or p + layer).
  • the voltage-resistant layers used before were all single-conductivity semiconductors.
  • the invention also discloses a MOST composed of such a voltage-resistant layer, and an on-resistance R per unit area. SwiftProportional to the 1.3th power of the breakdown voltage.
  • FIG. 1 (a) and FIG. 1 (b) represent a manufacturing method of a super-junction power device 1.
  • the process is to first grow a first epitaxial layer 3 from a semiconductor wafer of a substrate 2.
  • the substrate 2 is a heavily doped n + layer
  • the first epitaxial layer 3 is a lightly doped n layer, in which a p-type region 4 is ion-implanted.
  • an epitaxial layer is required for every 50 to 100 volts. Therefore, for a 600V transistor, the n-type epitaxial layers of 5, 7, 9, 11, and 13 in FIG. 1 (a) must be sequentially formed, and 6, 8 in FIG. 10, 12 and 14 p-type ion implanted layers.
  • the formed p-type ion implantation layers 4, 6, 8, 10, 12 and 14 form the p-region 16 in FIG. 1 (b) after diffusion, and the region not affected by the ion implantation is the n-region 15. This forms the p and n regions arranged alternately.
  • the device layer or device feature layer 17 is made.
  • the device characteristic layer 17 contains an n + source region 18 formed by ion implantation, an oxide layer 19 and a metal gate or a polysilicon gate 20 thereon.
  • the above manufacturing method uses multiple epitaxy and is expensive.
  • the CB layer structure uses the principle of charge compensation, in which the doping of the p and n regions must be accurately controlled, which also increases the difficulty of manufacturing and increases the cost of the device.
  • Another disadvantage of the MOST containing the CB layer structure is that when the conduction current is large, the charge of the carrier itself will affect the charge balance, causing a secondary breakdown phenomenon in which the breakdown voltage decreases as the current increases, making the safe operating area ( SOA) is not ideal.
  • Another disadvantage of the MOST with the CB layer structure is that there are two voltages between the p-region and the n-region: one is the built-in voltage, and the other is the additional resistance generated by the on-resistance in that region when it is turned on. Voltage. These two voltages make There is a depletion region between the two regions, thereby reducing the effective cross-sectional area of the conduction region. In other words, the on-resistance increases as the current increases.
  • An object of the present invention is to provide a semiconductor device including a new structure withstand voltage layer, called a semiconductor
  • High K composite pressure-resistant layer referred to as high dielectric semi-pressure-resistant layer or high dielectric half layer (High K and Semiconductor Layer, or HKS-Layer). It can avoid the above disadvantages, while making the on-resistance?.
  • the relationship between ,, and the breakdown voltage B is improved, and has a high switching speed.
  • the present invention provides a semiconductor device including a voltage-resistant layer between a conductive contact layer and a conductive device feature layer, the voltage-resistant layer includes at least one semiconductor region and at least one dielectric region having a high dielectric constant.
  • the semiconductor region and the dielectric region are both in contact with an interface formed by the device feature layer and the contact layer.
  • the semiconductor region and the dielectric region are in contact with each other, and a contact surface formed by the semiconductor region and the dielectric region is perpendicular or approximately perpendicular to the contact layer and the device. Feature layer.
  • Both the semiconductor region and the dielectric region are in contact with the interface formed by the device feature layer and the contact layer, which may be direct contact or indirect contact through a thin semiconductor region or a thin dielectric region.
  • the semiconductor region and the dielectric region are in contact with each other, which may be direct contact or indirect contact through a thin dielectric region having a low dielectric constant.
  • a cell may be formed by at least one of the semiconductor region and at least one of the dielectric region, and many of the cells are closely arranged to form the pressure-resistant layer.
  • the semiconductor region may be composed of a semiconductor of a first conductivity type, a device feature layer is a semiconductor region containing a heavily doped second conductivity type, and a contact layer is a semiconductor of a first conductivity type that is heavily doped.
  • the semiconductor region may be constituted by a semiconductor of a first conductivity type, and the contact layer is constituted by a thin semiconductor of a first conductivity type on a heavily doped semiconductor of the first conductivity type, A conductive type semiconductor is in direct contact with the voltage-resistant layer.
  • the semiconductor region may include both the semiconductor portion of the first conductivity type and the semiconductor portion of the second conductivity type, wherein both the semiconductor of the first conductivity type and the semiconductor of the second conductivity type are in contact with the device characteristic layer and The layer is in direct contact, and the device feature layer is a semiconductor region containing a heavily doped second conductivity type.
  • the semiconductor region may contain both the semiconductor portion of the first conductivity type and the semiconductor portion of the second conductivity type, wherein the semiconductor of the first conductivity type is in direct contact with the device feature layer and the contact layer, and the second conductivity
  • the type of semiconductor is in direct contact with the characteristic layer of the device, and indirectly contacts the contact layer through a thin dielectric layer with a high dielectric constant or a thin dielectric layer with a low dielectric constant, and the characteristic layer of the device contains a heavy miscellaneous element.
  • the two semiconductors of different conductivity types may have a dielectric region with a high dielectric constant.
  • the contact layer may be a heavily doped semiconductor of a second conductivity type.
  • the contact layer may have a thin semiconductor layer of the first conductivity type on a heavy semiconductor layer of the second conductivity type, and the thin semiconductor layer of the first conductivity type is directly connected to the withstand voltage layer. contact.
  • Figure 2 Description of the withstand voltage layer (within the W distance is the withstand voltage layer), which represents a pin diode;
  • Figure 3 (a): Usually RMOST and its electric field distribution, showing the schematic diagram of RMOST structure
  • One side of the dielectric material is a p-type semiconductor region and one side is an n-type semiconductor region;
  • Figure 8 (a): Schematic diagrams of various structures of the HKS pressure-resistant layer containing p-region and n-region along the section III- ⁇ in Figure 5 (d), which shows the interdigitated pattern;
  • Figure 8 (d) Schematic diagrams of various structures of HKS pressure-resistant layer containing p-regions and n-regions along the section III-II- ⁇ in Figure 5 (d);
  • Figure 8 (h) Schematic diagrams of various structures of the HKS pressure-resistant layer containing p-region and n-region along the ⁇ - ⁇ cross-section in Figure 5 (d), showing the hexagonal close-packed pattern of the n-region fully connected;
  • Fig. 8 (i) Various structural schematic diagrams of the HKS pressure-resistant layer containing the p-region and the n-region along the III-III 'cross-section in Fig. 5 (d), showing the hexagonal close-packed pattern of the p-region fully connected;
  • Figure 9 Schematic of a HKS voltage-resistant layer with a thin, low-dielectric Si0 2 layer between the high-dielectric constant material and the semiconductor material;
  • Figure 11 Schematic diagram of n-VDMOST formed by a high dielectric constant material passing through a lightly miscellaneous n-region and then in contact with the n + -drain region.
  • Figure 12 A schematic diagram of n-VDMOST using the HKS pressure-resistant layer of Figure 5 (d).
  • Figure 13 A schematic diagram of n-VDMOST using the HKS voltage-resistant layer of Figure 5 (d), but the p-region is not in direct contact with the n + drain region.
  • Figure 14 A schematic diagram of an IGBT using the HKS voltage-resistant layer of Figure 5 (d).
  • FIG. 15 A schematic diagram of an IGBT using the HKS voltage-resistant layer of Figure 5 (d) but with a buffer layer. Best Mode of the Invention In semiconductor power devices, there is generally a withstand voltage layer between the p + region (or equivalent to the p + region) and the n + region (or equivalent to the 11+ region).
  • FIG. 2 (a) is a schematic diagram of a pin diode, which is composed of a p + region 24, an n + region 25, and an i region 23, where the i region 23 is a withstand voltage layer.
  • A is the anode of the diode and K is the cathode of the diode.
  • FIG. 2 (b) is a schematic diagram of a p + n-n + diode, where the thickness of the depletion layer of the n-region 26 when the reverse bias voltage is applied to the breakdown voltage is the voltage-resistant layer.
  • Figure 2 (c) is a schematic diagram of an electronically conductive n-RMOST.
  • S is the source electrode
  • G is the gate electrode
  • D is the drain electrode.
  • the gate oxide layer 32 is not a p + region, but because the potential on the plane 31 below the gate oxide layer 32 and the interface between the p + source substrate region 29 and the n region 27 are actually used The potential phases are similar, and the difference is much smaller than the breakdown voltage of the device, so it can be regarded as an equipotential plane.
  • FIG. 3 is a schematic diagram of a VDMOST.
  • the plane 31 can be approximated here as an equipotential with the p + source substrate region 29. Therefore, in the present invention, a region below the plane 31 to the interface between the n region 27 and the n + drain region 28 is used as the pressure-resistant layer 34. A region above the plane 31 is used as the device feature layer 33.
  • the edge of the depletion region has reached the interface between the n-type region 27 and the ⁇ + drain region 28 when the reverse bias voltage is applied to the two MOSTs before the breakdown voltage ⁇ ⁇ is reached. Therefore, the thickness of the pressure-resistant layer is as shown in the figure, and this assumption is consistent with the usual actual situation.
  • both sides of the withstand voltage layer are semiconductors of the p + region and the ⁇ + (or ⁇ ) region.
  • the device characteristic layer may not be a p + region, but a metal, and it forms a Schottlcy contact with the n region of the voltage-resistant layer.
  • Figure 2 (e) shows a schematic diagram of a Schottky diode.
  • the metal layer 35 is used in place of the p + layer in the above case.
  • the pressure-resistant layer may not be in contact with the n + (or 11) region, but in contact with the metal to form a Schottky contact. Therefore, we call the contact area under the pressure-resistant layer the contact layer.
  • Fig. 2 (f) shows the situation of a close-through IGBT. It is considered that the p + layer 36 is in contact with the pressure-resistant layer.
  • Figure 3 (a) is a schematic diagram of RM0ST. It is composed of ⁇ region 27, ⁇ + source region 30, ⁇ + source substrate region 29, and ⁇ + drain region 28.
  • G is the gate
  • S is a source electrode
  • D is a drain electrode.
  • the voltage-resistant layer is a depletion region 34 of the thickness shown in the figure.
  • Figure 3 (b) shows the electric field distribution when the bias voltage approaches the breakdown voltage in RMSOT, E Represents the electric field in the y direction of the coordinate axis.
  • the gradient of the electric field is N /.
  • 7 ⁇ 3 ⁇ 4 represents the donor concentration in the n region.
  • avalanche breakdown occurs. Breakdown
  • the value of the critical electric field E e felicit7 is about 3 ⁇ 10 5 V / cm, and the area of the shaded area between E and j; represents the integral of the electric field to the path, that is, the breakdown voltage V B.
  • the following two conditions must be satisfied: (1) the gradient of the electric field is small and g , N D is small; (2) the width of the depletion region is large.
  • ⁇ is small, which means that the carrier concentration of the voltage-resistant layer is small and the resistivity is high.
  • the large width of the depletion layer represents a long conduction path. Since the on-resistance is directly proportional to the resistivity and path length, this will greatly increase the on-resistance.
  • the best design is that the electric field near the n region 27 and the n + drain region 28 is E C J3, and the breakdown voltage is 2E e , it ⁇ WI3.
  • the above electric field distribution can be considered as the superposition of two electric fields.
  • One is the electric field caused by the applied voltage on a pin diode, as shown in Figure 3 (c).
  • the value of the electric field is equal to 2 ,. ⁇ / 3 and does not change with distance.
  • the other is a linearly changing electric field from the bottom electric field value to the top electric field value + E m3 ⁇ 4 / 3.
  • its gradient is qN D le s and its peak is-(7N 0 W / 2 s s R + qN D WI2.
  • the latter electric field causes the on-resistance R 0 to increase as the breakdown voltage increases.
  • FIG. 4 (a) is a schematic diagram of a CB-RMOST. Its pressure-resistant layer 34 is composed of n-region 27 and p-region 37 Alternately arranged, its thickness is W.
  • the electric field of the line I-I 'in the n-region 27 is shown by a solid line in FIG. 4 (b). It is basically constant, but changes slightly near the plane 31 and near the n + drain region 28. This electric field can also be decomposed into two 3 ⁇ 4 fields as shown in Fig. 4 (c) and Fig. 4 (d).
  • Fig. 4 (c) corresponds to the case of a pin diode, as in Fig.
  • Fig. 4 (d) shows the vertical electric field generated by the n-region 27. This electric field is much smaller than the electric field of Fig. 3 (d) at the same miscellaneous concentration. In fact, the N D in the CB structure can be large, and the electric field generated is still much smaller. Because the vertical electric field generated by the positive charge of the ionized donor does not continuously accumulate from the middle of the voltage-resistant layer, but the power lines generated by the ionized donor near the top and bottom of the n-region 27 are negatively charged by the gate electrode G above. The charge and the negative charge of the n + drain region 28 below are terminated, while the electric field of the ionizing donor farther from the top and bottom of the n region 27 is terminated by the ionizing acceptor of the surrounding p region 37.
  • the voltage-resistant layer structure proposed by the present invention is to arrange a material with a high dielectric constant and a semiconductor phase to form a situation as shown in FIG. 5, where HK in the figure represents a material with a high dielectric constant.
  • the dielectric coefficient is not the dielectric coefficient of the semiconductor material but a value larger than that. Much larger, but a value smaller than the dielectric constant of a high dielectric constant material. Roughly speaking, if there is a permittivity after mixing, then e M »e s . This makes the slope like Fig. 3 (d) become very small at the same miscellaneous concentration and becomes qN D le M. In other words, you can use the larger value of 7 ⁇ 3 ⁇ 4 to get the same peak electric field E Struktur., 7/3.
  • the HKS layer of the present invention When the HKS layer of the present invention is used as a pressure-resistant layer, when the n-type region 27 is depleted, most of the electric flux lines emitted by the ionization donor will go laterally into the adjacent medium 38 with a high dielectric constant, and finally pass through the high dielectric constant medium 38.
  • the medium 38 with the dielectric constant goes to the top and is absorbed by the negative charge induced in the p + region 24. Therefore, the value of the maximum electric field generated by the ionized donor in the n-type layer 27 is much smaller than qN D ⁇ / 2.
  • these electric flux lines coming in from the n-type region 27 are similar to the ones that generate many ionized donors. But because of its large size, the electric field generated by itself is small.
  • Figures 5 (c) and 5 (d) show the inventor's Chinese invention patent ZL91 101845.X and US invention patent 5,216,275 in the CB structure with a high dielectric constant HK material.
  • n-zone 27 In the non-ideal situation of n-zone 27 being too light, there is an electric flux line from the bottom n + -zone 25, which flows through the medium 38 with a high dielectric constant and then flows to the p-zone 37, ending with the excess ionizing acceptor charge Above.
  • the semiconductor region in the pressure-resistant layer of the present invention may be an n-type region, a p-type region, or both. Therefore, when there is no need to point out in the following, the semiconductor region S will be uniformly represented.
  • the HKS layer there are many structural patterns in the arrangement of the high-dielectric-constant material and the semiconductor region.
  • FIG. 6 shows a method of arranging a plurality of high-dielectric-constant materials and semiconductor regions along a ⁇ -II ′ cross-section as shown in FIG. 5 (a). Many cells are divided by dotted lines in the figure.
  • FIG. 6 (a) shows interdigitated bar graphs ( Figure 6 (a)), fully connected square-shaped cell patterns in the semiconductor region ( Figure 6 (b)), and fully connected square-shaped cell patterns in the HK region ( Figure 6 (c)).
  • Figure 6 (d) Fully connected rectangular cell pattern in semiconductor area
  • Figure 6 (e) Fully connected rectangular cell pattern in HK area
  • Figure 6 (f) Mosaic block pattern
  • Figure 6 (f) Fully connected semiconductor area Hexagonal close-packed pattern
  • Figure 6 (h) a hexagonal close-packed pattern with full connectivity in the HK area
  • Fig. 7 (a) is a schematic diagram of a structure using HKS layer as MOST.
  • a typical numerical calculation example can illustrate its superiority. It is assumed that an interdigitated stripe pattern is used, each cell width is 13.04 ⁇ , ⁇ region 27 and HK region 38 each occupy half the width, and the thickness of the HKS layer is 65 ⁇ .
  • the donor concentration in the ⁇ region is 2.07 ⁇ 10 15 cm_ 3 ,
  • the relative permittivity of high dielectric constant materials is equal to 234 (twenty times higher than the relative permittivity of silicon).
  • the simulation calculation was performed by using the MEDICI software, and a standard model was used.
  • the obtained breakdown voltage was 750 volts, and the specific on-resistance was 30 ⁇ ⁇ cm 2 .
  • the specific on-resistance of the conventional RMOST at the same breakdown voltage is 123 mQ ⁇ cm 2 .
  • Figure 7 (b) and Figure 7 (c) show the transient current characteristics of turn-on and turn-off at a 750-volt power supply series resistance of 5.75 ⁇ 10 7 ⁇ ⁇ ⁇ m, respectively.
  • the gate voltage used is changed from 0V to 20V and from 20V to 0V. It can be seen that the rise and fall times are lns, the turn-on time is less than 2ns, and the turn-off time is less than 80ns.
  • Another advantage is that there is no depletion of the n-region 27 caused by the built-in voltage of the p-region and the n-region or the additional voltage when the current passes, as in the MOST made by the CB structure. Therefore, the on-resistance does not increase as the drain-source voltage increases. Only when the voltage is very large, the electron velocity in the 11 region 27 (also called the drift region) is saturated, and the resistance is increased.
  • FIG. 8 shows many structural diagrams of the arrangement of the high-dielectric-constant material and the n-type semiconductor region and the p-type semiconductor region in the cross section of III-II ′ ′ in FIG. 5 (d).
  • These figures include interdigitated bar graphs ( Figure 8 (a)), fully connected square-shaped cell figures in the ⁇ region ( Figure 8 (b)), and fully connected square-shaped cell figures in the p region ( Figure 8 (c ;, n region Fully connected rectangular cell graphics ( Figure 8 (d)), p-area fully connected rectangular cell graphics ( Figure 8 (e)), one of the mosaic square graphics ( Figure 8 (f)), two of the mosaic square graphics (Fig. 8 (g)), a hexagonal close-packed pattern of fully connected n-regions (Fig. 8 (h)), and a hexagonal close-packed pattern of fully connected p-regions (Fig. 8 (i)).
  • the above-mentioned high dielectric constant material is not limited to a single material. It can even be a composite material.
  • the semiconductor is Si
  • it is between the high dielectric constant material may have a thin layer 40 spaced Si ⁇ 2, as shown in FIG.
  • the shaded area in the figure represents the SiO 2 layer 40.
  • the dielectric constant is small, as long as the 310 2 layer 40 is thin enough, it does not prevent the flux lines of the semiconductor S from entering the high-dielectric constant HK, or the flux lines from the high-dielectric constant medium. HK goes into semiconductor S.
  • FIG. 10 is one example of an embodiment for manufacturing a VDMOST by using the present invention.
  • a silicon wafer with an n + substrate 41 having an n-type epitaxial layer 42 is grooved by an anisotropic etching method to obtain the situation shown in FIG. 10 (a).
  • This trough has a side wall and a trough bottom.
  • the trench is then filled with a high dielectric constant material as shown in Fig. 10 (b).
  • a p + source substrate region 29 and an n + source region 30 are formed in the n region 27 through diffusion or ion implantation.
  • make the metal electrode to get the VDMOST structure as shown in Figure 10 (c).
  • FIG. 11 shows another n-VDMOST constructed using the present invention. It is characterized in that the high-dielectric constant material does not directly contact the n + drain region 28, but contacts through an n region 45. Due to the existence of this n- region 45, the resistance of VDMOST near the n + drain region 28 will be further reduced when it is turned on. Although a reverse voltage is applied to the drain D and the source S, the graph There are also small voltages in areas 44 and 45, but the withstand voltage of the device mainly depends on area 43, so we use n area 45 and n + drain area 28 as the contact layer.
  • FIG. 12 shows a schematic diagram of a cell of n-VDMOST using the structure of FIG. 5 (d) of the present invention as a pressure-resistant layer.
  • FIG. 13 shows a schematic diagram of a cell of another n-VDMOST similar to FIG. 12 constructed using the present invention.
  • the difference from FIG. 12 is that the p-region 37 is not directly connected to the lower n + drain region 28, but is indirectly connected to the lower n + drain region 28 through a thin dielectric layer HK38.
  • the dielectric layer connecting the p region 37 and the n + drain region 28 may not be a material with a high dielectric constant, but a thin material with a low dielectric constant.
  • FIG. 14 shows an IGBT constructed using the present invention.
  • the main difference from the VDMOST of FIG. 12 is that the contact layer is not an n + region but a p + region 36.
  • FIG. 15 shows an IGBT with a buffer layer (region 46) constructed using the present invention.
  • the main difference from FIG. 14 is that in the contact layer, in addition to the p + substrate 36, there is also an n + buffer layer 46 on the p + substrate 36.
  • n-type can be regarded as a material of the first conductivity type
  • p-type can be regarded as a material of the second conductivity type.
  • the n-type and p-type of each embodiment can be Reverse without affecting the content of the present invention.
  • multiple changes and multiple devices can be made under the guidance of the thought of the present invention.
  • the invention does not have the problem that the breakdown voltage of COOLMOST decreases under a large current.
  • the charge of the carrier itself does not affect the charge balance.
  • the space charge density in the n-region will decrease, which will increase the breakdown voltage.
  • the present invention also does not have the problem of depletion of the n-region caused by the built-in voltage of the p-region and the n-region or the additional voltage when the current passes, as in the MOST made of the CB structure, so the on-resistance does not follow the drain
  • the invention is not only easy to manufacture, low in device cost, but also long in life and high in work efficiency.

Description

一种半导体器件 发明领域
本发明涉及一种半导体器件， 特别是半导体功率器件的耐压层。 背景技术
众所周知， 在通常的功率器件中， 加于 n+区和 p+区间的反向电压是由一个掺杂较轻 而较厚的半导体层来承受的， 以下称此层为耐压层 (Voltage Sustaining Layer)„对于高压功 率器件， 导通电阻 。,, (或导通压降)也主要由耐压层来决定。 此层掺杂愈轻， 或厚度愈大， 或两者都是， 则击穿电压愈高， 但导通电阻 (或导通压降)也愈大。 在许多功率器件中， 最 重要的问题之一是既要有高的击穿电压又要有低的导通电阻。这两者之间的关系成为制造 高性能功率器件的障碍。更有甚者，上述 是指耐压层中的导通区域的单位面积的电阻， 而实际上耐压层中总有些区域不参加导电。 例如，垂直型 (纵向型) MOSFET 的源衬底区之 下的区域， 双极型晶体管基区接触层下的区域， 都是不参加导电的区域。
本发明人的中国发明专利 ZL91101845.X及美国发明专利 5,216,275 解决了上述问 题。 其解决方法是在 p+区和 n+区间用一个复合缓冲层（Composite Buffer Layer, 或简称 CB层)来耐压。 在 CB层中含有两种导电类型相反的区域。 这两种区域从平行于 CB层与 n+层 (或 p+层)界面的任一剖面来讲， 都是相间排列的。 而在此之前所用的耐压层都是单一 导电类型的半导体。 在该发明中还公布了用这种耐压层构成的 MOST, 单位面积的导通 电阻 R。„正比于击穿电压 的 1.3次方。这代表对通常耐压层关系的一个突破，而 MOST 其它的电性能也很好。 - 在过去几年中， 半导体功率器件的工业界中发生了重大变化。 利用超结 (Super Junction)器件的结构 (即 CB层结构)的 MOST已能提供高电压及大电流。
图 1(a)和图 1 (b)代表一个超结功率器件 1的制造方法。 其过程是先用一个衬底 2的 半导体片生长第一外延层 3。在该图中衬底 2是一个重掺杂的 n+层， 第一外延层 3是轻掺 杂 n层， 在这个层中离子注入一层 p型区 4。 一般而言， 每 50到 100伏的耐压需要一个 外延层。 因此， 对一个 600V的晶体管， 要依次再做图 1 (a)中 5， 7， 9， 11及 13的 n型 外延层， 每次外延之后要做图 1(a)中的 6， 8， 10， 12及 14的 p型离子注入层。
形成的 p型离子注入层 4， 6， 8， 10， 12与 14经过扩散后形成了图 1(b)中的 p区 16， 无离子注入影响的区域是 n区 15。 这就形成了相间排列的 p区与 n区。 然后再做器 件层或称器件特征层 17。 器件特征层 17中含有离子注入形成的 n+源区 18 , 氧化层 19及 其上的金属栅或多晶硅栅 20。 在两个 n+源区 18之间还有一个 p+区 21， 其下还有深结的 p+区 22， 深 p+区 22与 p+区 21相联接。
显然， 上述的制造方法用了多次外延， 很昂贵。 CB层结构利用了电荷补偿原理， 其 中 p区与 n区的掺杂要精确控制， 这也使得制造难度增加， 器件的成本增高。
含有 CB层结构的 MOST另一个缺点是当导通电流很大时， 载流子本身的电荷会影 响电荷平衡， 造成击穿电压随电流增加而下降的二次击穿现象， 使安全工作区 (SOA)不够 理想。
含有 CB层结构的 MOST的再一个缺点是由于 p区与 n区之间存在两个电压： 一个 是内建电压，另一个是当一区导通时在该区内由导通电阻产生的附加电压。这两个电压使 两区之间存在耗尽区， 从而使导通区的有效截面的面积减小。换言之， 导通电阻随电流的 增加而增加。 发明内容
本发明的目的在于提供一种半导体器件， 其包括一种新结构的耐压层， 称为半导体
(Semiconductor)与高介电系数的介质 (High K)构成的复合耐压层， 简称高介半耐压层或高 介半层 (High K and Semiconductor Layer, 或简称 HKS- Layer)。 它可以避免上述缺点，.而 同时使导通电阻 ?。,,与击穿电压 B的关系得到改进， 而且具有很高的开关速度。
本发明提供一种半导体器件， 包括在导电的接触层和导电的器件特征层之间的 耐压层， 所述耐压层包括至少一个半导体区和至少一个具有高介电系数的介质区， 所 述半导体区和介质区均与所述器件特征层和接触层所形成的界面相接触，所述半导体 区与介质区相互接触， 其所形成的接触面垂直或近似垂直于所述接触层和器件特征 层。
所述半导体区和介质区均与器件特征层和接触层所形成的界面相接触， 其可以 是直接接触， 也可以是通过一个薄的半导体区或一个薄的介质区间接接触。
所述半导体区与介质区相互接触， 其可以是直接接触， 也可以是通过一个薄的 具有低介电系数的介质区间接接触。 '
可以由至少一个所述半导体区和至少一个所述介质区构成了一个元胞， 许多所 述的元胞紧密排列构成了所述耐压层。
所述半导体区可由第一种导电类型的半导体构成， 器件特征层是含有重惨杂的 第二种导电类型的半导体区， 而接触层是重掺杂的第一种导电类型的半导体。
所述半导体区可由第一种导电类型的半导体构成， 接触层是在一个重掺杂的第 一种导电类型的半导体之上有一个薄的第一种导电类型的半导体构成，所述薄的第一 种导电类型的半导体与耐压层直接接触。
所述半导体区可以既含有第一种导电类型的半导体部分， 也含有第二种导电类 型的半导体部分，其中第一种导电类型的半导体及第二种导电类型的半导体均与器件 特征层及接触层直接接触， 而器件特征层是含有重掺杂的第二种导电类型的半导体 区。
所述半导体区可以既含有第一种导电类型的半导体部分， 也含有第二种导电类 型的半导体部分， 其中第一种导电类型的半导体与器件特征层及接触层均直接接触， 第二种导电类型的半导体与器件特征层直接接触，且通过一个薄的高介电系数的介质 层或一个薄的低介电系数的介质层与接触层间接接触，而器件特征层是含有重惨杂的 第二种导电类型的半导体区。
所述两种不同导电类型的半导体之间可具有高介电系数的介质区。
所述接触层可以是重掺杂的第二种导电类型的半导体。
所述接触层可以在一个重惨杂的第二种导电类型的半导体层上有一个薄的第一 种导电类型的半导体层， 所述薄的第一种导电类型的半导体层与耐压层直接接触。 附图概述
图 1(a): 制造 C00LM0ST的现有技术的方法示意图， 表示多次外延及离子注入; 图 1(b): 制造 COOLMOST的现有技术的方法示意图， 表示经过扩散后形成一个周 围是 n区的 p区；
图 2(a): 耐压层的说明 (W距离内是耐压层)， 表示 pin二极管；
图 2(b): 耐压层的说明 (W距离内是耐压层)， 表示 p+ii— n+二极管；
图 2(c)： 耐压层的说明 (W距离内是耐压层)， 表示 n-RMOST；
图 2(d): 耐压层的说明 (W距离内是耐压层)， 表示 n-VDMOST;
图 2(e): 耐压层的说明 (W距离内是耐压层)， 表示 Schottky二极管；
图 2(f): 耐压层的说明 (W距离内是耐压层)， 表示接近穿通的 IGBT;
图 3(a): 通常 RMOST及其电场分布， 表示 RMOST的结构示意图；
图 3(b): 通常 RMOST及其电场分布， 表示在偏压临近击穿电压时的电场分 ； 图 3(c): 通常 RMOST及其电场分布， 表示电场的一个不变分量；
图 3(d): 通常 RMOST及其电场分布， 表示电场的一个随距离变化的分量； 图 4(a): CB-RMOST及其电场分布， 表示 CB- RMOST的结构示意图；
图 4(b): CB-RMOST及其电场分布， 表示在偏压临近击穿电压时的电场分布； 图 4(c): CB-RMOST及其电场分布， 表示电场的一个不变分量；
图 4(d): CB-RMOST及其电场分布， 表示电场的一个随距离变化的分量； 图 5(a): 半导体与高介电系数材料构成的耐压层 (HKS 耐压层)的示意图， 表示高介 电系数 料与 n型半导体构成的耐压层；
图 5(b): 半导体与高介电系数材料构成的耐压层 (HKS 耐压层)的示意图， 表示高介 电系数材料与 p型半导体构成的耐压层；
图 5(c): 半导体与高介电系数材料构成的耐压层 (HKS 耐压层)的示意图， 表示高介 电系数材料与 n型半导体区及 p型半导体区构成的耐压层， 高介电系数材料的周围是 p 型半导体区；
图 5(d): 半导体与高介电系数材料构成的耐压层 (HKS 耐压层)的示意图， 表示高介 电系数材料与 n型半导体区及 p型半导体区构成的耐压层，高介电系数材料的周围一边是 p型半导体区， 一边是 n型半导体区；
图 6(a): 沿图 5中 ΙΙ - Ι 剖面的 HKS耐压层的各种不同结构示意图， 表示叉指条 图形；
图 6(b): 沿图 5中 II - II ' 剖面的 HKS耐压层的各种不同结构示意图， 表示 S区全 连通的方块形元胞图形；
图 6(c): 沿图 5中 II - II ' 剖面的 HKS耐压层的各种不同结构示意图， 表示 HK区 全连通的方块形元胞图形；
图 6(d): 沿图 5中 II - II ' 剖面的 HKS耐压层的各种不同结构示意图， 表示 S区全 连通的矩形元胞图形；
图 6(e): 沿图 5中 II - II 1 剖面的 HKS耐压层的各种不同结构示意图， 表示 HK区 全连通的矩形元胞图形；
图 6(f): 沿图 5中 II - II ' 剖面的 HKS耐压层的各种不同结构示意图， 表示镶嵌方 块图形；
图 6(g): 沿图 5中 II - Ι 剖面的 HKS耐压层的各种不同结构示意图， 表示 S区全 连通的六角形密堆积图形； 图 6(h): 沿图 5中 Π- Ι 剖面的 HKS耐压层的各种不同结构示意图， 表示 HK区 全连通的六角形密堆积图形。
图 7(a): 用叉指条 HKS耐压层的 n- RMOS的示意图， 表示结构示意图；
图 7(b): 用叉指条 HKS耐压层的 n- RMOS的示意图， 表示开启特性；
图 7(c): 用叉指条 HKS耐压层的 n-RMOS的示意图， 表示关断特性；
图 8(a): 沿图 5(d)中 III - ΠΓ 剖面的含有 p区及 n区的 HKS耐压层的各种不同结构 示意图， 表示叉指条图形；
图 8(b): 沿图 5(d)中 III - ΠΓ 剖面的含有 p区及 n区的 HKS耐压层的各种不同结构 示意图， 表示 n区全连通的方块形元胞图形；
图 8(c): 沿图 5(d)中 III - ΙΙΓ 剖面的含有 p区及 n区的 HKS耐压层的各种不同结构 示意图， 表示 p区全连通的方块形元胞图形；
图 8(d): 沿图 5(d)中 ΙΙΙ-ΙΙΓ 剖面的含有 p区及 n区的 HKS耐压层的各种不同结构 示意图， 表示 n区全连通的矩形元胞图形；
图 8(e): 沿图 5(d)中 III- ΠΓ 剖面的含有 p区及 n区的 HKS耐压层的各种不同结构 示意图， 表示 p区全连通的矩形元胞图形；
图 8(f): 沿图 5(d)中 III - ΙΙΓ 剖面的含有 p区及 n区的 HKS耐压层的各种不同结构 示意图， 表示镶嵌方块图形之一；
图 8(g): 沿图 5(d)中 III- ΠΓ 剖面的含有 p区及 n区的 HKS耐压层的各种不同结构 示意图， 表示镶嵌方块图形之二；
图 8(h): 沿图 5(d)中 ΙΠ - ΠΓ 剖面的含有 p区及 n区的 HKS耐压层的各种不同结构 示意图， 表示 n区全连通的六角形密堆积图形；
图 8(i): 沿图 5(d)中 III- III' 剖面的含有 p区及 n区的 HKS耐压层的各种不同结构 示意图， 表示 p区全连通的六角形密堆积图形；
图 9: 高介电系数材料与半导体材料之间有一个薄的低介电系数的 Si02层的 HKS耐 压层示意图；
图 10(a): 利用 HKS耐压层结构的 VDMOST的制造过程， 表示 n+衬底上有 n外延 层的硅片上刻了深度接近于外延层厚度的槽；
图 10(b):利用 HKS耐压层结构的 VDMOST的制造过程， 表示在槽中填满了 HK的 介电材料；
图 10(c):利用 HKS耐压层结构的 VDMOST的制造过程， 表示在 n型区的表面做器 件的有源区；
图 11：一个高介电系数材料经过一个轻惨杂 n区再和 n+漏区接触构成的 n- VDMOST 的示意图。
图 12: —个利用图 5(d)的 HKS耐压层构成的 n-VDMOST的示意图。
图 13： 一个利用图 5(d)的 HKS 耐压层但 p 区不与 n+漏区直接接触而构成的 n - VDMOST的示意图。
图 14: 一个利用图 5(d)的 HKS耐压层而构成 IGBT的示意图。
图 15: —个利用图 5(d)的 HKS耐压层但具有缓冲层的 IGBT 的示意图。 本发明的最佳实施方式 在半导体功率器件中， 一般都有一个在 p+区 (或相当于 p+区)与 n+区 (或相当于 11+区) 之间的耐压层。 图 2(a)是一个 pin二极管的示意图， 它是由 p+区 24， n+区 25和 i区 23构 成， 其中 i区 23是耐压层。 这里 A是二极管的阳极， K是二极管的阴极。 图 2(b)是一个 p+n— n+二极管的示意图， 其中 n—区 26在反偏压加到击穿电压时耗尽层厚度如为 则厚 度为 W的区域是耐压层。 图 2(c)是一个电子导电的 n-RMOST的示意图。 这里 S是源电 极， G是栅电极， D是漏电极。 尽管在平面 31之上， 在栅氧化层 32之处并不是 p+区， 但因为实际使用时在栅氧化层 32之下的平面 31上的电位和 p+源衬底区 29与 n区 27交 界面的电位相差不多， 其差别比起器件的击穿电压 ^小得多， 因此可以近似认为是一个 等位面。 在下面讨论耐压时， 把平面 31之上的区域称为器件特征层 33。 器件特征层 33 对电场分布的作用可当作 p+层。 图 2(d)是一个 VDMOST的示意图。 这里平面 31可近似 当作与 p+源衬底区 29等电位。 因此本发明中将以平面 31以下到 n区 27与 n+漏区 28的 界面之间的区域作为耐压层 34。而以平面 31之上的区域作为器件特征层 33。这里假设上 述两种 MOST在加反偏电压而未达到击穿电压 νβ时耗尽区的边缘已经到了 η型区 27与 η+漏区 28的界面。 因此耐压层的厚度为图中所示的 ， 这种假设符合通常的实际情形。
在上述的情形中， 耐压层的两边是 ρ+区与 η+(或 η)区的半导体。 实际上， 器件特征 层可以不是 ρ+区，而是金属，它和耐压层的 η区形成 Schottlcy接触。图 2(e)示出一个 Schottky 二极管的示意图。 其中用金属层 35代替了上述情形中的 p+层。 同样的理由， 耐压层下面 也可以不是和 n+(或 11)区相接触， 而是和金属相接触， 形成 Schottky接触。 因此， 我们称 耐压层下面的接触的区为接触层。 图 2(f)示出一个接近穿通的 IGBT的情形。 耐压层下面 接触的可以认为是 p+层 36。
为了说明本发明的原理， 这里先简述传统功率 MOS器件击穿电压 ）^与导通电阻 R。„关系不理想的原因。 图 3(a)是一个 RM0ST的示意图。 它是 ώ η区 27， η+源区 30， ρ+ 源衬底区 29和 η+漏区 28构成。 这里 G是栅电极， S是源电极， D是漏电极。 其中耐压 层是图中所示厚度为 的耗尽区域 34。 图 3(b)示出 RMSOT中偏压临近击穿电压时的电 场分布， E代表在坐标轴 y方向上的电场。 根据 Poisson方程， 电场的梯度是 N / 。 其 中7\¾代表 n区的施主浓度。 当最大电场达到击穿临界电场 时， 就发生雪崩击穿。 击 穿临界电场 Ee„7的数值约在 3 · 105V/cm左右， E和 j;之间阴影区的面积代表电场对路径 的积分， 即击穿电压 VB。 显然， 要击穿电压 高， 必须满足以下两个条件： （1)电场的 梯度小， g卩 ND小； （2)耗尽区宽度 大。但是 ^小， 代表耐压层在导通时载流子浓度小， 电阻率高。耗尽层宽度 大， 代表导通路径长。 由于导通电阻正比于电阻率及路径长度， 这会使得导通电阻大大增加。 对于功率 MOST, 最佳的设计是在 n区 27与 n+漏区 28临 近处电场为 ECJ3， 则击穿电压为 2Ee,it · WI3。
上述电场分布可以认为是两个电场的叠加。一个是外加电压 ^在一个 pin二极管上 引起的电场， 如图 3(c)所示。 电场的值等于 2 ,.Λ/3且不随距离变化。 另一个是从底部的 电场值为 到顶部的电场值为 +Em¾/3的线性变化的电场， 如图 3(d)所示， 它的梯度 为 qNDl es, 其峰值为 -(7N0W/2 ss R+qNDWI2 。 后一个电场是造成导通电阻 R0„随击穿 电压 增大而增大的原因。
本发明人提出的 CB 耐压层结构（中国发明专利 ZL91101845.X 及美国发明专利 5,216,275)解决了上述问题。 以下简要说明 CB结构为何能改进导通电阻 与击穿电压 VB的关系。 图 4(a)是一个 CB-RMOST的示意图。 它的耐压层 34是由 n区 27和 p区 37 交替排列而成的，其厚度为 W。 CB-RMOST在加反偏压而使 n区 27与 p区 37全耗尽时， n区 27中电离施主的正电荷产生的电力线终止于其邻近的 p区 37中电离受主的负电荷上。 因此 n区 27中线 I - I '的电场如图 4(b)的实线所示。 它基本上是不变的， 只是在靠近平 面 31及靠近 n+漏区 28处略有变化。这个电场也可以分解为如图 4(c)与图 4(d)所示的两个 ¾场。 图 4(c)相当于一个 pin二极管的情形， 和图 3(c)—样。 图 4(d)则表示由 n区 27产生 的纵向电场。 这个电场比起同样惨杂浓度下的图 3(d)的电场小得多。 实际上， CB结构中 ND可以很大， 而产生的这个电场仍然小得多。 因为这个由电离施主正电荷产生的纵向电 场不是从耐压层中间开始不断积累而来的， 而是由 n区 27顶部及底部附近的电离施主产 生的电力线分别被位于上面的栅电极 G的负电荷及位于下面的 n+漏区 28负电荷所终止， 而离 n区 27顶部及底部较远处的电离施主的电场均被周围的 p区 37的电离受主所终止。
本发明所提出的耐压层结构是将高介电系数的材料与半导体相间排列， 构成如图 5 所示的情形， 图中的 HK代表高介电系数的材料。
本发明的原理如下。
在图 5(a)中， 如果 HK区 38与 n区 27都很窄， 从大体上说， 相当于一种混合的材 料， 其介电系数不是半导体材料的介电系数 而是比它的值大得多， 但比高介电系数的 材料的介电系数 小的一个值。 粗略地讲， 如混合后当作有介电系数 ， 则当 时， eM » es。 这使得象图 3(d)那样的斜率 ， 在同样惨杂浓度下会变得很小， 成 为 qNDl eM。 用另一句话来说， 就是可以用更大值的 7\¾来得到同样的峰值电场 E„.,7/3。
用本发明的 HKS层作耐压层， 由于 n型区 27耗尽时， 其中电离施主发出的电通量 线， 多数会横向走到邻近的高介电系数的介质 38 中去， 最后通过高介电系数的介质 38 内部走到顶部被 p+区 24内感应出的负电荷吸收。 因此 ,η型层 27中电离施主产生的最大 电场的值会比 qND · /2 小得多。 而在高介电系数的介质 38中， 这些从 n型区 27进来 的电通量线， 类似于使其产生了许多电离施主。 但由于 很大， 它自身所产生的电场较 小。
图 5(c)及图 5(d)是本发明者的中国发明专利 ZL91 101845.X及美国发明专利 5,216,275 的 CB结构中引入了高介电系数 HK的材料。
在图 5(c)中， 当 p型区 37及 n型区 27都耗尽时。 在理想的情形， n区 27的电离施 主正电荷产生的电通量线恰好全部被 p型区 37电离施主所终止。在 n区 27掺杂过重的不 理想情形， 则多余的电通量线可进入高介电系数介质 38内部， 然后流到顶部 p+区 24， 终 止于 p+区 24的感应负电荷上。在 n区 27惨杂过轻的不理想情形， 则从底部 n+区 25有发 出的电通量线， 经高介电系数的介质内部再流向 p区 37, 终止于多余的电离受主负电荷 上。
在图 5(d)中， 当 n型区 27及 p型区 37全耗尽时。 在理想的情形， n区 27电离施主 正电荷产生的电通量线经过高介电系数的介质再流向 p区 37， 被那里的电离受主负电荷 所终止。 在 n区 27掺杂过重的不理想情形， 其多余的电通量线可经过高介电系数的介质 38再流向顶部 p+区 24， 终止于 p+区 24的感应负电荷上。在 n区 27惨杂过轻的不理想情 形， 则从底部 n+区 25有发出的电通量线， 经过高介电系数的介质 38内部再流向 p区 37， 终止于多余的电离受主电荷之上。
综上所述， 本发明的耐压层中的半导体区可以是 n型区也可以是 p型区， 也可以是 两种都有。 因此在下面不需要特别指出时， 将统一用半导体区 S来表示。 在 HKS层中， 高介电系数的材料与半导体区的安排有许多结构图形。图 6示出了一 些沿如图 5(a)的 Π - II '剖面的许多高介电系数的材料与半导体区的安排方法。 图中由虚线 划分出许多元胞。 这些图形包括叉指条图形 (图 6(a)), 半导体区全连通的方块形元胞图形 (图 6(b))， HK区全连通的方块形元胞图形 (图 6(c)), 半导体区全连通的矩形元胞图形 (图 6(d)), HK区全连通的矩形元胞图形 (图 6(e)), 镶嵌方块图形 (图 6(f))， 半导体区全连通的 六角形密堆积图形 (图 6(g)), HK区全连通的六角形密堆积图形 (图 6(h))。
图 7(a)是一个用 HKS层做 MOST的结构示意图。用一个典型数值计算例子可以说 明它的优越性。 设采用的是叉指条图形， 每个元胞宽为 13.04μΓη， η区 27及 HK区 38各 占一半宽度， HKS层的厚度为 65μη。 Ν区的施主浓度是 2.07 · 1015cm_3，
高介电系数材料的相对介电系数等于 234(比硅的相对介电系数高二十倍）。 用 MEDICI软件做模拟计算， 采用了标准模型， 得到的击穿电压是 750伏， 比导通电阻是 30ιηΩ · cm2。 而同样击穿电压下的传统的 RMOST的比导通电阻是 123mQ · cm2。 图 7(b) 及图 7(c)分别示出在 750伏电源串联电阻 5.75 · 107Ω · μπι下的丌启及关闭的瞬态电流特 性。所用的栅极电压是从 0伏变到 20伏以及从 20伏变到 0伏，可以看到其上升及下降时 间各为 lns， 开启时间不到 2ns, 关断时间不到 80ns。
显然， 这里不存在 COOLMOST在大电流下击穿电压下降的问题， 即在导通时 n区 27的电子电荷破坏电荷'平衡从而使击穿电压下降的问题。 相反， 当 n区电子数增加时， n 区的空间电荷密度会下降， 从而使击穿电压 高。 这使得这种器件有较大的安全工作区， 电流达到 100A/cm2而击穿电压维持不变。
另一个优点是， 这里不存在象 CB结构做的 MOST中那样有 p区与 n区的内建电压 或电流通过时的附加电压引起 n区 27的耗尽问题。 因此导通电阻不会随漏源电压增加而 增大。只是在电压很大时，引起了 11区 27(也称漂移区)中电子速度的饱和，电阻有所增加。
图 8示出在图 5(d)沿 ΙΙΙ-ΙΠ' 剖面的高介电系数的材料与 η型半导体区及 ρ型半导 体区的安排的许多结构示意图。 这些图形包括叉指条图形 (图 8(a))， η区全连通方块形元 胞图形 (图 8(b))，p区全连通方块形元胞图形 (图 8(c; ，n区全连通的矩形元胞图形 (图 8(d)), p区全连通的矩形元胞图形 (图 8(e)), 镶嵌方块图形之一 (图 8(f)), 镶嵌方块图形之二 (图 8(g)), n区全连通的六角形密堆积图形 (图 8(h))， p区全连通的六角形密堆积图形 (图 8(i))。
上述的高介电系数材料， 并不限于一种单一的材料。它甚至可以是一种复合的材料。 例如， 在图 6(a)中， 如果半导体是 Si， 它与高介电系数材料之间可以有一个薄的 Si〇2层 40隔开， 如图 9所示。 图中的阴影区代表 Si02层 40。 尽管 的介电系数很小， 但只 要 3102层40足够薄， 并不妨碍半导体 S的电通量线进入高介电系数的介质 HK中去， 或 电通量线从高介电系数的介质 HK进入半导体 S中去。
图 10是利用本发明制造 VDMOST的实施例子之一。 一块有 n型外延层 42的 n+衬 底 41的硅片用各向异性的腐蚀方法刻槽， 得到如图 10(a)所示的情形。此槽具有边墙和槽 底。再用高介电系数的材料填充槽， 使其如图 10(b)所示那样。然后在 n区 27内经过扩散 或离子注入形成 p+源衬底区 29 及 n+源区 30。 再做金属电极，得到如图 10(c)所示的 VDMOST结构。
图 11示出利用本发明构成的另一种 n-VDMOST。 它的特点是高介电系数的材料并 不与 n+漏区 28直接接触，而是经过一个 n区 45來接触。由于这个 n区 45的存在， VDMOST 在导通时靠近 n+漏区 28的电阻会进一歩减小。尽管在漏极 D与源极 S加反向电压时， 图 中 44区及 45区也有小部分电压， 但器件的耐压主要靠 43区， 因此我们把 n区 45及 n+ 漏区 28作为接触层。
图 12示出利用本发明的图 5(d)结构作耐压层的 n-VDMOST的一个元胞的示意图。 图 13示出利用本发明构成的与图 12相仿的另一个 n-VDMOST的一个元胞的示意 图。 这里， 与图 12的区别在于， p区 37并不与下部 n+漏区 28直接相联， 而是通过一个 薄的介质层 HK38与下部 n+漏区 28间接相联。 当然， 这个联接 p区 37与 n+漏区 28的介 质层也可以不是高介电系数的材料， 而是薄的低介电系数的材料。
图 14示出利用本发明所构成的一种 IGBT。它与图 12的 VDMOST的主要区别是接 触层不是 n+区而是一个 p+区 36。
图 15示出利用本发明构成的一种带有缓冲层 (46区)的 IGBT。它与图 14的主要区别 是在接触层内， 除有 p+的衬底 36外， 还有在 p+衬底 36上的一个 n+缓冲层 46。
上面对利用本发明作了许多实例说明。其所述 n型可看作是第一种导电类型的材料， 而 p型可看作是第二种导电类型的材料， 显然， 按照本发明的原理， 各实施例的 n型与 p 型可以对调而不影响本发明的内容。对于本领域的普通技术人员而言，还可以在本发明的 思想指导下， 作出多种变化及多种器件。 工业实用性
本发明不存在 COOLMOST在大电流下击穿电压下降的问题， 相反， 当导通电流很 大时， 载流子本身的电荷不会影响电荷平衡。 当 n区电子数增加时， n区的空间电荷密度 会下降， 从而使击穿电压增高。 这使得本发明有较大的安全工作区， 电流达到 l OOA/cm2 而击穿电压维持不变。
另夕卜， 本发明也不存在象 CB结构做的 MOST中那样有 p区与 n区的内建电压或电 流通过时的附加电压引起 n区的耗尽问题， 因此导通电阻不会随漏源电压增加而增大。只 是在电压很大时， 引起了 n区 (也称漂移区)中电子速度的饱和， 电阻有所增加。 导通电阻 R。„与击穿电压 的关系得到改进， 而且具有很高的开关速度。
总之， 本发明不仅制造容易， 器件成本低， 而且寿命长， 工作效率高。

Claims

1、 一种半导体器件， 包括在导电的接触层和导电的器件特征层之间的耐压层， 其特征在于所述耐压层包括至少一个半导体区和至少一个具有高介 ¾系数的介质区， 所述半导体区和介质区均与所述器件特征层和接触层所形成的界面相接触，所述半导 体区与介质区相互接触，其所形成的接触面垂直或近似垂直于所述接触层和器件特征 层。
2、 如权利要求 1所述的一种半导体器件， 其特征在于所述半导体区和介质区均 与器件特征层和接触层所形成的界面相接触， 此接触可以是直接接触， 也可以是通过 一个薄的半导体区或一个薄的介权质区间接接触。
3、 如权利要求 1所述的一种半导体器件， 其特征在于所述半导体区与介质区相 互接触， 此接触可以是直接接触， 也可以是通过一个薄的具有低介电系数的介质区间 接接触。
4、 如权利要求 1所述的一种半导体器件， 其特征在于至少一个所述半导体区和 至少一个所述介质区构成了一个元胞， 许多所述的元胞紧密排列构成了所述耐压层。
5、 如权利要求 1所述的半导体器件， 其特征在求于所述半导体区是由第一种导电 类型的半导体构成， 器件特征层是含有重掺杂的第二种导电类型的半导体区构成， 而 接触层是重掺杂的第一种导电类型的半导体构成。
6、 如权利要求 1所述的半导体器件， 其特征在于所述半导体区是由第一种导电 类型的半导体构成，接触层是在一个重掺杂的第一种导电类型的半导体之上有一个薄 的第一种导电类型的半导体构成，所述薄的第一种导电类型的半导体与耐压层直接接 触。
7、 如权利要求 1所述的半导体器件， 其特征在于所述半导体区既含有第一种导 电类型的半导体部分， 也含有第二种导电类型的半导体部分， ^其中第一种导电类型的 半导体及第二种导电类型的半导体均与器件特征层及接触层直接接触，而器件特征层 是含有重掺杂的第二种导电类型的半导体区。
8、 如权利要求 1所述的半导体器件， 其特征在于所述半导体区既含有第一种导 电类型的半导体部分， 也含有第二种导电类型的半导体部分， 其中第一种导电类型的 半导体与器件特征层及接触层均直接接触，第二种导电类型的半导体与器件特征层直 接接触，且通过一个薄的高介电系数的介， 14 一个薄的低介电系数的介质层与接触 层间接接触， 而器件特征层是含有重掺杂 二种导电类型的半导体区。
9、 如权利要求 7或 8所述的半导体器件， 其特征在于所述两种不同导电类型的 半导体之间是具有高介电系数的介质区。
10、 如权利要求 1 所述的半导体器件， 其特征在于所述接触层是重掺杂的第二 种导电类型的半导体。 '
11、 如权利要求 1 所述的半导体器件， 其特征在于所述接触层是在一个重惨杂 的第二种导电类型的半导体层上有一个薄的第一种导电类型的半导体层，所述薄的第 一种导电类型的半导体层与耐压层直接接触。
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