Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
  • H01L25/0657—Stacked arrangements of devices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
  • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
  • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
  • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
  • H01L2225/06503—Stacked arrangements of devices
  • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to a three-dimensional semiconductor circuit arrangement with superposed, vertically electrically connected chips and in particular the electrical contacting of at least one electronic component of an upper chip layer with at least one electronic component of an underlying chip layer.
• chips are increasingly arranged one above the other and connected to one another in a vertically electrically conductive manner.
• the interchip connections are short and low in resistance so that the signal transmission speed is high.
• Each semiconductor circuit layer or each chip layer of the three-dimensional semiconductor circuit arrangement comprises a substrate layer as the lower layer and thereon an upper layer comprising layer sequences of metallization layers and dielectric intermediate layers including active electronic components, conductor tracks and contacts, via which the active elements with external connections or with contacts one below or chip layer of the three-dimensional IC arranged above it can be electrically conductively connected.
• an upper chip is electrically conductively connected to an underlying chip by means of vertical connection connections, in that a metal pin protruding from the underside of the upper chip through an opening in a planarization layer of the lower chip onto a contact surface of the lower chip located in the opening Chips is put on.
• the contact surface of the lower chip is made of an easily fusible material, for example Auln, and by pressing the upper chip and heating the contact surface permanent contact is made between the metal pin of the upper chip and the contact surface of the lower chip.
• the contact area of the lower chip and the overlying opening in the planarization layer must be selected to be large enough so that the metal pin of the upper chip always hits the contact area of the lower chip.
• DE 19202121 C1 describes a similar vertical chip connection between a contact area of a lower chip and an active component of the upper chip.
• an upper chip is first firmly fixed on the lower chip by means of an adhesive layer after the adjacent surface of the lower chip has been made absolutely flat by means of a passivation layer.
• the upper chip has a vertical through opening in the region of the contact area of the lower chip, which opening was created either before or after the connection of the two chips in the upper chip.
• this through-hole is first covered with a silicon oxide layer, the passivation layer of the underlying chip is then etched away in the area of the through-hole up to the contact area of the lower chip, and the through-hole is then filled with electrically conductive material in order to create a vertical, electrically conductive connection between a construction element of the upper chip and the contact surface of the lower chip. It is also important in this method that the contact area of the lower chip is large so that the through-hole in any case comes to lie above the contact area of the chip underneath in spite of any adjustment inaccuracies when stacking the chips one above the other.
• the aforementioned three-dimensional ICs therefore have the disadvantage that the contact surfaces for vertical interchip contacting must be comparatively large, for example 20 ⁇ m ⁇ 20 ⁇ m, because of the adjustment inaccuracies of, for example, + 10 ⁇ m when stacking the chips, so that contacting is ensured in any case is. Due to the small thickness of the stacked chips of less than 20 ⁇ m, the large interchip contact areas cause undesired crosstalk between the metallization of the various chips and the interchip contact area. In addition, because of the large interchip contact areas, very large and powerful drivers with a correspondingly high power consumption are required, which runs counter to the basic goals of chip design. Finally, large interchip contact areas act as comparatively powerful area radiators with electromagnetic radiation characteristics, so that the information transmitted via the interchip contact areas is comparatively easy to detect, which is critical when transmitting security-relevant signals, for example in chip cards.
• the crosstalk problem also requires very careful chip design and experimentation to ensure that the functional components of the chips are not affected by crosstalk of the signals.
• the interchip contact area of, for example, 20 ⁇ m ⁇ 20 ⁇ m in size is subdivided into individual contact surface areas, the respective size of which preferably corresponds approximately to the size of the contact element of the overlying chip or is slightly larger.
• the contact element of the upper chip layer is designed as a metal pin in accordance with the teaching of DE 4314907 Cl and has a diameter of, for example, 1 ⁇ m
• the interchip contact area of the underlying chip layer is preferably at a distance of 1 ⁇ m ⁇ 1 ⁇ m in contact area areas formed between the contact surface areas of, for example, 0.5 ⁇ m.
• the contact element of the upper chip layer thus contacts at least one contact surface area and a maximum of four contacts regardless of any adjustment inaccuracies. Tactile areas of the contact area of the lower chip layer.
• a suitable electronic control for example by means of selection transistors, only those contact surface areas which are actually contacted by the contact element of the upper chip layer are then switched "active". The remaining contact surface areas are "inactive". There is no potential at them, so that they do not emit radiation. Because of the smaller effective contact area that is formed by the active contact area areas, the interchip connection requires less power overall, so that additional powerful drivers can be used. The crosstalk behavior also improved significantly.
• each interchip contact area of the lower chip layer would be dimensioned with, for example, 20 ⁇ m ⁇ 20 ⁇ m, in order to ensure inaccuracies in any case.
• the overall contact area is reduced to a size of somewhat more than 8 ⁇ m ⁇ 8 ⁇ m (four Contact surface areas per contact element) plus a surrounding tolerance range to compensate for adjustment inaccuracies of 10 ⁇ m width, i.e. a total of just over 28 ⁇ m x 28 ⁇ m total contact area.
• the risk of crosstalk on metallizations of the adjacent chips is reduced to a smaller area.
• FIG. 1 shows a detail from a three-dimensional IC comprising two chip layers with interchip contact surface areas according to the invention
• FIG. 4 shows a contact area array according to the present invention.
• the lower chip layer and the upper chip layer each comprise a substrate layer 1 or I 1 , an overlying layer 2 or 2 1 with metallization layers, dielectric intermediate layers and active elements 8 and a passivation layer 3 or 3 'with which the contact surfaces 15 or 6 of the upper layers 2 or 2 ' siviert and the surfaces of the individual chip layers are flat.
• This electrically conductive material serves as an electrically conductive connecting element 5 between the contact surface 6 of the upper chip layer and the contact surface 15 of the lower chip layer.
• the connecting element 5 is surrounded in the through opening 16 by a spacer layer 7 made of silicon oxide and is covered with a further passivation layer 4 1 over the passivation layer 3 1 .
• the contact area 15 is formed by a plurality of small contact area areas 9. As can be seen in FIG. 1, the electrically conductive connecting element 5 only contacts individual contact surface areas 9 of the contact surface 15. Only these contact surface regions 9 that have actually been contacted are activated so that the non-contacted contact surface areas 9 have no connection to the connecting element 5.
• FIG. 2 This is shown schematically in FIG. 2.
• the electrically conductive connecting element 5 is dimensioned so that it contacts a maximum of two adjacent contact surface areas 9. This ensures that at least one contact area 9 and, with a suitable two-dimensional array arrangement of the contact areas 9, a maximum of four contact areas 9 are contacted.
• the "contacting" of the actually contacted contact surface areas 9 can be carried out by means of a simple control logic, for example by means of selection transistors.
• the selection logic circuit can be integrated in the drivers of the interchip connections and / or lie under the contact area regions 9. The latter is shown in FIG. 1, where selection control devices 10 lie below the contact surface areas 9 and only the electrical connection 11 that is contacted by the electrically conductive connecting element 5 is switched to “active”.
• Suitable electronic switches are known in general and in a wide variety of different designs and are described, for example, in US Pat. No. 5,424,589, in particular in FIGS. 6a to 6c with the associated description column 17, line 27 to column 18, line 14. Reference is hereby made to the disclosure of US 5,424,589.
• the selection circuit can advantageously be expanded in order to test the contacting of the interchip connections and to carry out a reliability test.
• a more comfortable selection circuit can not only connect or block individual contact area regions 9 to form a conductor track 14.
• an optional connection to one of several conductor tracks 14 can be switched (for example by means of parallel, independently controllable switches).
• Such an arrangement is particularly advantageous for generic semiconductor circuit arrangements with many interchip connections because, with the same assembly tolerance, adjacent contact surfaces 15 which can be connected to individual connecting elements 5 can overlap and thus a lower total contact surface requirement is achieved. In such a case, the actual physical connections of contact surfaces 9 and connecting elements 5 determined after installation by testing and then set the selection circuit.
• FIG. 3 shows a contact area array 20 on the surface of a layer 2 of a lower chip layer.
• Each contact surface 15 is assigned an image sensor in an overlying chip layer (not shown in FIG. 3) and an evaluation circuit (not shown) in the lower chip layer. Due to possible adjustment inaccuracies when stacking the individual chip layers on one another, the edge lengths a of the individual contact areas 15 are comparatively large and are, for example, 20 ⁇ m ⁇ 20 ⁇ m. As a result, an adjustment inaccuracy of approximately ⁇ 10 ⁇ m is detected.
• the contact surfaces 15 are arranged at a distance d of, for example, 0.5 ⁇ m. The total dimension of the contact surface array 20 is thus
• FIG. 4 shows a contact area array 20 corresponding to the contact area array 20 from FIG. 3 in accordance with a preferred embodiment of the present invention.
• a contact surface 15 is formed by four contact surface regions 9, since it can be assumed that the contacting point 5 ', the dimensions of which roughly correspond to the dimensions of a contact surface region 9, will only meet one or possibly two adjacent contact surface regions 9 in exceptional cases. If a diameter of 1 ⁇ m is again used as the basis for the contacting point 5 1 and if each contact area region 9 is dimensioned accordingly as a 1 ⁇ m ⁇ 1 ⁇ m area, then a contact area 15 formed from four contact area areas 9 has an edge length of twice 1 ⁇ m + 0.5 ⁇ m distance, i.e. a total of 2.5 ⁇ m x 2.5 ⁇ m. An array of four contact surfaces 15 accordingly has the dimensions:
• FIG. 4 shows such a contact area array formed from 4 ⁇ 4 contact areas 15 in the central position of the larger contact area array 20 for ideal conditions when the stacked chip layers are ideally adjusted to one another.
• a / 2 ⁇ 10 ⁇ m
• the larger contact area array 20 is 10 ⁇ m in each direction expanded compared to the central 4x4 array.
• FIG. 3 of 81.5 ⁇ m and FIG. 4 of 29.5 ⁇ m show that the total area of the interchip contact areas can be drastically reduced by means of the present invention.
• no other electronic components are provided in the three-dimensional structure in this area.
• the contact surface areas 9 contacted by a connecting element 5 that is to say a maximum of four contact surface areas 9 each, are then actively switched and electrically conductively connected to the electronic component of the lower chip layer assigned to this connecting element.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Physics & Mathematics (AREA)
• Semiconductor Integrated Circuits (AREA)
• Crystals, And After-Treatments Of Crystals (AREA)
• Bipolar Transistors (AREA)
• Battery Mounting, Suspending (AREA)
• Crushing And Grinding (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (2)

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ID=7689553

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (1)

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• 2001
  • 2001-06-21 DE DE10130864A patent/DE10130864A1/de not_active Withdrawn
• 2002
  • 2002-06-20 WO PCT/EP2002/006861 patent/WO2003001597A2/de not_active Ceased
  • 2002-06-20 DE DE50213010T patent/DE50213010D1/de not_active Expired - Lifetime
  • 2002-06-20 JP JP2003507891A patent/JP4481638B2/ja not_active Expired - Fee Related
  • 2002-06-20 EP EP02745398A patent/EP1402575B1/de not_active Expired - Lifetime
  • 2002-06-20 AT AT02745398T patent/ATE414328T1/de not_active IP Right Cessation
  • 2002-06-20 AU AU2002316990A patent/AU2002316990A1/en not_active Abandoned

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