WO2002078084A2 - Verfahren zur herstellung ferroelektrischer speicherzellen - Google Patents
Verfahren zur herstellung ferroelektrischer speicherzellen Download PDFInfo
- Publication number
- WO2002078084A2 WO2002078084A2 PCT/DE2002/001054 DE0201054W WO02078084A2 WO 2002078084 A2 WO2002078084 A2 WO 2002078084A2 DE 0201054 W DE0201054 W DE 0201054W WO 02078084 A2 WO02078084 A2 WO 02078084A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- adhesive layer
- layer
- oxygen
- temperature
- diffusion barrier
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7687—Thin films associated with contacts of capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
Definitions
- the invention relates to a method for producing ferroelectric memory cells according to the stack principle, wherein between a lower capacitor electrode of a storage capacitor and a conductive plug formed underneath, which is used to electrically connect this capacitor electrode to a transistor electrode of a selection transistor formed in or on a semiconductor wafer, an adhesive layer and an oxygen diffusion barrier are formed over the adhesive layer and, after the ferroelectric has been deposited, are subjected to an RTP step in an oxygen atmosphere.
- transistors are typically produced in or on a semiconductor wafer. An intermediate oxide is then deposited. The ferroelectric capacitor modules are produced on this intermediate oxide. The connection between the ferroelectric capacitor modules and the transistors is achieved by a plug that is located directly below the capacitor module in the stack-cell principle.
- ferroelectric layer of the ferroelectric capacitor module it is necessary to carry out an annealing (ferro anneal) in an oxygen atmosphere at temperatures of up to 800 ° C.
- ferro anneal the plug, which usually consists of polysilicon or tungsten, must be protected against oxidation, otherwise the electrical connection between the lower capacitor electrode and the transistor will be irreversibly interrupted.
- reactions between the electrodes, the ferroelectric and the plug are to be avoided if they affect the functionality of the chip.
- FIG. 1 shows a schematic cross section through a section of a ferroelectric memory cell constructed according to the stack cell principle. Shown is a plug 1 leading through an intermediate oxide layer 7 (TEOS), for example made of polysilicon, an immediately above lower part 2 of an adhesive layer, for example made of TiSi 2 , an overlying upper part 3 of the adhesive layer, for example made of Ti, a lower part 4 of Oxygen diffusion barrier, for example made of Ir and above it a second part 5 of the oxygen diffusion barrier, for example made of IrO 2 . Over this upper Ir0 2 section 5 of the oxygen diffusion barrier is the lower one
- TEOS intermediate oxide layer 7
- Capacitor electrode 6 which consists of Pt, for example.
- RTP Rapid Thermal Processing
- Temperature can be found at which the layer system remains conductive.
- the method according to the invention is characterized in that the following steps are carried out:
- Layer width of the layer system consisting of the adhesive layer and oxygen diffusion barrier, so that the silicidation of the adhesive layer proceeds faster than its oxidation during the RTP step.
- the rate of oxidation of the adhesive layer and from this the diffusion coefficient of oxygen in the material of the adhesive layer, for example titanium is determined as a function of the temperature.
- the rate at which a TiSi-Ir layer is formed from a titanium layer and from it the associated one Diffusion coefficient determined depending on the temperature is determined depending on the temperature. Then, with a given titanium layer thickness, the temperature-dependent diffusion coefficients and the oxidation rates can be used to calculate the optimum temperature required for the TiSi-Ir formation to proceed quickly enough, that is to say faster than the simultaneous formation of the insulating TiSi O areas to maintain the conductivity of the layer system.
- the invention provides a formula with which the optimal temperature range or the optimal temperature for the RTP step can be calculated:
- the left term gives the time until the silicate layer has been silicided and the right term the time until the adhesive layer has completely oxidized , d BARR the layer thickness of the system from the oxygen diffusion barrier and the adhesive layer thereof, k> BARR half layer width,
- Fig. 1 shows a schematic cross section through a
- FIG. 2a and 2b show details of section II from FIG. 1, each of which illustrates a process for a functioning electrical connection (a) and a process (b) which leads to an interruption of the conductive connection by oxidation of the adhesive layer, and
- FIG. 3 which, like FIG. 1, shows a cross section through a section of a ferroelectric memory cell constructed according to the stack cell principle, shows the quantities which are essential for the method according to the invention.
- These sizes are the thickness d BARR of the layer system consisting of adhesive layer 2, 3 and oxygen diffusion barrier 4, 5, b BARR half the width of this layer system, D Sauerst0ff (strongly drawn arrow) the (temperature-dependent) diffusion coefficient of oxygen in the material of the adhesive layer 2, 3 and D silicon (heavily drawn arrow from below) is the (temperature-dependent) diffusion coefficient of silicon, which is decisive for the silicidation of the adhesive layer 2, 3.
- Silicon oxygen the left term indicates the time until the silicification of the adhesive layer and the right term the time until the oxidation of the same.
- D silicon gives the temperature-dependent diffusion coefficient of silicon and D Sauerst ⁇ ff the temperature-dependent diffusion coefficient of oxygen along a certain interface.
- the quotients d / D and b / D are unit times. From that for a certain species in a certain matrix for a certain
- the function of temperature is, and the selected dimensions b and d, the time for silicidation (left term) must be less than the time for oxidation (right term).
- an RTP step (after the top electrode structure) was carried out at 800 ° C. for 15 seconds in oxygen and then the ferro-anneal in 0 2 at a temperature of about 675 ° C. for 15 minutes.
- ferroelectric manufactured according to this manufacturing process was carried out at 800 ° C. for 15 seconds in oxygen and then the ferro-anneal in 0 2 at a temperature of about 675 ° C. for 15 minutes.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002576015A JP2004526320A (ja) | 2001-03-23 | 2002-03-22 | 強誘電性記憶セルの製造方法 |
EP02727262A EP1371093A2 (de) | 2001-03-23 | 2002-03-22 | Verfahren zur herstellung ferroelektrischer speicherzellen |
KR1020037012312A KR100579337B1 (ko) | 2001-03-23 | 2002-03-22 | 강유전성 메모리 셀 제조 방법 |
US10/669,072 US6806097B2 (en) | 2001-03-23 | 2003-09-23 | Method for fabricating ferroelectric memory cells |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10114406A DE10114406A1 (de) | 2001-03-23 | 2001-03-23 | Verfahren zur Herstellung ferroelektrischer Speicherzellen |
DE10114406.7 | 2001-03-23 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/669,072 Continuation US6806097B2 (en) | 2001-03-23 | 2003-09-23 | Method for fabricating ferroelectric memory cells |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002078084A2 true WO2002078084A2 (de) | 2002-10-03 |
WO2002078084A3 WO2002078084A3 (de) | 2003-03-13 |
Family
ID=7678800
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2002/001054 WO2002078084A2 (de) | 2001-03-23 | 2002-03-22 | Verfahren zur herstellung ferroelektrischer speicherzellen |
Country Status (7)
Country | Link |
---|---|
US (1) | US6806097B2 (de) |
EP (1) | EP1371093A2 (de) |
JP (1) | JP2004526320A (de) |
KR (1) | KR100579337B1 (de) |
CN (1) | CN1331215C (de) |
DE (1) | DE10114406A1 (de) |
WO (1) | WO2002078084A2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113421881B (zh) * | 2021-05-26 | 2022-08-19 | 复旦大学 | 通过金属扩散调节铁电存储器表面层有效厚度的方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999028972A1 (en) * | 1997-11-28 | 1999-06-10 | Motorola Inc. | Semiconductor device with ferroelectric capacitor dielectric and method for making |
US5932907A (en) * | 1996-12-24 | 1999-08-03 | International Business Machines Corporation | Method, materials, and structures for noble metal electrode contacts to silicon |
WO2000039842A1 (de) * | 1998-12-23 | 2000-07-06 | Infineon Technologies Ag | Kondensatorelektrodenanordnung |
DE10014315A1 (de) * | 1999-03-26 | 2000-10-05 | Sharp Kk | Halbleiterspeicher und Verfahren zur Herstellung desselben |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5046043A (en) * | 1987-10-08 | 1991-09-03 | National Semiconductor Corporation | Ferroelectric capacitor and memory cell including barrier and isolation layers |
US5434102A (en) * | 1991-02-25 | 1995-07-18 | Symetrix Corporation | Process for fabricating layered superlattice materials and making electronic devices including same |
WO1992019564A1 (en) * | 1991-05-01 | 1992-11-12 | The Regents Of The University Of California | Amorphous ferroelectric materials |
JPH09102591A (ja) * | 1995-07-28 | 1997-04-15 | Toshiba Corp | 半導体装置及びその製造方法 |
DE19640243A1 (de) * | 1996-09-30 | 1998-04-09 | Siemens Ag | Kondensator mit einer Sauerstoff-Barriereschicht und einer ersten Elektrode aus einem Nichtedelmetall |
KR20010013595A (ko) * | 1997-06-09 | 2001-02-26 | 엔, 마이클 그로브 | 개선된 장벽 특성을 나타내는 결정 퍼로브스카이트강유전체 셀을 어닐링하는 방법 |
KR100279297B1 (ko) * | 1998-06-20 | 2001-02-01 | 윤종용 | 반도체 장치 및 그의 제조 방법 |
WO2000049660A1 (en) * | 1999-02-16 | 2000-08-24 | Symetrix Corporation | Iridium oxide diffusion barrier between local interconnect layer and thin film of layered superlattice material |
JP4150154B2 (ja) * | 2000-08-21 | 2008-09-17 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
-
2001
- 2001-03-23 DE DE10114406A patent/DE10114406A1/de not_active Withdrawn
-
2002
- 2002-03-22 KR KR1020037012312A patent/KR100579337B1/ko not_active IP Right Cessation
- 2002-03-22 EP EP02727262A patent/EP1371093A2/de not_active Withdrawn
- 2002-03-22 JP JP2002576015A patent/JP2004526320A/ja active Pending
- 2002-03-22 CN CNB028071182A patent/CN1331215C/zh not_active Expired - Fee Related
- 2002-03-22 WO PCT/DE2002/001054 patent/WO2002078084A2/de active Application Filing
-
2003
- 2003-09-23 US US10/669,072 patent/US6806097B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5932907A (en) * | 1996-12-24 | 1999-08-03 | International Business Machines Corporation | Method, materials, and structures for noble metal electrode contacts to silicon |
WO1999028972A1 (en) * | 1997-11-28 | 1999-06-10 | Motorola Inc. | Semiconductor device with ferroelectric capacitor dielectric and method for making |
WO2000039842A1 (de) * | 1998-12-23 | 2000-07-06 | Infineon Technologies Ag | Kondensatorelektrodenanordnung |
DE10014315A1 (de) * | 1999-03-26 | 2000-10-05 | Sharp Kk | Halbleiterspeicher und Verfahren zur Herstellung desselben |
Non-Patent Citations (2)
Title |
---|
M. HEINTZE, A. CATANA, P.E. SCHMID, F. LÉVY, P. STADELMANN AND P. WEISS: "Oxygen impurity effects on the formation of thin titanium silicide films by rapid thermal annealing" J. PHYS. D: APPL. PHYS., Bd. 23, 1990, Seiten 1076-1081, XP001124373 * |
WEE A T S, HUAN A C H, THIAN W H, TAN K L, HOGAN R,: "INVESTIGATION OF TITANIUM SILICIDE FORMATION USING SECONDARY ION MASS SPECTROMETRY" MAT. RES.SOC.SYMP.PROC., Bd. 342, 1994, Seiten 117-122, XP008010645 Pittsburgh, USA * |
Also Published As
Publication number | Publication date |
---|---|
JP2004526320A (ja) | 2004-08-26 |
US20040157345A1 (en) | 2004-08-12 |
DE10114406A1 (de) | 2002-10-02 |
CN1331215C (zh) | 2007-08-08 |
EP1371093A2 (de) | 2003-12-17 |
CN1518766A (zh) | 2004-08-04 |
US6806097B2 (en) | 2004-10-19 |
KR20030085034A (ko) | 2003-11-01 |
KR100579337B1 (ko) | 2006-05-12 |
WO2002078084A3 (de) | 2003-03-13 |
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