Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
  • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/942—Masking
  • Y10S438/947—Subphotolithographic processing
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/942—Masking
  • Y10S438/948—Radiation resist
  • Y10S438/949—Energy beam treating radiation resist on semiconductor

Definitions

• the present invention contains subject matter similar to that disclosed in U.S. Application No. 09/824,218, filed on April 3, 2001 (Attorney Docket No. 50432-112).
• the present invention relates to the field of semiconductor processing, and more particularly to the formation of metal gate electrodes.
• polysilicon gate electrodes are formed from semiconductor materials that suffer from higher resistivities than most metal materials. Therefore, polysilicon gate electrodes may operate at much slower speeds than gates made of metallic materials. To partially compensate for the high resistance, polysilicon materials often require extensive and expensive suicide processing in order to increase their speed of operation to acceptable levels.
• a SiRN anti-reflective coating (ARC) 18 is formed on the metal gate layer 16. This is followed by formation of a cap layer 20 over the ARC layer 18.
• the cap layer 20 may comprise silicon nitride
• the anti-reflective coating 18 and the cap layer 20 aid in the patterning of the gate prior to the reactive ion etch process used to form the gate.
• Anti-reflective coatings 18, 20 increase the resolution during the lithography process.
• the metal gate is now etched. This is accomplished by conventional patterning and etching techniques.
• the tungsten layer is typically etched with a fluorine containing chemistry, such as SF 6 N 2 or SF 6 /C1 2 N 2 , with WF 6 being the primary product species.
• a fluorine containing chemistry such as SF 6 N 2 or SF 6 /C1 2 N 2
• WF 6 being the primary product species.
• the latter chemistry has yielded good profiles.
• an appropriate SF 6 /C1 2 ratio may be chosen to provide the best profiles.
• the recipe may even be richer in Cl 2 than in SF 6 as required. It is desirable for the etchant to have good selectivity to the TiN of the barrier layer 14 so that the tungsten can be cleared across the entire wafer without attacking the gate oxide.
• the TiN ideally serves as an etch stop layer during the etching of the tungsten.
• An ideal etching process is depicted in Figure IB, which shows the patterning of the metal gate electrode by an anisotropic reactive ion etch process, stopping on the TiN at the barrier layer 14.
• Figure IB shows the patterning of the metal gate electrode by an anisotropic reactive ion etch process, stopping on the TiN at the barrier layer 14.
• this depiction is only an ideal depiction, as the TiN has proven in practice to be an inadequate etch stop layer.
• Figure 1C when the tungsten is being cleared from the rest of the wafer, the TiN is completely etched on some parts of the wafer (indicated by reference numeral 22 in Figure 1C) allowing the etchant to attack the gate oxide 12.
• embodiments of the present invention which provide a method of forming a metal gate on a wafer, comprising the steps of forming a gate oxide on a substrate and forming a first metal layer on the gate oxide.
• the etch selectivity in at least a surface region of the first metal layer is increased.
• a second metal layer is formed on the first metal layer.
• the second metal layer is then etched to form a metal gate, with the etching stopping on the surface region of the first metal layer.
• the first metal layer comprises TiN and the etch selectivity is increased by implanting a metallic species into the TiN.
• the metallic species comprises either aluminum or tantalum, depending on the nature of the W etch chemistry. If the W etch chemistry is F-rich, aluminum may be used as the etch stop layer owing to the low vapor pressure of A1F 3 . On the other hand, if the W etch chemistry is Cl-rich, the much lower vapor pressure of TaCl 5 as opposed to TaFs, WF 6 and TiCl 4 will also result in a significant slowdown of the etch rate, allowing the etch to be terminated when clearing of W is detected.
• the surface region of the TiN, containing the implanted metallic species, has better etch selectivity than the region of TiN that does not contain the metallic species.
• the etch selectivity is thereby improved without additional layers, and without significantly affecting the work function ofthe TiN.
• the etching of the tungsten may proceed and stop on the TiN layer, thereby assuredly protecting the gate oxide underlying the etch stop layer and the TiN of the first metal layer.
• a similar approach may also be used when TaN, TaSiN or WN for example are used as the underlying metal gates, since the F- component of the W etch will readily attack these materials as well as gate oxide.
• an aluminum implanted layer will provide a chance to switch to Cl 2 based etches with suitable addiives such as HBr, O 2 or N 2 , where the etch rate of these materials is much lower and also results in increased selectivity to gate oxide materials.
• suitable addiives such as HBr, O 2 or N 2 , where the etch rate of these materials is much lower and also results in increased selectivity to gate oxide materials.
• the earlier stated needs are also met by another embodiment of the present invention, which provides a metal gate structure comprising a gate oxide and a first metal layer on the gate oxide.
• the first metal layer has a surface region with greater etch selectivity than a remaining region of the first metal layer.
• a second metal layer is on the first metal layer.
• the first metal layer comprises TiN
• the second metal layer comprises tungsten.
• the TiN has implanted metal in the surface region, this metal comprising tantalum in some embodiments and aluminum in other embodiments.
• a metal gate structure comprising a TiN layer having a lower region and a surface region with metal impurities.
• the surface region has greater etch selectivity than the lower region.
• a tungsten gate is provided on the TiN layer.
• Figure 1A depicts a metal gate stack prior to the patterning of the metal gate, in accordance with the prior art.
• Figure IB depicts a metal gate after an ideal etching process in accordance with the prior art.
• Figure 1C depicts the metal gate after an actual etching process, exhibiting areas of degraded gate oxide, in accordance with methods of the prior art.
• Figure 2 is a depiction of a cross-section of a portion of a metal gate structure during formation of the metal gate, in accordance with embodiments of the present invention.
• Figure 3 depicts the structure of Figure 2 after implantation of ions into a surface region of a first metal layer of the metal gate structure, in accordance with embodiments of the present invention.
• Figure 4 depicts the structure of Figure 3 following the deposition of the metal gate and anti- reflective coatings, in accordance with embodiments of the present invention.
• Figure 5 depicts the structure of Figure 4 after etching has been performed to etch the metal gate and first metal layer, in accordance with embodiments of the present invention.
• Figure 6 depicts the metal gate structure of Figure 5 after the first metal layer has been removed across the wafer in accordance with embodiments of the present invention.
• Figure 7 depicts the metal gate structure of Figure 6 after the anti-reflective coatings have been removed in accordance with embodiments of the present invention.
• the present invention addresses and solves problems related to the formation of metal gate structures, in particular, to those involved in the etching of a metal gate causing the possible degradation of gate oxide across a wafer.
• the present invention which increases the etch selectivity of the TiN currently used in metal gates. This is achieved, in embodiments of the invention, by implanting a metallic species, such as aluminum or tantalum, into a surface region of the TiN.
• a metallic species such as aluminum or tantalum
• implantation is employed to increase the etch selectivity of the TiN, a separate, additional etch stop layer is not required, so that the stack height is not appreciably altered.
• Some increase of the TiN layer from before may be required to compensate for the finite thickness of the implanted region, if electrical constraints determine that a certain thickness of un-modified TiN is required to define the gate structure.
• the improved TiN layer provides adequate etch stopping capability and the implanted metallic species does not detrimentally affect the work function of the TiN.
• the implanted species must itself be etchable in chemistries other than that used for the W etch. For example, Al can be etched in Cl based chemistries, and Ta can be cleared either by a short F based breakthrough or a longer Cl based step.
• Figure 2 depicts a portion of a metal gate structure during its formation in accordance with embodiments of the present invention.
• a substrate 30 is provided with a gate oxide layer 32 by conventional methodology.
• the gate oxide layer 32 has a thickness of between about 15 to about 30 A in embodiments of the present invention.
• a first metal layer 34 is formed on the gate oxide layer 32.
• the first metal layer 34 may comprise TiN, in certain embodiments of the present invention, although other metals may be used.
• the TiN is deposited by conventional methodologies, such as physical vapor deposition, for example.
• the thickness of the first metal layer 34 may be between about 100 to about 200 A in embodiments of the present invention.
• the first metal layer 34 serves as a barrier layer and an adhesion layer, in certain embodiments.
• the TiN metal layer served the function of an etch stop layer. It has been found, however, that untreated TiN is inadequate in this function as it fails to protect the underlying gate oxide across the wafer during the etching of the overlying metal gate layer.
• the first metal layer 34 is treated to improve the etch selectivity of at least a surface region of the layer 34.
• the present invention introduces metal impurities 38 into at least a surface region 37 of the first metal layer 34.
• the surface region 37 may extend completely through the first metal layer 34.
• the surface region 37 extends only through a portion of the first metal layer 34.
• a lower region 35 of the first metal layer 34 contains little or none of the impurities 38.
• the metallic species 38 introduced into the TiN of the first metal layer 34 may be one or more of a number of different materials.
• Candidates for the metallic species include aluminum, tantalum, copper, and gold. Of these materials, aluminum and tantalum are favored, since copper and gold have deleterious effects on transistors.
• Aluminum forms a stable nonvolatile fluoride A1F 3 at typical cathode temperatures (50 °C) and can adequately stop F-containing W etch chemistries. Tantalum chloride has a much lower vapor pressure than TaF 5 and WF 6 and can appreciably slow down the etch rate in Cl 2 -rich SF 6 /C N 2 tungsten etch chemistries.
• aluminum and tantalum are described as exemplary metallic species in the first metal layer 34, other materials or combinations of materials may be used without departing from the scope of the present invention.
• the use of implantation to increase the etch selectivity of a surface region 37 of the first metal layer 34 does not affect the height of the metal gate stack, increases the etch stopping capability of the first metal layer 34, and does not significantly impact the work function of the TiN in the first metal layer 34.
• the remainder of the metal gate structure is provided on the first metal layer 34.
• Tungsten may be deposited as a second metal layer 38 to a thickness of between about 500 to about 1,000 A. Although tungsten is described as an exemplary material, other metals or metal alloys may be employed in the second metal layer 38.
• Anti-reflective coatings such as an SiRN ARC 40, are provided on the second metal layer 38.
• a cap layer 42 is then formed over the ARC layer 40.
• the ARC layer 40 may be between about 300 to about 1,000 A.
• the cap layer 42 which may be silicon nitride (SiN), for example, may be between about 300 to about 1,000 A.
• the anti-reflective coating of layer 40 and the cap layer 42 aid in the patterning of the metal gate structure.
• the improved etch selectivity of the TiN of the first metal layer 34 in the surface region 37 prevents this unintended etching through to the gate oxide layer 32. Hence, the etching process proceeds until the surface region 37 of the first metal layer 34 is reached. If aluminum is used as the implanted species, the etching effectively stops due to formation of a stable, non-volatile AlF 3 -rich layer at typical cathode temperatures (50 °C).
• the etching slows down appreciably due to the much lower vapor pressure of TaCl 5 as compared to TaF 5 or WF ⁇ . This permits termination of the W etch before any attack of underlying TiN occurs. The complete etching of the TiN of the first metal layer 34 and degradation of the gate oxide in the gate oxide layer 32 is thereby prevented.
• a different etch chemistry is now employed, as depicted in Figure 6, to remove the first metal layer 34 over the gate oxide 32 in areas not under the second metal layer 38 of the metal gate.
• Figure 7 depicts the metal gate structure of Figure 6 after the cap layer 42 and the anti- reflective coating 40 have been removed by conventional etching techniques.
• the TiN layer with improved etch selectivity protects the gate oxide across the wafer during the etching of the metal gate and serves to improve the yield.
• the height of the metal gate stack is unchanged and the work function of the TiN is not deleteriously affected.

Landscapes

• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Drying Of Semiconductors (AREA)

Priority Applications (5)

Applications Claiming Priority (2)

Publications (2)

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Family Applications (1)

Country Status (9)

Families Citing this family (23)

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• 2001
  • 2001-03-19 US US09/810,348 patent/US6444513B1/en not_active Expired - Lifetime
• 2002
  • 2002-02-06 DE DE60211318T patent/DE60211318T2/de not_active Expired - Lifetime
  • 2002-02-06 AU AU2002238059A patent/AU2002238059A1/en not_active Abandoned
  • 2002-02-06 KR KR1020037012166A patent/KR100819193B1/ko not_active Expired - Fee Related
  • 2002-02-06 CN CNB028067924A patent/CN1246883C/zh not_active Expired - Fee Related
  • 2002-02-06 WO PCT/US2002/003556 patent/WO2002075791A2/en not_active Ceased
  • 2002-02-06 EP EP02704371A patent/EP1371088B1/en not_active Expired - Lifetime
  • 2002-02-06 JP JP2002574109A patent/JP4076862B2/ja not_active Expired - Fee Related
  • 2002-02-27 TW TW091103577A patent/TWI246721B/zh not_active IP Right Cessation
  • 2002-08-27 US US10/228,045 patent/US6657268B2/en not_active Expired - Fee Related

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