Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/57—Protection from inspection, reverse engineering or tampering
  • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates to a shielding device with which effective protection against attacks on an integrated circuit is achieved.
• An active protective shield in which current-carrying conductor tracks and / or active components are used in order to shield an external attack on the circuit, is particularly effective. So far, the risk of analyzing the circuits from the back of the semiconductor chip, i. H. through the semiconductor substrate, neglected.
• SOI substrate Silicon On Insulator
• SOI substrate Silicon On Insulator
• It consists largely of a bulk silicon layer in volume, on which, separated by a thin insulator layer from the bulk silicon layer, there is a thin, usually crystalline body silicon layer in which the semiconductor components are formed.
• the object of the present invention is to provide effective protection against attacks on integrated circuits from the back of the substrate. This object is achieved with the shielding device for integrated circuits with the features of claim 1. Refinements result from the dependent claims.
• the shielding device comprises means for optical and / or electrical shielding, which are arranged on the side of the integrated circuit facing the substrate in the semiconductor chip.
• Preferred configurations use an SOI substrate in order to form the integrated circuit in the body silicon layer of the SOI substrate and to use the insulator layer of the SOI substrate as an optical shielding device from the bulk silicon layer.
• electrical conductors in particular conductor tracks or conductor surfaces, to be provided as a shielding device in the bulk silicon layer of an SOI substrate, preferably in the vicinity of the insulator layer.
• These conductors can be connected to the body silicon layer or to one or more components of the circuit present in the body silicon layer by means of one or more vias which are led through the insulation layer into the body silicon layer. In this way, active control of the conductors arranged in the bulk silicon layer can be realized.
• This figure shows in cross section an SOI substrate with a conductor structure arranged according to the invention.
• the SOI substrate Silicon On Insulator
• a bulk silicon layer 1 which, as a silicon body, forms the component that makes up the essential volume of the substrate, a thin insulator layer 2 applied thereon or formed in the silicon body, and a likewise thin, preferably crystalline one body silicon layer 3, in which the semiconductor components of the integrated circuit are formed.
• the thicknesses of the layers are not shown to scale, since it is only a matter of the basic arrangement of the layers in relation to one another.
• Electrically conductive vias 4 are shown in the figure with vertical lines, which pass through the insulator layer 2 and electrically connect the body silicon layer 3 to the bulk silicon layer 1.
• these plated-through holes 4 can be connected in any manner to components of a circuit integrated in the body silicon layer 3.
• the plated-through holes 4 are electrically conductively connected to conductors 5, which are attached in the bulk silicon layer 1, preferably in the vicinity of the insulator layer 2.
• These electrical conductors can be designed as conductor tracks, which can be structured in a grid-like or double-grid fashion, or as conductor surfaces or the like.
• These conductors 5 can be produced in the manufacture of the substrate by implanting dopant into the semiconductor material of the bulk silicon layer 1. It is advantageous if the conductors 5 cover the largest possible area of the substrate surface.
• the SOI substrate is mounted on a module carrier 6, which is, however, not essential for the invention.
• an SOI substrate even in semiconductor circuits, for which no SOI substrate is normally provided, means that optical inspection using backside IR microscopy is no longer possible due to the different refractive indices of the semiconductor material and the isolator.
• the insulator layer therefore forms a shielding device according to the invention.
• electrical conductors can be provided as shielding components; in particular, these Conductor via vertical electrically conductive connections, e.g. B. the vias described, are actively controlled with components of the integrated circuit.
• active backside shielding of the substrate can also be provided in the case of a conventional substrate without an insulation layer.
• a protective shield acts like an active protective shield on the top of the IC chip.

Landscapes

• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Semiconductor Integrated Circuits (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Optical Integrated Circuits (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Related Child Applications (1)

Publications (2)

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Family Applications (1)

Country Status (5)

Families Citing this family (11)

Family Cites Families (18)

• 2001
  • 2001-02-08 DE DE10105725A patent/DE10105725B4/de not_active Expired - Fee Related
• 2002
  • 2002-02-08 WO PCT/DE2002/000470 patent/WO2002063687A2/de not_active Ceased
  • 2002-02-08 DE DE50212016T patent/DE50212016D1/de not_active Expired - Lifetime
  • 2002-02-08 EP EP02714001A patent/EP1358676B1/de not_active Expired - Lifetime
  • 2002-02-08 AT AT02714001T patent/ATE391343T1/de not_active IP Right Cessation
• 2003
  • 2003-08-08 US US10/637,192 patent/US6919618B2/en not_active Expired - Fee Related

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