FR2951016B1 - Procede de protection d'une puce de circuit integre contre des attaques laser - Google Patents

Procede de protection d'une puce de circuit integre contre des attaques laser

Info

Publication number
FR2951016B1
FR2951016B1 FR0956920A FR0956920A FR2951016B1 FR 2951016 B1 FR2951016 B1 FR 2951016B1 FR 0956920 A FR0956920 A FR 0956920A FR 0956920 A FR0956920 A FR 0956920A FR 2951016 B1 FR2951016 B1 FR 2951016B1
Authority
FR
France
Prior art keywords
protecting
integrated circuit
circuit chip
chip against
against laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0956920A
Other languages
English (en)
Other versions
FR2951016A1 (fr
Inventor
Pascal Fornara
Fabrice Marinet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR0956920A priority Critical patent/FR2951016B1/fr
Priority to US12/897,217 priority patent/US8399280B2/en
Priority to EP10186459.3A priority patent/EP2306518B1/fr
Priority to CN201010504549.6A priority patent/CN102034688B/zh
Publication of FR2951016A1 publication Critical patent/FR2951016A1/fr
Application granted granted Critical
Publication of FR2951016B1 publication Critical patent/FR2951016B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3223—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
FR0956920A 2009-10-05 2009-10-05 Procede de protection d'une puce de circuit integre contre des attaques laser Expired - Fee Related FR2951016B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR0956920A FR2951016B1 (fr) 2009-10-05 2009-10-05 Procede de protection d'une puce de circuit integre contre des attaques laser
US12/897,217 US8399280B2 (en) 2009-10-05 2010-10-04 Method for protecting an integrated circuit chip against laser attacks
EP10186459.3A EP2306518B1 (fr) 2009-10-05 2010-10-04 Méthode de protection d'une puce de circuit intégré contre une analyse par attaques laser
CN201010504549.6A CN102034688B (zh) 2009-10-05 2010-10-08 保护集成电路芯片免受激光攻击的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0956920A FR2951016B1 (fr) 2009-10-05 2009-10-05 Procede de protection d'une puce de circuit integre contre des attaques laser

Publications (2)

Publication Number Publication Date
FR2951016A1 FR2951016A1 (fr) 2011-04-08
FR2951016B1 true FR2951016B1 (fr) 2012-07-13

Family

ID=42124358

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0956920A Expired - Fee Related FR2951016B1 (fr) 2009-10-05 2009-10-05 Procede de protection d'une puce de circuit integre contre des attaques laser

Country Status (2)

Country Link
US (1) US8399280B2 (fr)
FR (1) FR2951016B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2981783B1 (fr) * 2011-10-19 2014-05-09 St Microelectronics Rousset Systeme de detection d'une attaque par laser d'une puce de circuit integre
US9306573B2 (en) * 2014-07-21 2016-04-05 Microsemi SoC Corporation Apparatus and method for detecting and preventing laser interrogation of an FPGA integrated circuit

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4203780A (en) * 1978-08-23 1980-05-20 Sony Corporation Fe Ion implantation into semiconductor substrate for reduced lifetime sensitivity to temperature
JPH11250215A (ja) * 1998-03-04 1999-09-17 Nippon Telegr & Teleph Corp <Ntt> Ｉｃチップおよびｉｃカード
US6191618B1 (en) 1999-07-23 2001-02-20 Intel Corporation Contention-free, low clock load domino circuit topology
US7485920B2 (en) * 2000-06-14 2009-02-03 International Rectifier Corporation Process to create buried heavy metal at selected depth
JP4710187B2 (ja) * 2000-08-30 2011-06-29 ソニー株式会社 多結晶シリコン層の成長方法および単結晶シリコン層のエピタキシャル成長方法
DE10105725B4 (de) * 2001-02-08 2008-11-13 Infineon Technologies Ag Halbleiterchip mit einem Substrat, einer integrierten Schaltung und einer Abschirmvorrichtung
US6855584B2 (en) * 2001-03-29 2005-02-15 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
DE10337256A1 (de) * 2002-11-21 2004-06-09 Giesecke & Devrient Gmbh Integrierte Schaltkreisanordnung und Verfahren zur Herstellung derselben
JP2005051040A (ja) * 2003-07-29 2005-02-24 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及び半導体基板
JP4250038B2 (ja) 2003-08-20 2009-04-08 シャープ株式会社 半導体集積回路
EP1691413A1 (fr) 2005-02-11 2006-08-16 Axalto SA Composant électronique protégé contre les attaques.
JP5334354B2 (ja) * 2005-05-13 2013-11-06 シャープ株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
US8399280B2 (en) 2013-03-19
FR2951016A1 (fr) 2011-04-08
US20110080190A1 (en) 2011-04-07

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20150630