US20040124524A1 - Shielding device for integrated circuits - Google Patents
Shielding device for integrated circuits Download PDFInfo
- Publication number
- US20040124524A1 US20040124524A1 US10/637,192 US63719203A US2004124524A1 US 20040124524 A1 US20040124524 A1 US 20040124524A1 US 63719203 A US63719203 A US 63719203A US 2004124524 A1 US2004124524 A1 US 2004124524A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- conductor
- silicon layer
- shielding device
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/57—Protection from inspection, reverse engineering or tampering
- H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a shielding device, with which effective protection against intrusions of an integrated circuit can be achieved.
- SOI substrate Silicon On Insulator (SOI) substrate is widely used in semiconductor technology. In terms of volume, it is, for the most part, a bulk silicon layer on which, separated from the bulk silicon layer by a thin insulator layer, there is a thin, generally crystalline body silicon layer in which the semiconductor components are formed.
- SOI Silicon On Insulator
- a shielding device for the integrated circuit including a shield disposed on a side of the integrated circuit in the semiconductor chip facing the substrate, the shield at least one of optically and electrically shielding the integrated circuit.
- the shielding device includes measures for optical and/or electrical shielding, which are disposed on the side of the integrated circuit in the semiconductor chip facing the substrate.
- Preferred configurations use an SOI substrate to form the integrated circuit in the body silicon layer of the SOI substrate and to use the insulator layer of the SOI substrate as a device for optical shielding from the bulk silicon layer.
- the substrate is an SOI substrate and the shield is an insulation layer of the substrate.
- the substrate is an SOI substrate having a bulk silicon layer, a body silicon layer having at least one component formed therein, and an insulator layer having a via
- the conductor is disposed in the bulk silicon layer
- the via electrically connects the conductor to at least one of the body silicon layer and the component.
- electrical conductors in particular, conductor tracks or conductor surfaces, are provided as a shielding device in the bulk silicon layer of an SOI substrate, preferably, in the vicinity of the insulator layer.
- These conductors may be connected by one or more vias, which pass through the insulation layer into the body silicon layer, to the body silicon layer or to one or more components of the circuit that are present in the body silicon layer.
- the conductors disposed in the bulk silicon layer can be operated actively.
- the shield is at least one conductor disposed in the substrate on the side of the integrated circuit facing the substrate.
- the conductor is an element selected from the group consisting of a conductor surface, a conductor track, a conductor grid and a conductor double grid.
- the conductor is a doped region in the substrate.
- FIGURE is a fragmentary, cross-sectional view of an SOI substrate having a conductor structure disposed according to the invention.
- the thicknesses of the layers are not represented true to scale because it is only the fundamental configuration of the layers relative to one another that is important.
- a SOI substrate has a bulk silicon layer 1 that, as a silicon body, forms the part that substantially makes up the volume of the substrate, a thin insulator layer 2 placed thereon or formed in the silicon body, and a likewise thin, preferably, crystalline body silicon layer 3 , in which the semiconductor components of the integrated circuit are formed.
- vertical lines are used to represent electrically conductive vias 4 that pass through the insulator layer 2 and electrically connect the body silicon layer 3 to the bulk silicon layer 1 .
- these vias 4 may be joined in any desired way to components of an integrated circuit in the body silicon layer 3 .
- the vias 4 are electrically conducted to conductors 5 that are placed in the bulk silicon layer 1 , preferably, in the vicinity of the insulator layer 2 .
- These electrical conductors may be configured in the form of conductor tracks, which may be structured as a grid or as a double grid, or in the form of conductor surfaces or the like.
- These conductors 5 may be produced during the fabrication of the substrate by dopant implantation in the semiconductor material of the bulk silicon layer 1 . It is advantageous for the conductors 5 to cover as large as possible an area of the substrate surface.
- the SOI substrate is mounted on a module support 6 , although the latter is not essential to the invention.
- active backside shielding of the substrate may also be provided for a conventional substrate without an insulation layer.
- Such a shield works, in principle, like an active shield on the top side of the IC chip.
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Optical Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
A shielding device includes optical and/or electrical shielding disposed on the side of the integrated circuit in the semiconductor chip facing the substrate. Preferred configurations use an SOI substrate with the integrated circuit in the body silicon layer and the insulator layer as a device for optical shielding from the bulk silicon layer. Electrical conductors may be present as an optical and electrical shielding device in the bulk silicon layer, and they may be connected to the circuit using vias.
Description
- This application is a continuation of copending International Application No. PCT/DE02/00470, filed Feb. 8, 2002, which designated the United States and was not published in English.
- 1. Field of the Invention
- The present invention relates to a shielding device, with which effective protection against intrusions of an integrated circuit can be achieved.
- For integrated circuits in security-relevant applications, the difficulty arises that the circuits need to be protected against intrusions for spying on or analyzing the relevant circuit, e.g., by focused ion beam (FIB). Optical or mechanical analysis methods are also employed.
- There are already a number of security concepts with which the integrated circuits can be protected against such intrusions, in particular, provided with a shield. An active shield, in which current-carrying conductor tracks and/or active components are used to shield against an external intrusion of the circuit, is particularly effective in this context. To date, the risk of the circuits being analyzed from the backside of the semiconductor chip, i.e., through the semiconductor substrate, has been ignored.
- A so-called Silicon On Insulator (SOI) substrate is widely used in semiconductor technology. In terms of volume, it is, for the most part, a bulk silicon layer on which, separated from the bulk silicon layer by a thin insulator layer, there is a thin, generally crystalline body silicon layer in which the semiconductor components are formed.
- It is accordingly an object of the invention to provide a shielding device for integrated circuits that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that provides effective protection against intrusions of integrated circuits from the substrate backside.
- With the foregoing and other objects in view, in a semiconductor chip having a substrate with an integrated circuit, there is provided, in accordance with the invention, a shielding device for the integrated circuit including a shield disposed on a side of the integrated circuit in the semiconductor chip facing the substrate, the shield at least one of optically and electrically shielding the integrated circuit.
- The shielding device according to the invention includes measures for optical and/or electrical shielding, which are disposed on the side of the integrated circuit in the semiconductor chip facing the substrate. Preferred configurations use an SOI substrate to form the integrated circuit in the body silicon layer of the SOI substrate and to use the insulator layer of the SOI substrate as a device for optical shielding from the bulk silicon layer.
- In accordance with a further feature of the invention, the substrate is an SOI substrate and the shield is an insulation layer of the substrate.
- In accordance with an added feature of the invention, the substrate is an SOI substrate having a bulk silicon layer, a body silicon layer having at least one component formed therein, and an insulator layer having a via, the conductor is disposed in the bulk silicon layer, and the via electrically connects the conductor to at least one of the body silicon layer and the component.
- In accordance with another feature of the invention, electrical conductors, in particular, conductor tracks or conductor surfaces, are provided as a shielding device in the bulk silicon layer of an SOI substrate, preferably, in the vicinity of the insulator layer. These conductors may be connected by one or more vias, which pass through the insulation layer into the body silicon layer, to the body silicon layer or to one or more components of the circuit that are present in the body silicon layer. As such, the conductors disposed in the bulk silicon layer can be operated actively.
- In accordance with an additional feature of the invention, the shield is at least one conductor disposed in the substrate on the side of the integrated circuit facing the substrate.
- In accordance with yet another feature of the invention, the conductor is an element selected from the group consisting of a conductor surface, a conductor track, a conductor grid and a conductor double grid.
- In accordance with a concomitant feature of the invention, the conductor is a doped region in the substrate.
- Other features that are considered as characteristic for the invention are set forth in the appended claims.
- Although the invention is illustrated and described herein as embodied in a shielding device for integrated circuits, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
- The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
- The FIGURE is a fragmentary, cross-sectional view of an SOI substrate having a conductor structure disposed according to the invention.
- In the FIGURE, the thicknesses of the layers are not represented true to scale because it is only the fundamental configuration of the layers relative to one another that is important.
- Referring now to the single FIGURE of the drawing, it is seen that a SOI substrate has a bulk silicon layer1 that, as a silicon body, forms the part that substantially makes up the volume of the substrate, a thin insulator layer 2 placed thereon or formed in the silicon body, and a likewise thin, preferably, crystalline
body silicon layer 3, in which the semiconductor components of the integrated circuit are formed. - In the FIGURE, vertical lines are used to represent electrically conductive vias4 that pass through the insulator layer 2 and electrically connect the
body silicon layer 3 to the bulk silicon layer 1. In thebody silicon layer 3, these vias 4 may be joined in any desired way to components of an integrated circuit in thebody silicon layer 3. The vias 4 are electrically conducted toconductors 5 that are placed in the bulk silicon layer 1, preferably, in the vicinity of the insulator layer 2. These electrical conductors may be configured in the form of conductor tracks, which may be structured as a grid or as a double grid, or in the form of conductor surfaces or the like. Theseconductors 5 may be produced during the fabrication of the substrate by dopant implantation in the semiconductor material of the bulk silicon layer 1. It is advantageous for theconductors 5 to cover as large as possible an area of the substrate surface. In the example, the SOI substrate is mounted on amodule support 6, although the latter is not essential to the invention. - The use of an SOI substrate even in the case of semiconductor circuits for which an SOI substrate is not normally provided, has the effect that optical inspection by backside infrared microscopy is no longer possible due to the different refractive indices of the semiconductor material and the insulator. The insulator layer, therefore, forms a shielding device according to the invention. In a conventional semiconductor substrate, or, especially, in the bulk silicon layer of an SOI substrate, as in the exemplary embodiment which is described, electrical conductors may be provided as shielding components; in particular, these conductors may be actively operated using components of the integrated circuit through vertical electrical connections, e.g., the vias that have been described.
- In configurations with electrical conductors as a shielding device on the substrate side of the semiconductor chip, and electrical connection between these conductors and the integrated circuit, it is possible, in particular, to apply signal pulses to the conductors of the shielding device and, by subsequent verification of these applied signal pulses, to detect possible manipulations from the backside of the substrate, i.e., from the bulk silicon layer in the exemplary embodiment with an SOI substrate. Such a configuration provides an active backside shield.
- Although the use of an SOI substrate is preferred according to the invention, active backside shielding of the substrate may also be provided for a conventional substrate without an insulation layer. Such a shield works, in principle, like an active shield on the top side of the IC chip.
Claims (12)
1. In a semiconductor chip having a substrate with an integrated circuit, a shielding device for the integrated circuit comprising:
a shield disposed on a side of the integrated circuit in the semiconductor chip facing the substrate, said shield at least one of optically and electrically shielding the integrated circuit.
2. The shielding device according to claim 1 , wherein:
said substrate is an SOI substrate; and
said shield is an insulation layer of said substrate.
3. The shielding device according to claim 1 , wherein said shield is at least one conductor disposed in the substrate on the side of the integrated circuit facing the substrate.
4. The shielding device according to claim 3 , wherein:
the substrate is an SOI substrate having:
a bulk silicon layer;
a body silicon layer having at least one component formed therein; and
an insulator layer having a via;
said conductor is disposed in said bulk silicon layer; and
said via electrically connects said conductor to at least one of said body silicon layer and said component.
5. The shielding device according to claim 3 , wherein said conductor is an element selected from the group consisting of a conductor surface, a conductor track, a conductor grid and a conductor double grid.
6. The shielding device according to claim 3 , wherein said conductor is a doped region in the substrate.
7. In a semiconductor chip having a substrate with an integrated circuit, a shielding device for the integrated circuit comprising:
means for at least one of optical and electrical shielding disposed on a side of the integrated circuit in the semiconductor chip facing the substrate.
8. The shielding device according to claim 7 , wherein:
said substrate is an SOI substrate; and
said shielding means is an insulation layer of said substrate.
9. The shielding device according to claim 7 , wherein said shielding means is at least one conductor disposed in the substrate on the side of the integrated circuit facing the substrate.
10. The shielding device according to claim 9 , wherein:
the substrate is an SOI substrate having:
a bulk silicon layer;
a body silicon layer having at least one component formed therein; and
an insulator layer having a via;
said conductor is disposed in said bulk silicon layer; and
said via electrically connects said conductor to at least one of said body silicon layer and said component.
11. The shielding device according to claim 9 , wherein said conductor is an element selected from the group consisting of a conductor surface, a conductor track, a conductor grid and a conductor double grid.
12. The shielding device according to claim 9 , wherein said conductor is a doped region in the substrate.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10105725.3 | 2001-02-08 | ||
DE10105725A DE10105725B4 (en) | 2001-02-08 | 2001-02-08 | Semiconductor chip with a substrate, an integrated circuit and a shielding device |
PCT/DE2002/000470 WO2002063687A2 (en) | 2001-02-08 | 2002-02-08 | Screening device for integrated circuits |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2002/000470 Continuation WO2002063687A2 (en) | 2001-02-08 | 2002-02-08 | Screening device for integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040124524A1 true US20040124524A1 (en) | 2004-07-01 |
US6919618B2 US6919618B2 (en) | 2005-07-19 |
Family
ID=7673280
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/637,192 Expired - Fee Related US6919618B2 (en) | 2001-02-08 | 2003-08-08 | Shielding device for integrated circuits |
Country Status (5)
Country | Link |
---|---|
US (1) | US6919618B2 (en) |
EP (1) | EP1358676B1 (en) |
AT (1) | ATE391343T1 (en) |
DE (2) | DE10105725B4 (en) |
WO (1) | WO2002063687A2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2893183A1 (en) * | 2005-11-10 | 2007-05-11 | Gemplus Sa | METHOD FOR PROTECTING AN ELECTRONIC COMPONENT AGAINST FAULT INJECTION ATTACKS |
US9653410B1 (en) | 2016-03-15 | 2017-05-16 | Nxp Usa, Inc. | Transistor with shield structure, packaged device, and method of manufacture |
US9741671B1 (en) | 2016-11-10 | 2017-08-22 | Nxp B.V. | Semiconductor die with backside protection |
EP3246943A1 (en) * | 2016-05-20 | 2017-11-22 | Commissariat à l'énergie atomique et aux énergies alternatives | Electronic device having puf-type identification |
EP2232412B1 (en) * | 2007-08-02 | 2019-03-06 | Nxp B.V. | Tamper-resistant semiconductor device and methods of manufacturing thereof |
US10593619B1 (en) | 2018-08-28 | 2020-03-17 | Nsp Usa, Inc. | Transistor shield structure, packaged device, and method of manufacture |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10337256A1 (en) * | 2002-11-21 | 2004-06-09 | Giesecke & Devrient Gmbh | Integrated circuit and production process especially for chip cards has active circuit on substrate surface and deep doped layer to protect against rear interrogation |
FR2950997B1 (en) * | 2009-10-05 | 2011-12-09 | St Microelectronics Rousset | INTEGRATED CIRCUIT CHIP PROTECTED AGAINST LASER ATTACKS |
EP2306518B1 (en) * | 2009-10-05 | 2014-12-31 | STMicroelectronics (Rousset) SAS | Method of protecting an integrated circuit chip against spying by laser attacks |
FR2951016B1 (en) * | 2009-10-05 | 2012-07-13 | St Microelectronics Rousset | METHOD FOR PROTECTING AN INTEGRATED CIRCUIT CHIP AGAINST LASER ATTACKS |
FR2980636B1 (en) | 2011-09-22 | 2016-01-08 | St Microelectronics Rousset | PROTECTION OF AN ELECTRONIC DEVICE AGAINST REAR-BACK LASER ATTACK, AND CORRESPONDING SEMICONDUCTOR SUPPORT |
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US5424235A (en) * | 1990-09-10 | 1995-06-13 | Sony Corporation | Semiconductor memory device |
US5525531A (en) * | 1995-06-05 | 1996-06-11 | International Business Machines Corporation | SOI DRAM with field-shield isolation |
US5742082A (en) * | 1996-11-22 | 1998-04-21 | Motorola, Inc. | Stable FET with shielding region in the substrate |
US6310372B1 (en) * | 1997-12-25 | 2001-10-30 | Seiko Epson Corporation | Substrate for electro-optical apparatus, electro-optical apparatus, method for driving electro-optical apparatus, electronic device and projection display device |
US20020040998A1 (en) * | 1998-12-24 | 2002-04-11 | Hyundai Electronics Industries, Co., Ltd. | SOI semiconductor device capable of preventing floating body effect |
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US4179310A (en) * | 1978-07-03 | 1979-12-18 | National Semiconductor Corporation | Laser trim protection process |
US5306942A (en) * | 1989-10-11 | 1994-04-26 | Nippondenso Co., Ltd. | Semiconductor device having a shield which is maintained at a reference potential |
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KR100294026B1 (en) * | 1993-06-24 | 2001-09-17 | 야마자끼 순페이 | Electro-optical device |
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US5986331A (en) * | 1996-05-30 | 1999-11-16 | Philips Electronics North America Corp. | Microwave monolithic integrated circuit with coplaner waveguide having silicon-on-insulator composite substrate |
JP2001517874A (en) * | 1997-09-19 | 2001-10-09 | フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ. | Semiconductor element wiring method for preventing product plagiarism and product operation, semiconductor element manufactured by this method, and method of using semiconductor element in chip card |
JP3583633B2 (en) * | 1998-12-21 | 2004-11-04 | シャープ株式会社 | Method for manufacturing semiconductor device |
DE50013722D1 (en) * | 1999-05-03 | 2006-12-21 | Infineon Technologies Ag | METHOD AND DEVICE FOR SECURING A MULTI-DIMENSIONALLY BUILT CHIP STACK |
DE19940759B4 (en) * | 1999-08-27 | 2004-04-15 | Infineon Technologies Ag | Circuit arrangement and method for the production thereof |
DE10003112C1 (en) * | 2000-01-13 | 2001-07-26 | Infineon Technologies Ag | Chip with all-round protection of sensitive circuit parts against access by unauthorized persons by means of shielding arrangements (shields) using an auxiliary chip |
JP3604002B2 (en) * | 2000-06-02 | 2004-12-22 | シャープ株式会社 | Semiconductor device |
JP2002353424A (en) * | 2001-03-23 | 2002-12-06 | Seiko Epson Corp | Method of manufacturing for substrate device, substrate device, method of manufacturing for electro-optical device, electro-optical device and electronic unit |
-
2001
- 2001-02-08 DE DE10105725A patent/DE10105725B4/en not_active Expired - Fee Related
-
2002
- 2002-02-08 DE DE50212016T patent/DE50212016D1/de not_active Expired - Lifetime
- 2002-02-08 AT AT02714001T patent/ATE391343T1/en not_active IP Right Cessation
- 2002-02-08 WO PCT/DE2002/000470 patent/WO2002063687A2/en active IP Right Grant
- 2002-02-08 EP EP02714001A patent/EP1358676B1/en not_active Expired - Lifetime
-
2003
- 2003-08-08 US US10/637,192 patent/US6919618B2/en not_active Expired - Fee Related
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US5424235A (en) * | 1990-09-10 | 1995-06-13 | Sony Corporation | Semiconductor memory device |
US5525531A (en) * | 1995-06-05 | 1996-06-11 | International Business Machines Corporation | SOI DRAM with field-shield isolation |
US5742082A (en) * | 1996-11-22 | 1998-04-21 | Motorola, Inc. | Stable FET with shielding region in the substrate |
US6310372B1 (en) * | 1997-12-25 | 2001-10-30 | Seiko Epson Corporation | Substrate for electro-optical apparatus, electro-optical apparatus, method for driving electro-optical apparatus, electronic device and projection display device |
US20020040998A1 (en) * | 1998-12-24 | 2002-04-11 | Hyundai Electronics Industries, Co., Ltd. | SOI semiconductor device capable of preventing floating body effect |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2893183A1 (en) * | 2005-11-10 | 2007-05-11 | Gemplus Sa | METHOD FOR PROTECTING AN ELECTRONIC COMPONENT AGAINST FAULT INJECTION ATTACKS |
WO2007057325A1 (en) * | 2005-11-10 | 2007-05-24 | Gemplus | Method for protecting an electronic component against fault-injection attacks |
EP2232412B1 (en) * | 2007-08-02 | 2019-03-06 | Nxp B.V. | Tamper-resistant semiconductor device and methods of manufacturing thereof |
US9653410B1 (en) | 2016-03-15 | 2017-05-16 | Nxp Usa, Inc. | Transistor with shield structure, packaged device, and method of manufacture |
EP3246943A1 (en) * | 2016-05-20 | 2017-11-22 | Commissariat à l'énergie atomique et aux énergies alternatives | Electronic device having puf-type identification |
US9741671B1 (en) | 2016-11-10 | 2017-08-22 | Nxp B.V. | Semiconductor die with backside protection |
US10593619B1 (en) | 2018-08-28 | 2020-03-17 | Nsp Usa, Inc. | Transistor shield structure, packaged device, and method of manufacture |
Also Published As
Publication number | Publication date |
---|---|
EP1358676A2 (en) | 2003-11-05 |
DE50212016D1 (en) | 2008-05-15 |
WO2002063687A2 (en) | 2002-08-15 |
WO2002063687A3 (en) | 2003-05-30 |
ATE391343T1 (en) | 2008-04-15 |
DE10105725B4 (en) | 2008-11-13 |
US6919618B2 (en) | 2005-07-19 |
DE10105725A1 (en) | 2002-09-05 |
EP1358676B1 (en) | 2008-04-02 |
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Owner name: INFINEON TECHNOLOGIES AG, GERMANY Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AUMULLER, CHRISTIAN;JANKE, MARCUS;HOFREITER, PETER;REEL/FRAME:016670/0399;SIGNING DATES FROM 20030806 TO 20030915 |
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STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
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Effective date: 20130719 |