WO1996016445A1 - Integrated circuit structure with security feature - Google Patents

Integrated circuit structure with security feature Download PDF

Info

Publication number
WO1996016445A1
WO1996016445A1 PCT/EP1995/004601 EP9504601W WO9616445A1 WO 1996016445 A1 WO1996016445 A1 WO 1996016445A1 EP 9504601 W EP9504601 W EP 9504601W WO 9616445 A1 WO9616445 A1 WO 9616445A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
integrated circuit
shielding layer
structure according
circuit structure
Prior art date
Application number
PCT/EP1995/004601
Other languages
French (fr)
Inventor
Andrew Beaumont
Original Assignee
Motorola Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB9423630A external-priority patent/GB9423630D0/en
Application filed by Motorola Ltd. filed Critical Motorola Ltd.
Publication of WO1996016445A1 publication Critical patent/WO1996016445A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention provides an integrated circuit structure having a top circuit layer including at least an essential functional portion of the circuit, a passivation layer provided on top of the top circuit layer and a shielding layer provided over at least a major portion of the passivation layer to prevent the top circuit layer from being analysed through the passivation layer, wherein each of the shielding layer and the passivation layer include at least one aperture, the apertures being aligned over the essential functional portion of the circuit so as to expose the top circuit layer.
  • the shielding layer is of a material having similar chemical properties to those of the essential functional portion of the top circuit layer so that, if the shielding layer is chemically acted upon, the top circuit layer is simultaneously chemically acted upon in a similar manner.
  • the shielding layer is optically and/or electrically obscuring or opaque.
  • the essential functional portion of the top circuit layer has electrically conductive portions, for example of conductive material, such as metal, or semiconductor material.
  • the shielding layer is of the same material as the essential functional portion of the top circuit layer.
  • the shielding layer is of electrically conductive material and is electrically coupled to the top circuit layer.
  • FIG. 1 shows a schematic plan view of an integrated circuit structure according to a first embodiment of the invention
  • FIG. 3 shows a cross-sectional view along line A- A through the portion of the structure shown in FIG. 2;
  • FIG.4 shows a second embodiment of the invention.
  • an integrated circuit 10 is formed with at least a top circuit layer 20 formed of a number of circuit elements 15 on a substrate layer 21.
  • a passivation layer 19 is provided on and around the circuit layer 20. It will be appreciated that there may be one or more further circuit layers below the substrate layer 21.
  • a shielding layer 18 is provided on the passivation layer 19 and a top passivation layer 17, for example of a silicon dioxide based material, is provided on the shielding layer 18.
  • an outline of the upper surface of the integrated circuit 10 is shown with the shielding layer 18 extending to that outline.
  • the shielding layer 18 is provided with first apertures 11 , below which the passivation layer 19 has corresponding apertures so as to expose wire bonding contact areas 12 on the top circuit layer 20.
  • the top passivation layer 17 does not extend over the contact areas 12, since they must be available to make contact with wires for electrical connection to the integrated circuit 10.
  • the shielding layer 18 is provided with apertures 13 which are formed over essential portions of the top circuit layer. As best shown in FIGS. 2 and 3, apertures 16 are also provided in the passivation layer 19 at positions corresponding to apertures 13 in shielding layer 18 so as to expose the top circuit layer 20. In this case, the top passivation layer 17 extends over the top circuit layer 20.
  • the shielding layer 18 is of a material which is opaque or oscuring to light so that the top circuit layer 20 below cannot be simply analysed by visible inspection, for example an aluminium based material, and may also or alternatively be of a material which prevents electrical analysis of the circuit layer 20 therethrough.
  • the passivation layer 19 may, again, be silicon dioxide based.
  • the top circuit layer 20 could again be aluminium based.
  • the substrate level 21 such as an interlevel dielectric layer 21 , for example of silicon dioxide based material, provides isolation from other active circuit elements in lower layers (which are not shown).
  • the top circuit layer 20 and the shielding layer could be of semiconductor material.
  • FIG. 2 there is shown one of the apertures 13 through the shielding layer 18 and the further aperture 16 through the passivation layer 19 exposing active circuit elements 15 of an essential portion of the top circuit layer 20. As explained above, this entire area is covered by the top passivation layer 17, although this is not shown in this FIG.
  • the bonding areas 27 of the top circuit layer 20 are then connected to the shielding layer 18 via further apertures 24 in the top passivation layer 17 corresponding to the apertures 13 and 16 over the essential portions of the top circuit layer 20 and apertures 23 in the top passivation layer 17 allowing connection to the shielding layer 18 using bonding wires 26 or anuy other type of electrical connection.
  • FIG. 4 also shows apertures 25 in the top passivation layer to allow electrical connection to be made to the contact areas 12, as mentioned above.
  • the connections between the shielding layer 18 and the top circuit layer 20 can be made before the top passivation layer 17 is applied, which can then cover the whole area, as in the previous embodiment.

Abstract

An integrated circuit (10) is formed with at least a top circuit layer (20) having a passivation layer (19) provided on and around the circuit layer (20). A shielding layer (18) is provided on the passivation layer (19) and a top passivation layer (17) is provided on the shielding layer (18). The shielding layer (18) and the passivation layer (19) are provided with respective corresponding apertures (13 and 16) which are formed over essential portions of the top circuit layer (20) so as to expose the top circuit layer (20). The top circuit layer (20) and the shielding layer (18) have the same or similar chemical properties and the shielding layer (18) is opaque to light so that the top circuit layer (20) cannot be simply analysed by visible inspection. Thus, attempts to remove the shielding layer (18) by chemical means, for example etching, will also remove or damage the top circuit layer (20) exposed through the apertures (16 and 13).

Description

INTEGRATED CIRCUIT STRUCTURE WITH SECURITY FEATURE
Field of the Invention This invention relates to integrated circuit structures and particularly to such structures which have enhanced security features.
Background of the Invention As is well known, integrated circuits are being used increasingly in all areas of life. In particular, integrated circuits are being utilised in many fields which require security, for example in banking, where integrated circuits may contain personal and financial confidential information and control access to sensitive information elsewhere. They often, therefore, contain secret codes and/or algorithms to restrict access only to authorised persons. In some cases, it has been known for such circuits to be analysed by unauthorised persons to try to gain knowledge of the codes or algorithms so as to gain unauthorised access to the sensitive and/or confidential information.
Consequently, it is an object of the present invention to try to reduce the ease with which such unauthorised analysis can be made.
Brief Summary of the Invention Accordingly, the invention provides an integrated circuit structure having a top circuit layer including at least an essential functional portion of the circuit, a passivation layer provided on top of the top circuit layer and a shielding layer provided over at least a major portion of the passivation layer to prevent the top circuit layer from being analysed through the passivation layer, wherein each of the shielding layer and the passivation layer include at least one aperture, the apertures being aligned over the essential functional portion of the circuit so as to expose the top circuit layer.
In a preferred embodiment, the shielding layer is of a material having similar chemical properties to those of the essential functional portion of the top circuit layer so that, if the shielding layer is chemically acted upon, the top circuit layer is simultaneously chemically acted upon in a similar manner. Preferably, the shielding layer is optically and/or electrically obscuring or opaque. ^Preferably, the essential functional portion of the top circuit layer has electrically conductive portions, for example of conductive material, such as metal, or semiconductor material. Preferably, the shielding layer is of the same material as the essential functional portion of the top circuit layer. In one embodiment, the shielding layer is of electrically conductive material and is electrically coupled to the top circuit layer.
Preferably, a further passivation layer is provided over the shielding layer and the exposed circuit layer. Preferably the structure is a single circuit layer structure.
Brief Description of the Drawings Two embodiments of the invention will now be more fully described, by way of example, with reference to the drawings, of which: FIG. 1 shows a schematic plan view of an integrated circuit structure according to a first embodiment of the invention;
FIG. 2 shows an enlarged view of a portion of the structure of FIG. 1 ;
FIG. 3 shows a cross-sectional view along line A- A through the portion of the structure shown in FIG. 2; and
FIG.4 shows a second embodiment of the invention.
Detailed Description As shown in the drawings, an integrated circuit 10 is formed with at least a top circuit layer 20 formed of a number of circuit elements 15 on a substrate layer 21. A passivation layer 19 is provided on and around the circuit layer 20. It will be appreciated that there may be one or more further circuit layers below the substrate layer 21. A shielding layer 18 is provided on the passivation layer 19 and a top passivation layer 17, for example of a silicon dioxide based material, is provided on the shielding layer 18.
As best shown in FIG. 1 , an outline of the upper surface of the integrated circuit 10 is shown with the shielding layer 18 extending to that outline. The shielding layer 18 is provided with first apertures 11 , below which the passivation layer 19 has corresponding apertures so as to expose wire bonding contact areas 12 on the top circuit layer 20. Of course the top passivation layer 17 does not extend over the contact areas 12, since they must be available to make contact with wires for electrical connection to the integrated circuit 10.
In addition to the apertures 11, the shielding layer 18 is provided with apertures 13 which are formed over essential portions of the top circuit layer. As best shown in FIGS. 2 and 3, apertures 16 are also provided in the passivation layer 19 at positions corresponding to apertures 13 in shielding layer 18 so as to expose the top circuit layer 20. In this case, the top passivation layer 17 extends over the top circuit layer 20. The shielding layer 18 is of a material which is opaque or oscuring to light so that the top circuit layer 20 below cannot be simply analysed by visible inspection, for example an aluminium based material, and may also or alternatively be of a material which prevents electrical analysis of the circuit layer 20 therethrough. The passivation layer 19 may, again, be silicon dioxide based. The top circuit layer 20 could again be aluminium based. The substrate level 21 , such as an interlevel dielectric layer 21 , for example of silicon dioxide based material, provides isolation from other active circuit elements in lower layers (which are not shown). Alternatively, the top circuit layer 20 and the shielding layer could be of semiconductor material.
Referring now to Fig. 2, there is shown one of the apertures 13 through the shielding layer 18 and the further aperture 16 through the passivation layer 19 exposing active circuit elements 15 of an essential portion of the top circuit layer 20. As explained above, this entire area is covered by the top passivation layer 17, although this is not shown in this FIG.
As will be apparent, if the top circuit layer 20 and the shielding layer 18 are of materials having the same or similar chemical properties, and more especially if they are of the same material, for example aluminium, then attempts to remove the shielding layer by chemical means, for example etching, will also remove or damage the circuit elements 15 of the essential portions of the top circuit layer 20 exposed through the apertures 16 and 13. Referring now to FIG. 4, an alternative embodiment of the invention is shown, where the shielding layer 18 has been made active by utilising the shielding layer, made of an electrically conductive material, as part of the circuit. In this embodiment, the apertures 13 and 16, as before, expose areas 27 of the top circuit layer 20. The active circuitry connected with each bonding area 27 is made reliant upon an electrical connection through the shielding layer 18 for operation. The bonding areas 27 of the top circuit layer 20 are then connected to the shielding layer 18 via further apertures 24 in the top passivation layer 17 corresponding to the apertures 13 and 16 over the essential portions of the top circuit layer 20 and apertures 23 in the top passivation layer 17 allowing connection to the shielding layer 18 using bonding wires 26 or anuy other type of electrical connection. FIG. 4 also shows apertures 25 in the top passivation layer to allow electrical connection to be made to the contact areas 12, as mentioned above. Alternatively, of course, the connections between the shielding layer 18 and the top circuit layer 20 can be made before the top passivation layer 17 is applied, which can then cover the whole area, as in the previous embodiment.
It will be appreciated that although only two particular embodiments of the invention have been described in detail, various modifications and improvements can be made by a person skilled in the art without departing from the scope of the present invention.

Claims

r Claims
1 . An integrated circuit structure having a top circuit layer including at least an essential functional portion of the circuit, a passivation layer provided on top of the top circuit layer and a shielding layer provided over at least a major portion of the passivation layer to prevent the top circuit layer from being analysed through the passivation layer, wherein each of the shielding layer and the passivation layer include at least one aperture, the apertures being aligned over the essential functional portion of the circuit so as to expose the top circuit layer.
2. An integrated circuit structure according to claim 1 , wherein the shielding layer is of a material having similar chemical properties to those of the essential functional portion of the top circuit layer so that, if the shielding layer is chemically acted upon, the top circuit layer is simultaneously chemically acted upon in a similar manner.
3. An integrated circuit structure according to claim 2, wherein the shielding layer is optically obscuring or opaque.
4. An integrated circuit structure according to either claim 2 or claim 3, wherein the shielding layer is electrically obscuring or opaque.
5. An integrated circuit structure according to any preceding claim, wherein the essential functional portion of the top circuit layer has electrically conductive portions.
6. An integrated circuit structure according to claim 5, wherein , the electrically conductive portions are of metal.
7. An integrated circuit structure according to claim 5, wherein, the electrically conductive portions are of semiconductor material.
8. An integrated circuit structure according to any preceding claim, wherein the shielding layer is of the same material as the essential functional portion of the top circuit layer.
9. An integrated circuit structure according to any preceding claim, wherein the shielding layer is of electrically conductive material and is electrically coupled to the top circuit layer.
10. An integrated circuit structure according to any preceding claim, wherein a further passivation layer is provided over the shielding layer and the exposed top circuit layer.
1 1 . Αn integrated circuit structure according to any preceding claim, wherein the structure is a single circuit layer structure.
PCT/EP1995/004601 1994-11-23 1995-11-22 Integrated circuit structure with security feature WO1996016445A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB9423630.4 1994-11-23
GB9423630A GB9423630D0 (en) 1994-11-23 1994-11-23 Intergrated circuit structure with security feature
GB9425570.0 1994-12-19
GBGB9425570.0A GB9425570D0 (en) 1994-11-23 1994-12-19 Integrated circuit structure with security feature

Publications (1)

Publication Number Publication Date
WO1996016445A1 true WO1996016445A1 (en) 1996-05-30

Family

ID=26306028

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1995/004601 WO1996016445A1 (en) 1994-11-23 1995-11-22 Integrated circuit structure with security feature

Country Status (1)

Country Link
WO (1) WO1996016445A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997047040A1 (en) * 1996-05-30 1997-12-11 Shellcase Ltd. I.c. device with concealed conductor lines
EP0981162A1 (en) * 1998-08-19 2000-02-23 Siemens Aktiengesellschaft Semiconductor chip with surface cover against optical inspection of the circuit structure
WO2002059964A2 (en) * 2001-01-24 2002-08-01 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in passivation layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0221351A1 (en) * 1985-10-22 1987-05-13 Siemens Aktiengesellschaft Integrated circuit with an electroconductive flat element
JPH01165129A (en) * 1987-12-21 1989-06-29 Sharp Corp Integrated circuit
JPH06204211A (en) * 1992-12-28 1994-07-22 Matsushita Electric Works Ltd Manufacturing method of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0221351A1 (en) * 1985-10-22 1987-05-13 Siemens Aktiengesellschaft Integrated circuit with an electroconductive flat element
JPH01165129A (en) * 1987-12-21 1989-06-29 Sharp Corp Integrated circuit
JPH06204211A (en) * 1992-12-28 1994-07-22 Matsushita Electric Works Ltd Manufacturing method of semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 013, no. 437 (E - 826) 29 September 1989 (1989-09-29) *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 556 (E - 1620) 24 October 1994 (1994-10-24) *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997047040A1 (en) * 1996-05-30 1997-12-11 Shellcase Ltd. I.c. device with concealed conductor lines
EP0981162A1 (en) * 1998-08-19 2000-02-23 Siemens Aktiengesellschaft Semiconductor chip with surface cover against optical inspection of the circuit structure
WO2002059964A2 (en) * 2001-01-24 2002-08-01 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in passivation layer
WO2002059964A3 (en) * 2001-01-24 2003-01-23 Hrl Lab Llc Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in passivation layer

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