WO2002059964A2

WO2002059964A2 - Integrated circuits protected against reverse engineering and method for fabricating the same using etched passivation openings in passivation layer

Info

Publication number: WO2002059964A2
Application number: PCT/US2002/002261
Authority: WO
Inventors: Lap-Wai Chow; James P. Baukus; William M. Clark, Jr.
Original assignee: Hrl Laboratories, Llc
Priority date: 2001-01-24
Filing date: 2002-01-24
Publication date: 2002-08-01
Also published as: US20020096744A1; AU2002236877A1; TW533533B; WO2002059964A3

Abstract

Semiconducting devices, including integrated circuits, are protected from reverse engineering by passivation openings made in a passivation layer. When a reverse engineeretches away the passivation layer and typically the first metal layer, underlying metallayers and/or other elements of the device are destroyed making the reverse engineeringall the more difficult. A method for fabricating such devices is also disclosed.

Description

INTEGRATED CIRCUITS PROTECTED AGAINST REVERSE ENGINEERING AND METHOD FOR FABRICATING THE SAME USING ETCHED PASSIVATION OPENINGS IN INTEGRATED CIRCUITS

I. BACKGROUND OF THE INVENTION

1. Field of the Invention.

This invention relates to the field of the prevention of reverse engineering of integrated circuits and/or making such reverse engineering so difficult and time-consuming as to make reverse engineering of integrated circuits non-feasible.

More particularly, this invention relates to using, in order to prevent and/or discourage such reverse engineering, openings etched in the passivation layer, typically, the uppermost insulating layer disposed atop an integrated circuit.

2. Description of the Related Art.

The design and development of semiconductor integrated circuits require a thorough understanding of the complex structures and processes and involve many man-hours of work requiring high skill, costing considerable sums of money.

In order to avoid these expenses, some developers stoop to the contentious practice of reverse engineering, disassembling existing devices manufactured by somebody else, and closely examining them to determine the physical structure of the integrated circuit, followed by copying the device. Thus, by obtaining a planar optical image of the circuits and by studying and copying them, the typically required product development efforts are circumvented. Such practices harm the true developer of the product and impairs its competitiveness in the market-place, because the developer had to expend significant amounts of resources for the development, while the reverse engineer did not have to.

A number of approaches have been used in order to frustrate such reverse engineering attempts, particularly in the field of semiconductor integrated circuits.

For instance, U.S. Patent No. 5,866,933 to Baukus, et. al. teaches how transistors in complementary metal oxide- semiconductor (CMOS) circuit can be connected by implanted, hidden and buried lines between the transistors. This hiding is achieved by modifying the p+ and n+ source/drain masks. The implanted interconnections are further used to make a 3 -input AND-circuit look substantially the same as a 3 -input OR-circuit.

Furthermore, US Patents Nos. 5,783,846 to Baukus, et. al. and 5,930,663 to Baukus et. al. teach a further modification in the source/drain implant masks, so that the implanted connecting lines between transistors have a gap inserted, the length of which is approximately the length of the feature size of the CMOS technology being used. These gaps are called "channel blocks."

If the gap is "filled" with one kind of implant (depending on whether the implanted connecting line is p or n), the line conducts; if another kind of implant is used for the gap- filling, the line does not conduct. The reverse engineer must determine connectivity on the basis of resolving the "n" or "p" implant at the minimum feature size of the chamiel block. In addition, transistor sizes and metal connection routings are modified, in order to deprive the reverse engineer of using clues which he can utilize to find inputs, outputs, gate lines and so on as keys to the circuit functionality.

Practicing the inventions taught in the above-mentioned patents to secure an integrated circuit causes the reverse engineer to perform steps that are not always needed. These steps include: decomposing the circuit layer by layer, careful processing of each layer

(which usually must include an etching step) followed by imaging of the layer with exact registration to other layers.

Once a particular standard circuit functionality has been determined, the reverse engineer will attempt to find some signature in the metal layers of that standard circuit which can exactly indicate the presence of that particular standard circuit in other places in the integrated circuit. If this can be done, that information can be entered into the reverse engineer's data base and automatic pattern recognition of the metal pattern is used to determine the circuit, without need for the extensive delayering. This would save considerable time and effort.

Therefore, there still exists a need for an inexpensive, easy-to-implement defensive method which can help to provide the enhanced protection against the reverse engineering of semiconductor integrated circuits, in particular to make such a signature impossible to determine. The present invention provides such a method.

II. SUMMARY OF THE INVENTION

Modern integrated circuits comprise a plurality of layers, such as metal layers, insulating layers, and other layers deposited and patterned to effect the circuit design. On the top of the integrated circuit there is provided a layer of passivating material, such as a layer of oxide or nitride or a series of layers of such materials, known in the art, is typically deposited in order to protect the integrated circuit from environmental degradation. The passivation layer typically has openings formed therein over metal pads formed in the highest metal layer. These openings are used to make electrical contact with the circuits formed on the integrated circuit via such pads. The contacts are made in the art by bonding small metal wires to the pads. The pad and wires are sufficiently large to resist environment degradation. However, the very fine conductors formed on the integrated circuit could be eaten away by environmental effects and therefore that are protected in the prior art by the aforementioned passivation layer. When a reverse engineer begins the process of reverse engineering, he typically etches away the passivation layer in order to be able to see the highest (from the top) level of metal. Then, he observes and records that metal layer data, followed by further etching in order to remove the that metal layer and the next oxide layer in order to observes and record the next metal layer data. The process is repeated through the various metal layers of the integrated circuit in question.

The gist of this invention is to provide at least one extra opening in the passivation layer, for example, an opening that is not required for a contact pad. In this case, normal, careful deprocessing by the reverse engineer will lead to the destruction of important elements and data because of the deeper etching that will occur in the region of the passivation opening. In other words, in order to learn the design of the integrated circuit, the reverse engineer cannot help destroying important portions of the circuit. This kind of protection will substantially assist in protecting the integrated circuit against reverse engineering.

A first aspect of the invention provides a semiconducting device adapted to prevent and/or to thwart reverse engineering, comprising an insulating layer disposed on a semiconductor substrate, a plurality of metal layers, said metal layers of said plurality being separated by said insulating layer, said plurality of said metal layers comprising a top metal layer and a number of lower metal layers disposed below said top metal layer, a passivation layer, said passivation layer being disposed on top metal layer of said plurality of said metal layers, and a passivation opening defined within said passivation layer, wherein said passivation opening has a location above one or more said lower metal layers, said location lying in a first vertical plane, and said top metal layer lying in a second vertical plane, said first vertical plane being spatially separated from said second vertical plane.

A second aspect of the invention provides a method for preventing and/or thwarting reverse engineering, comprising steps of providing an insulating layer disposed on a semiconductor substrate, providing a plurality of metal layers whereby said metal layers of said plurality are separated by said insulating layer, said plurality of said metal layers comprising a top metal layer and a number of lower metal layers disposed below said top metal layer, providing a passivation layer whereby said passivation layer is disposed on top metal layer of said plurality of said metal layers, and forming a passivation opening defined by said passivation layer, said passivation opening being provided at a location above one or more said lower metal layers, said location being spatially separated from said top metal layer.

III. BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where

Figure 1 a is schematic partial cross-section view through an integrated circuit device showing two metal layers of an integrated circuit separated by an oxide layer;

Figure lb is a plan view corresponding to Figure la;

Figure 2a schematic partial cross-section view through an integrated circuit device showing two metal layers of an integrated circuit separated by an oxide layer with extra openings formed in its passivation layer;

Figure 2b is a plan view corresponding to Figure 2a;

Figure 3 schematic partial cross-section view through an integrated circuit device showing two metal layers of an integrated circuit separated by an oxide layer and the effect of using an etchant to remove the passivation layer in the region of the extra openings formed therein;

Figure 3b is a plan view corresponding to Figure 3 a; and Figure 4 is a schematic diagram illustrating an embodiment of this invention wherein the protection against reverse engineering is utilized to disable the reading of the memory of a floating gate memory cell.

IN. DETAILED DESCRIPTION OF THE INVENTION

This invention can be used on any semiconducting device, including CMOS, bipolar silicon or group Ill-group V integrated circuits.

Figure 1 a shows a typical cross-section view of a part of a integrated circuit device having a plurality of metal layers. Figure lb is a plan view of the integrated circuit device. Top metal layer Ml and a next metal layer M2 are separated by an insulating layer 3, preferably, a silicon oxide layer. Each metal layer Ml and M2 preferably has a thickness of about 200 Angstroms and is preferably formed and patterned using conventional semiconductor fabrication techniques .The insulating layer 3 has a thickness preferably within a range of between 3,000 Angstroms and 5,000 Angstroms. Metal layer M2 is formed on an insulating layer 5 which in turned is usually disposed on or over other layers on a semiconducting substrate 8. Only two metal layers Ml and M2 are shown on Figures, la - 3a and lb - 3b for the purpose of illustrating the inventive concept; however, it should be understood that more than two metal layers are typically present and indeed many other metal layers may be present.

A passivation layer 4, preferably an oxide, a nitride or a polyimide, or a layered combination of such materials or similar materials, is deposited over the top metal layer Ml in order to protect the integrated circuit from environmental degradation. The thickness of the passivation layer 4 is preferably within a range of between 6000 Angstroms and 1 micrometer.

An opening is shown in passivation layer 4 at reference numeral 1. This opening is conventionally formed by a wet etch with the metal pad 2 formed by the Ml metal layer underneath acting as an etch stop. This etch exposes pad 2. Pad 2 is coupled by portions of the Ml layer to one or more circuits formed on the device. Those skilled in the art will appreciate that the integrated circuit device is connected up using small wires each of which are typically bonded to pad 2. A complex integrated circuit may have hundreds of pads 2 while a simple integrated circuit may have only a few pads 2. Metal layers 1 and 2 lie in different planes, the metal layer Ml being disposed on top of, and the metal layer M2 underneath, insulating layer 3.

The structure depicted by Figures la and lb is fabricated according to common manufacturing techniques known to those skilled in the art.

In accordance with the present invention, at least one additional passivation opening 6 is etched in the passivation layer 4, as is shown, for example, by Figures 2a and 2b. The at least one additional passivation opening 6 is preferably fabricated using methods known to those skilled in the art and preferably at the same time that openings 1 are formed for pads 2. The at least one additional passivation opening 6 is preferably located directly over where metal of metal layer M2 occurs (or the metal of a lower metal layer occurs), but in an area which is preferably not directly over metal of metal layer Ml. In that way, the additional passivation openings 6 preferably do not expose metal of metal layer Ml to environmental degradation.

A reverse engineer will remove the passivation layer 4, typically, by etching the passivation layer 4 away, in order to be able to see the highest level metal layer Ml, followed by further etching to remove metal layer Ml and insulating layer 3 in order to see the next metal layer M2 and so forth.

When, as shown by Figures 3 a and 3b, following such practice, the reverse engineer etches the passivation layer 4 having at least one passivation opening 6 therein, in the region of the passivation opening the etchant will penetrate to and etch in the region 6' below the top metal layer Ml, thereby exposing portions 7 of the lower metal layer M2. When viewed in plan view (see Figure 3b), the reverse engineer thinks he or she is seeing only the metal of layer Ml and in actuality the reverse engineer sees layer Ml and portions 7 of layer M2. The real problem for the reverse engineer occur when he or she etches away layer Ml since the etching processing will also etch away the exposed portions 7 of layer M2. When the reverse engineer next etches away layer 3 to expose layer M2, the reverse engineer will not see a complete layer M2 since the previously exposed portions 7 thereof will then be missing.

If the integrated circuit has hundreds or even thousands of openings 6 formed therein, layer M2, when exposed, will be literally like swiss cheese. The reverse engineer will have a problem (many problems actually) which, with time, can possibly be resolved. But reverse engineer does not want to spend a lot of time such efforts. The more time the reverse engineer spends hunting down problems the higher the likelihood that the reverse engineer will quit trying to reverse engineer the integrated circuit in question.

The size of the passivation opening is preferably not so large as to negatively impact the normal operation of the integrated circuit (i.e., causing corrosion), yet large enough to cause the perforation of the metal layer M2 beneath when an attempt to reverse engineer is undertaken. A typical passivation opening 6 could be a rectangular with a size of a side between about 1 micrometer and about 3 micrometers. However, the size of the opening 6 could be larger (or smaller) and the shape of the opening 6 in plan view is a matter of design choice. Any shape should work. The minimum size of openings 6 is dictated by the reflowability characteristics of the passivation layer 4 which is utilized. The size of openings 6 can be small or larger than the size of the openings 1 for pads 2.

As a result of his or her efforts, the reverse engineer inevitably will have made a perforated mess of metal layer M2 and the information the metal layer M2 contained will be all that much more difficult to reconstruct. Lower metal layers should be similarly affected as the reverse engineering continues his or her efforts. If the metal layers can be perforated, then by placing the passivation openings 6 in sufficiently strategic places, the pattern recognition approach, which the reverse engineer likes to use, can be really confused. Repeating circuits (circuit signatures) can be perforated in slightly different ways, giving the repeating circuits many different signatures.

Alternative embodiments of this invention utilize the same concept and envision making the passivation opening 6 over metal layers or over other conductive layers below the lower metal layer M2.

Yet another embodiment uses the same basic concept is to disable reading of memory such as, for example, electrically erasable programmable read only memory (EEPROM). In this case the polycrystalline silicon ("poly") level where the charge is stored is etched, thus discharging the memory bit. See Figure 4 which shows the floating gate PI and the control gate P2 of such a device. Data is stored in the device be placing a charge on floating gate P2. If at least one opening 6 in the passivation layer (a projection of opening 6 in the passivation layer is shown by the dotted outline 6 on insulating layer 10 between poly layers PI and P2) occurs over a floating gate, the then floating gate will discharge when it is etched and it will etch sooner than the reverse engineer expects due to the presence of opening 6 in the passivation layer 4 (which shown in Figure 2a for example).

According to this embodiment, shown on Figure 4, the structure comprises two poly layers PI and P2, each having a thickness of preferably about 1 micrometer and each separated by an appropriate insulator 10, preferably, an oxide or a nitride, having a thickness of preferably about 300 Angstroms. The structure also has a gate oxide layer 9, preferably having a thickness of about 100 Angstrom, an oxide area and N+ and P- areas as shown by Figure 4. The device typically has a metal bit line and a metal word line (not shown). The word and bit lines connect to the memory cell and one or more openings 6 in passivation layer 4 could also be used in connection with them as well.

An opening in the passivation, placed about 1 micrometer from the memory cell, and not necessarily over the bit or the word lines, will enable the etchant to go rapidly down into the device and etch the poly layer(s). In particular, when the lowest poly layer PI is etched, the charge on this so-called floating gate (which charge is the stored memory bit) is removed. As a result, the reverse engineer is prevented from reading the memory contents. In this embodiment, the passivation openings are placed slightly offset from each memory cell.

While metal layers are commonly used in integrated circuit devices and the present invention has been described in connection with same, the present invention need not be used with metal conductors. The present invention can be used to perforate or destroy any signal Having described the invention in connection with several embodiments thereof, modification will now suggest itself to those skilled in the art. As such, the invention is not to be limited to the described embodiments except as required by the appended claims.

Claims

CLAIMS WE CLAIM:

1. A semiconducting device adapted to prevent and/or to inhibit reverse engineering, comprising: (a) an insulating layer disposed on a semiconductor substrate;

(b) a plurality of metal layers, said metal layers of said plurality being separated by said insulating layer, said plurality of said metal layers comprising a top metal layer and at least one lower metal layer disposed below said top metal layer;

(c) a passivation layer, said passivation layer being disposed above the top metal layer of said plurality of said metal layers; and

(d) at least one passivation opening defined within said passivation layer, wherein said at least one passivation opening is spaced laterally from com ection pads of said top metal layer.

2. The device as claimed in Claim 1, wherein said semiconducting device comprises integrated circuits.

3. The device as claimed in Claim 2, wherein said integrated circuits further comprise complementary metal oxide- semiconductor, bi-polar silicon, or group Ill-group V integrated circuits.

4. The device as claimed in Claims 1, 2 or 3, wherein said at least one passivation opening is directly over metal in one or more of said lower metal layers.

5. The device as claimed by any one of the preceding claims, wherein said insulating layer further comprises silicon oxide.

6. The device as claimed by any one of the preceding claims, wherein said passivation layer further comprises either an oxide, a nitride, or a polyimide, or a combination thereof.

7. The device as claimed by any one of the preceding claims, wherein said semiconducting devices further comprise electrically erasable programmable read only memory.

8. The device as claimed in by any one of the preceding claims, wherein said insulating layer has a thickness within a range of between about 3,000 Angstroms and about 5,000

Angstroms.

9. The device as claimed by any one of the preceding claims, wherein said metal layers have a thickness of about 200 Angstroms each.

10. The device as claimed by any one of the preceding claims, wherein said passivation layer has a thickness within a range of between about 6000 Angstroms and about 1 micrometer.

11. A method for preventing and/or inhibiting reverse engineering, comprising steps of:

(a) providing at least one insulating layer on a semiconductor substrate;

(b) providing a plurality of metal layers whereby said plurality of metal layers are separated by said at least one insulating layer, said plurality of metal layers comprising a top metal layer and one or more lower metal layers disposed below said top metal layer;

(c) providing a passivation layer whereby said passivation layer is disposed above metal layer of said plurality of said metal layers; and

(d) forming one or more passivation openings in said passivation layer, said passivation openings being provided at locations arranged above metal in one of more of said metal lower layers, said locations being spatially separated from metal connection pads in said top metal layer.

12. The method as claimed in Claim 11, whereby when a process of reverse engineering is conducted, said process including etching away the passivation layer, the etching of the passivation layer may allow said top metal layer may remain intact but at the same time exposes portions of at least one lower metal layer at one or more of said locations.

13. The method as Claimed in Claims 11, or 12, wherein said at least one passivation opening is directly over metal in one or more said lower metal layers.

14. The method as claimed in Claims 13, wherein said semiconducting device comprises an integrated circuit.

15. The method as claimed in Claim 13, wherein said integrated circuits further comprise complementary metal oxide-semiconductor, bi-polar silicon, or group Ill-group V integrated circuits.

16. The method as claimed in Claims 11 or 12, wherein said semiconducting devices further comprise electrically erasable programmable read only memory.

17. The method as Claimed in Claim 16, wherein portions of said semiconducting devices are destroyed during revere engineering, the portions being destroyed including a floating gate structure of the electrically erasable programmable read only memory.

18. The method as claimed in any one of claims 11 - 17, wherein said insulating layer comprises silicon oxide.

19. The method as claimed in any one of claims 11 - 18 wherein said passivation layer comprises an oxide and/or a nitride.

20. The method as claimed in any one of claims 11 - 19, wherein said insulating layer has a thickness within a range of between about 3,000 Angstroms and about 5,000 Angstroms.

21. The method as claimed in any one of claims 11 - 20, wherein said metal layers have a thickness of about 200 Angstroms each.

22. The method as claimed in any one of claims 11 - 21, wherein said passivation layer has a thickness within a range of between about 6000 Angstroms and about 1 micrometer.