JP2001284357A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make illegal copy and pattern analysis difficult by adding dummy wirings. SOLUTION: The semiconductor device is composed of a semiconductor substrate and a plurality of mutilayered metal wiring layers, formed on the substrate for interconnecting a plurality of circuit elements formed on the substrate. Many dummy wirings 50, 52 are formed on one upper metal wiring layer among the metal wiring layer, utilizing empty regions 36, 38 of real wiring patterns 24, 28 formed on the one wiring layer. The dummy wirings utilize quasi-wiring patterns, resembling compact patterns of the real wiring patterns or resembling the real wiring patterns. The dummy wirings make difficult strict distinction between the real and dummy wiring patterns, thereby preventing the illegal copying by optical reverse engineering or the circuit analysis for illegal use.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device applicable to an LSI chip having a multi-layer wiring layer. More specifically, by forming a dummy wiring portion by using a vacant area of the actual wiring pattern formed in the multilayer wiring layer, it is possible to prevent illegal copying by optical reverse engineering and circuit analysis for the purpose of unauthorized use. It was made.

[0002]

2. Description of the Related Art The so-called reverse engineering of illegally analyzing the contents of a specific semiconductor chip by companies and individuals without proper rights has prevailed, and the case of manufacturing and selling functional equivalents without permission has been unprecedented. Absent. These pirate traders illegally copy functional equivalents to illegally sell copies of genuine equipment, so-called pirate goods, without having the proper right, or to protect against copy protection circuits embedded in semiconductor chips. Many cases have been developed in which an evasion device has been developed and illegal content has been illegally copied and sold as legitimate content that should only operate on legitimate equipment.

In order to prevent such a reverse engineering attack, various measures have been taken to make analysis from the surface of a semiconductor chip difficult. A typical example of such a method is a multilayer metal wiring structure. The use of multi-layer metal wiring makes it difficult to analyze the wiring structure with a microscope.

A multilayer metal wiring method will be described with reference to FIG. FIG. 8 is a cross-sectional view of the LSI chip 10 having a multilayer wiring layer, which is a very rough conceptual diagram. This LSI
The chip 10 has a semiconductor substrate (N-type or P-type substrate) 12, and a large number of circuit elements 16 and 18 of the same type or different types are formed from the front surface side thereof to form a circuit element section 14. In the circuit element section 14, a large number of transistors, diodes, resistance layers, capacitor elements, and insulators 20 are formed so as to be integrated at a very high density.

[0005] A plurality of wiring layers having a multilayer structure are formed on the front side of the semiconductor substrate 12. Usually, there are many cases of four or more layers, but in the example of the figure, a two-layer structure is exemplified. First layer 22
Is provided with an insulating layer 23 having a predetermined thickness such as SiO2 on the surface of the semiconductor substrate 12, and a first metal wiring layer (actual wiring pattern layer) 24 using aluminum or the like is deposited on the surface of the insulating layer 23. It is formed by using such a technique.
A plurality of through-holes 26 are formed at appropriate locations for electrical connection between the first metal wiring layer 24 and the circuit element section 14, thereby forming the circuit element section 1.
Contact with 4 is made.

A second layer 28 is further formed on the upper surface of the first layer 22 by a similar method. That is, the insulating layer 29 having an appropriate thickness is provided, and the second metal wiring layer 30 is formed on the surface of the insulating layer 29. The second metal wiring layer 30 is also a real wiring pattern, and the first metal wiring layer 30 is provided on the first layer 22.
A plurality of through holes 32 are formed in order to make contact with the metal wiring layer 24 or the circuit element portion 14 thereunder. The surface of the second layer 28 is covered with a protective layer 33 such as SiO2.

One example of actual wiring patterns provided on the first layer 22 and the second layer 28 is shown in FIG. As the first metal wiring layer 24 formed on the first layer 22 shown in FIG. 9, as shown in the figure, a wiring pattern of a metal layer mainly composed of wiring in the horizontal direction is shown.

As the second metal wiring layer 30 provided on the second layer 28 laminated on the first layer 22, as shown in FIG. 10, a wiring pattern of a metal layer mainly in the vertical direction is shown. When the first and second metal wiring layers 24 and 30 are overlapped, they are as shown in FIG.

The multilayer wiring structure as described above makes it possible to reduce the chip area, and makes the analysis of the metal wiring layer difficult due to the multilayer structure.

As another method, a method of covering the entire upper surface of the semiconductor chip (the protective layer 33 in FIG. 8) with a metal layer is considered. The protective layer 33 makes optical pattern analysis and circuit analysis using a microscope difficult.

[0011]

However, even in the case of the multi-layer metal wiring which is the first technique, the metal wiring layer formed on the first layer 22 or the second layer 28 using a bifocal microscope is used. When observing 24, 30 and the like, the plurality of metal wiring layers 24, 30 can be observed at the same time, so that the metal wiring state of each layer can be analyzed. Therefore, the multilayer metal wiring method is not so effective.

[0012] Further, since a technique of analyzing a metal wiring pattern for each layer by using a technique of dissolving only the upper layer without using a microscope has appeared, a multilayer metal wiring method is also an effective prevention means. Hard to say.

In the second method, in which the uppermost layer is covered with a metal layer, only the uppermost layer can be dissolved by etching, so that there is no protection against etching analysis. Further, the addition of the dedicated wiring layer in this manner increases the number of masks and the number of manufacturing steps in the semiconductor manufacturing process, and thus has a problem of increasing the cost.

In view of the above, the present invention has solved such a conventional problem. In a semiconductor device having a multi-layered metal wiring structure, by embedding a dummy wiring portion in each metal wiring layer, it is possible to obtain an optical or chemical structure. An object of the present invention is to propose a semiconductor device which makes it difficult to analyze a metal wiring layer and can protect against illegal copying and illegal circuit analysis.

[0015]

In order to solve the above-mentioned problems, in a semiconductor device according to the present invention, a semiconductor substrate is connected to a plurality of circuit elements formed on the semiconductor substrate. Therefore, a plurality of multi-layered metal wiring layers formed on the semiconductor substrate are provided, and the upper metal wiring layer of the metal wiring layers has an empty area of the actual wiring pattern formed on the metal wiring layer. , A large number of dummy wiring portions are formed.

According to the present invention, a large number of dummy wiring portions are formed by utilizing the empty area of the actual wiring pattern formed on the metal wiring layer (first or second layer) functioning as a multilayer wiring layer. This dummy wiring portion is formed in the upper and lower metal wiring layers. Since the upper and lower metal wiring layers overlap, it is observed that the dummy wiring part functions as a contact pattern of the metal wiring layer,
There is a high possibility that the dummy wiring portion itself is determined to be the same as the actual wiring pattern. This is because there is a high possibility that the pattern wiring is regarded as a pattern wiring similar to the actual wiring pattern. Therefore, it is difficult to analyze the actual wiring pattern, and there is an effect that it is possible to suppress the traffic of illegal copy and the traffic of circuit analysis for the purpose of illegal use.

[0017]

Next, an embodiment of a semiconductor device having a multilayer wiring structure according to the present invention will be described in detail with reference to the drawings. Also in the present invention, a semiconductor device such as an LSI chip employing a multilayer wiring structure is exemplified as a semiconductor device.

FIG. 1 is a cross-sectional view of the semiconductor device 10, which is a very conceptual diagram like the conventional example of FIG.

This semiconductor device 10 also has a semiconductor substrate 12
And a large number of circuit element portions 14 formed on the semiconductor substrate 12 and a plurality of wiring layers for electrically connecting the plurality of circuit elements. In the case of FIG. 1 as well, a two-layer structure is exemplified as the multilayer wiring layer for convenience of explanation.

In the LSI chip 10 shown in FIG.
It has a semiconductor substrate 12 made of silicon or the like, and a large number of circuit elements are incorporated at a high density on the surface side thereof to form a circuit element section 14. A first layer 22 and a second layer 28 are provided for pattern connection to the circuit element portion 14. The first layer 22 is an insulating layer 23 such as SiO2 having a predetermined thickness.
And a first metal wiring layer (actual wiring pattern) 24 formed on the upper surface thereof. The insulating layer 23 has a plurality of through holes 26 for making contact with the circuit element portion 14.
Are drilled. Similarly, an insulating layer 29 made of SiO2 is provided on the second layer 28, and a second metal wiring layer (actual wiring pattern) 30 is formed on the upper surface thereof by a method such as a vapor deposition and etching process.

In the present invention, the dummy wiring portions (40, 42) are formed by utilizing the free areas of the metal wiring layers 24, 30 which are the actual wiring patterns formed on the first layer 22 and the second layer 28, respectively. It is formed.

As the dummy wiring section, at least two types of wiring forms can be considered. The first dummy wiring portion is a case where a tile-shaped pattern portion having the same shape as a contact pattern portion provided in an actual wiring pattern is formed so as to be embedded in a plurality of empty areas. In this case, a plurality of pseudo wiring pattern layers similar to the actual wiring pattern are formed by burying them in the empty area.

The embodiments shown in FIGS. 2 to 4 show a case where a tile-shaped pattern portion is used, and the embodiments shown in FIGS. 5 to 7 show a case where a dummy wiring pattern portion is used. The embodiment described below is a case where the present invention is applied to a semiconductor device having a two-layer structure, and the first metal wiring layer 24 is a metal wiring layer mainly composed of horizontal wirings. The second metal wiring layer 30 is a semiconductor device (LSI) mainly formed as a metal wiring layer mainly composed of vertical wiring.
The case where the present invention is applied to the chip 10 will be described. Therefore, the patterns of the metal wiring layers 24 and 30 are the patterns shown in FIGS. 9 and 10 described as a conventional example.

A description will be given of the first metal wiring layer 24 formed on the first layer 22 with reference to FIG. FIG. 2 shows an empty area (gap) 36 existing in the first metal wiring layer 24 (FIG. 9).
Is used, a plurality of tile-shaped pattern portions 40 selected to be the same or similar to the contact pattern of the actual wiring pattern based on a certain rule are inserted.
In the case of FIG. 2, each of the metal wiring layers 24a, 24b, 24
, a plurality of tile-shaped pattern portions 40 such that the empty region 36 sandwiched between the c.
Is formed.

The above-mentioned certain rule for forming the tile-shaped pattern portion 40 is the same shape as the free space 36 within the range of the design rule (metal wiring layer forming rule) applied in the manufacturing process of the semiconductor device 10. The rule for embedding the dummy pattern is described.

The embedding of the tile pattern portion 40 is automatically generated by using dedicated software after the normal layout design is completed. Or generate it manually. However, when it is determined how to embed the tile pattern part 40, the wiring pattern of the entire FIG. 2 including the tile pattern part 40 can be formed all at once using the same mask. There is no increase in the number of manufacturing steps by providing the pattern section 40.

The dummy wiring portion is also buried in the second layer 28 by utilizing the empty area of the actual wiring pattern. FIG.
1 shows an embodiment of the present invention, in which a plurality of metal wiring layers 30 (30a, 30b,...) Arranged in a vertical direction have a plurality of The tile pattern portion 42 is embedded based on a certain rule.

Here, the certain rule refers to a dummy having the same shape in the empty area 38 within the range of the design rule (rule for forming a metal wiring layer) applied in the manufacturing process of the semiconductor device 10 as described above. Say the rules for embedding patterns.

When a plurality of tile-shaped pattern portions 42 are buried in the free space 38 in accordance with such a rule, a wiring pattern as shown in FIG. 3 is obtained as a whole. Therefore, when the first layer 22 and the second layer 28 are overlapped, a wiring pattern as shown in FIG. 4 is obtained.

FIG. 4 shows an example in which the tile pattern portion 40 formed on the first layer 22 and the tile pattern portion 42 formed on the second layer 28 are laid out so as not to completely overlap. However, it is also possible to arrange the tile pattern portions 40 and 42 so as to completely overlap.

As is clear from comparison of this wiring pattern with the conventional wiring pattern shown in FIG. 11, the wiring according to the present invention is much more complicated. Therefore, the difficulty of analyzing the wiring pattern is much higher in FIG. 2 than in FIG. 9 or in FIG. 3 than in FIG.
This is because the pattern shape of the dummy wiring portions 40 and 42 is similar to the shape of the contact pattern provided in the actual wiring pattern, so that the metal wiring layer will be analyzed optically using a bifocal microscope or the like. This is because it becomes difficult to determine which metal wiring layer is a proper metal wiring layer.

FIG. 5 et seq. Show an embodiment in which a dummy wiring pattern is used as a dummy wiring portion. That is,
As the dummy wiring portion, a pseudo wiring pattern having the same or similar pattern as the actual wiring pattern is used.
This pseudo wiring pattern is embedded in each free area.

In this embodiment, as the first metal wiring layer 24, a metal wiring layer mainly composed of the horizontal wiring shown in FIG. 9 is used, and the second metal wiring layer 24 is used. Reference numeral 30 denotes a case where the present invention is applied to a multilayer wiring layer in which a metal wiring layer mainly composed of vertical wirings shown in FIG. 10 is used.

Also in this embodiment, the actual wiring patterns 24 (24a, 24b, 24c,.
The dummy wiring section 50 (50a, 50) formed of a pseudo wiring pattern (fake wiring pattern) similar to the real wiring pattern 24 based on a certain rule in the empty area 36
, 50c,...) are embedded.

In the example of FIG. 5, in addition to the straight line pattern, a straight line pattern having a branch pattern and a bent pattern are laid out as the actual wiring pattern 24, but only the straight line pattern is used as the pseudo wiring pattern. I have. Of course, similarly to the actual wiring pattern, the dummy wiring portion 50 can be configured by selectively using a linear pattern or a bent pattern having a branch pattern according to the shape of the empty area 36.

The above-mentioned certain rule means that, within a range of a design rule (metal wiring layer forming rule) applied in a semiconductor manufacturing process, a free area has a shape similar to a regular wiring pattern existing in an area to be embedded. A rule for embedding a pseudo wiring pattern.

The generation and embedding of the pseudo wiring pattern are automatically generated by using dedicated software after the normal layout design is completed. Or generate it manually. Since the embedding of the pseudo wiring pattern can be performed in the same step as the actual wiring pattern, a dedicated process for embedding the pseudo wiring pattern is not required.

As shown in FIG. 6, the pseudo wiring pattern is also formed in the second layer 28 on the basis of the same rule as described above, and is formed by a dummy wiring part 52 composed of a pseudo wiring pattern (a deceptive wiring pattern) similar to the real wiring pattern 30. (52a, 52
, 52c,...) are embedded in the free space 38.

In the embodiment shown in FIG. 6, the dummy wiring section 50 is formed by using a pseudo wiring pattern composed of a straight pattern or a bent pattern having a branch pattern according to the shape of the empty area 38.

The first layer 22 and the second layer 28 are overlapped,
If this is seen through from above, a wiring pattern as shown in FIG. 7 is obtained. As is clear from comparison of these wiring patterns, it can be seen that the degree of wiring inclusion is much greater in FIG. 5 or FIG. 6 than in FIG. 9 or FIG. 10 without the dummy pattern. . Therefore, FIG.
6 or FIG. 6 is much more difficult to analyze the wiring pattern than FIG.

Since the pattern shape of the pseudo wiring pattern is similar to the pattern shape of the actual wiring pattern, even if the metal wiring layer is analyzed optically using a bifocal microscope or the like, any metal This is because it is difficult to determine whether the wiring layer is a regular wiring layer. Since the wiring pattern itself is much more complicated than when a tiled dummy pattern is used, pattern analysis and circuit analysis are more difficult than in the case of FIG.

In the case of using this pseudo wiring pattern, it becomes difficult to analyze a proper wiring pattern even by using chemical means such as etching. Therefore, countermeasures for preventing illegal copying and the like. Is extremely effective.

As described above, according to the present invention, only the dummy wiring portion is originally added to the empty area of the normal metal wiring layer, so that the number of masks for the etching process and the number of processes at the time of manufacturing are increased. There is no. Therefore, there is no influence on the manufacturing cost or the manufacturing TAT (Turn Around Time).

In general, filling a vacant region of a metal wiring layer with a metal layer also contributes to flattening of a layer surface which is most important in a multilayer wiring process. This is because embedding the dummy wiring layer reduces irregularities on the metal surface. This is because a special process called chemical mechanical polishing (CMP) is usually applied to address this problem, and this special process may be omitted by adding a dummy wiring layer.

If this special process is omitted, both the fixed cost and the number of manufacturing steps can be reduced in the semiconductor manufacturing process, leading to a significant cost reduction.

[0046]

As described above, according to the present invention, a dummy wiring layer is added to a vacant area of a metal wiring layer, and preferably, the dummy wiring layer has a multilayer wiring structure. According to this, the following effects can be obtained. (1) Due to the presence of the dummy wiring layer, optical analysis using a microscope or the like for illegal copying can be made extremely difficult. (2) It is possible to cope with fraudulent analysis using chemical etching. (3) Since the dummy wiring layer is added by using the empty area of the metal wiring layer, the number of masks and the number of steps do not increase, so that a high defense that can cope with illegal copying without increasing the cost can be exhibited. (4) Since the surface of the metal wiring layer can be flattened by adding a dummy wiring layer to an empty area of the metal wiring layer, a surface flattening process such as CMP can be omitted. If it can be omitted, both the fixed manufacturing cost and the number of manufacturing steps in the semiconductor manufacturing process can be reduced, so that the semiconductor manufacturing cost can be significantly reduced.

Therefore, the semiconductor device according to the present invention
It is extremely suitable to be applied to a semiconductor chip such as an LSI or a super LSI employing a multilayer wiring structure.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view used for conceptual explanation showing one embodiment when a semiconductor device according to the present invention is applied to a semiconductor device having a multilayer wiring structure.

FIG. 2 is a first-layer wiring pattern diagram showing an embodiment when applied to a semiconductor device having a multilayer wiring structure.

FIG. 3 is also a wiring pattern diagram of a second layer to which the present invention is applied.

FIG. 4 is a perspective view of a wiring pattern when a first layer and a second layer are overlapped.

FIG. 5 is a first layer wiring pattern diagram showing another embodiment when the semiconductor device according to the present invention is applied to a semiconductor device having a multilayer wiring structure.

FIG. 6 is also a wiring pattern diagram of a second layer to which the present invention is applied.

FIG. 7 is a perspective view of a wiring pattern when a first layer and a second layer are overlapped.

FIG. 8 is a cross-sectional view used for conceptual description of a conventional semiconductor device having a multilayer wiring structure.

FIG. 9 is a wiring pattern diagram of a first layer provided in the semiconductor device having the multilayer wiring structure.

FIG. 10 is also a wiring pattern diagram of a second layer.

FIG. 11 is a perspective view of a wiring pattern when a first layer and a second layer are overlapped.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device (LSI chip), 12 ... Semiconductor substrate, 14 ... Circuit element part, 22 ... First layer for multilayer wiring, 24 ... First metal wiring layer (actual) ... Second wiring, 30... Second metal wiring layer, 40, 42... Dummy wiring part (tile-shaped pattern part), 50, 52. Wiring pattern)

Claims (5)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate; and a plurality of multilayer metal wiring layers formed on the semiconductor substrate for connecting a plurality of circuit elements formed on the semiconductor substrate. A semiconductor device, wherein a number of dummy wiring portions are formed in a metal wiring layer in an upper layer portion by utilizing an empty area of an actual wiring pattern formed in the metal wiring layer. 2. The method according to claim 1, wherein when the dummy wiring portions are formed in the upper and lower metal wiring layers, a mutual positional relationship is selected so that the upper and lower dummy wiring portions do not completely overlap. The semiconductor device according to claim 1, wherein: 3. The semiconductor device according to claim 1, wherein said dummy wiring section is constituted by a plurality of tile-shaped pattern sections having the same shape. 4. The semiconductor device according to claim 1, wherein the dummy wiring section is a dummy wiring pattern that is the same as or similar to the actual wiring pattern. 5. The semiconductor device according to claim 3, wherein said dummy wiring portion is the same contact pattern portion as a pattern of a contact portion of said real wiring pattern.